2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
25 #include <asm/system.h>
26 #include <asm/arch/hardware.h>
27 #include <asm/arch/sys_proto.h>
28 #include <linux/errno.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 /* Bit/mask specification */
33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
47 /* Wrap bit, last descriptor */
48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
57 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
59 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
60 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
61 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
62 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
64 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
66 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
70 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
72 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
75 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
76 ZYNQ_GEM_NWCFG_FDEN | \
77 ZYNQ_GEM_NWCFG_FSREM | \
78 ZYNQ_GEM_NWCFG_MDCCLKDIV)
80 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
82 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
83 /* Use full configured addressable space (8 Kb) */
84 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
85 /* Use full configured addressable space (4 Kb) */
86 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
87 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
88 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
90 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
91 ZYNQ_GEM_DMACR_RXSIZE | \
92 ZYNQ_GEM_DMACR_TXSIZE | \
95 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
97 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
99 /* Use MII register 1 (MII status register) to detect PHY */
100 #define PHY_DETECT_REG 1
102 /* Mask used to verify certain PHY features (or register contents)
103 * in the register above:
104 * 0x1000: 10Mbps full duplex support
105 * 0x0800: 10Mbps half duplex support
106 * 0x0008: Auto-negotiation support
108 #define PHY_DETECT_MASK 0x1808
110 /* TX BD status masks */
111 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
112 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
113 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
115 /* Clock frequencies for different speeds */
116 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
117 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
118 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
120 /* Device registers */
121 struct zynq_gem_regs {
122 u32 nwctrl; /* 0x0 - Network Control reg */
123 u32 nwcfg; /* 0x4 - Network Config reg */
124 u32 nwsr; /* 0x8 - Network Status reg */
126 u32 dmacr; /* 0x10 - DMA Control reg */
127 u32 txsr; /* 0x14 - TX Status reg */
128 u32 rxqbase; /* 0x18 - RX Q Base address reg */
129 u32 txqbase; /* 0x1c - TX Q Base address reg */
130 u32 rxsr; /* 0x20 - RX Status reg */
132 u32 idr; /* 0x2c - Interrupt Disable reg */
134 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
136 u32 hashl; /* 0x80 - Hash Low address reg */
137 u32 hashh; /* 0x84 - Hash High address reg */
140 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
141 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
144 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
148 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
150 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
155 u32 addr; /* Next descriptor pointer */
160 /* Page table entries are set to 1MB, or multiples of 1MB
161 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
163 #define BD_SPACE 0x100000
164 /* BD separation space */
165 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
167 /* Setup the first free TX descriptor */
168 #define TX_FREE_DESC 2
170 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
171 struct zynq_gem_priv {
172 struct emac_bd *tx_bd;
173 struct emac_bd *rx_bd;
179 struct zynq_gem_regs *iobase;
180 phy_interface_t interface;
181 struct phy_device *phydev;
188 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
192 struct zynq_gem_regs *regs = priv->iobase;
195 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
200 /* Construct mgtcr mask for the operation */
201 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
202 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
203 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
205 /* Write mgtcr and wait for completion */
206 writel(mgtcr, ®s->phymntnc);
208 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
214 *data = readl(®s->phymntnc);
219 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
220 u32 regnum, u16 *val)
224 ret = phy_setup_op(priv, phy_addr, regnum,
225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
229 phy_addr, regnum, *val);
234 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
235 u32 regnum, u16 data)
237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
240 return phy_setup_op(priv, phy_addr, regnum,
241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
244 static int phy_detection(struct udevice *dev)
248 struct zynq_gem_priv *priv = dev->priv;
250 if (priv->phyaddr != -1) {
251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
252 if ((phyreg != 0xFFFF) &&
253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
254 /* Found a valid PHY address */
255 debug("Default phy address %d is valid\n",
259 debug("PHY address is not setup correctly %d\n",
265 debug("detecting phy address\n");
266 if (priv->phyaddr == -1) {
267 /* detect the PHY address */
268 for (i = 31; i >= 0; i--) {
269 phyread(priv, i, PHY_DETECT_REG, &phyreg);
270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
274 debug("Found valid phy address, %d\n", i);
279 printf("PHY is not detected\n");
283 static int zynq_gem_setup_mac(struct udevice *dev)
285 u32 i, macaddrlow, macaddrhigh;
286 struct eth_pdata *pdata = dev_get_platdata(dev);
287 struct zynq_gem_priv *priv = dev_get_priv(dev);
288 struct zynq_gem_regs *regs = priv->iobase;
290 /* Set the MAC bits [31:0] in BOT */
291 macaddrlow = pdata->enetaddr[0];
292 macaddrlow |= pdata->enetaddr[1] << 8;
293 macaddrlow |= pdata->enetaddr[2] << 16;
294 macaddrlow |= pdata->enetaddr[3] << 24;
296 /* Set MAC bits [47:32] in TOP */
297 macaddrhigh = pdata->enetaddr[4];
298 macaddrhigh |= pdata->enetaddr[5] << 8;
300 for (i = 0; i < 4; i++) {
301 writel(0, ®s->laddr[i][LADDR_LOW]);
302 writel(0, ®s->laddr[i][LADDR_HIGH]);
303 /* Do not use MATCHx register */
304 writel(0, ®s->match[i]);
307 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
308 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
313 static int zynq_phy_init(struct udevice *dev)
316 struct zynq_gem_priv *priv = dev_get_priv(dev);
317 struct zynq_gem_regs *regs = priv->iobase;
318 const u32 supported = SUPPORTED_10baseT_Half |
319 SUPPORTED_10baseT_Full |
320 SUPPORTED_100baseT_Half |
321 SUPPORTED_100baseT_Full |
322 SUPPORTED_1000baseT_Half |
323 SUPPORTED_1000baseT_Full;
325 /* Enable only MDIO bus */
326 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
328 if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
329 (priv->interface != PHY_INTERFACE_MODE_GMII)) {
330 ret = phy_detection(dev);
332 printf("GEM PHY init failed\n");
337 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
342 priv->phydev->supported &= supported | ADVERTISED_Pause |
343 ADVERTISED_Asym_Pause;
344 priv->phydev->advertising = priv->phydev->supported;
346 if (priv->phy_of_handle > 0)
347 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
349 return phy_config(priv->phydev);
352 static int zynq_gem_init(struct udevice *dev)
356 unsigned long clk_rate = 0;
357 struct zynq_gem_priv *priv = dev_get_priv(dev);
358 struct zynq_gem_regs *regs = priv->iobase;
359 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
360 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
363 /* Disable all interrupts */
364 writel(0xFFFFFFFF, ®s->idr);
366 /* Disable the receiver & transmitter */
367 writel(0, ®s->nwctrl);
368 writel(0, ®s->txsr);
369 writel(0, ®s->rxsr);
370 writel(0, ®s->phymntnc);
372 /* Clear the Hash registers for the mac address
373 * pointed by AddressPtr
375 writel(0x0, ®s->hashl);
376 /* Write bits [63:32] in TOP */
377 writel(0x0, ®s->hashh);
379 /* Clear all counters */
380 for (i = 0; i < STAT_SIZE; i++)
381 readl(®s->stat[i]);
383 /* Setup RxBD space */
384 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
386 for (i = 0; i < RX_BUF; i++) {
387 priv->rx_bd[i].status = 0xF0000000;
388 priv->rx_bd[i].addr =
389 ((ulong)(priv->rxbuffers) +
390 (i * PKTSIZE_ALIGN));
392 /* WRAP bit to last BD */
393 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
394 /* Write RxBDs to IP */
395 writel((ulong)priv->rx_bd, ®s->rxqbase);
397 /* Setup for DMA Configuration register */
398 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
400 /* Setup for Network Control register, MDIO, Rx and Tx enable */
401 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
403 /* Disable the second priority queue */
404 dummy_tx_bd->addr = 0;
405 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
406 ZYNQ_GEM_TXBUF_LAST_MASK|
407 ZYNQ_GEM_TXBUF_USED_MASK;
409 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
410 ZYNQ_GEM_RXBUF_NEW_MASK;
411 dummy_rx_bd->status = 0;
413 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
414 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
419 ret = phy_startup(priv->phydev);
423 if (!priv->phydev->link) {
424 printf("%s: No link.\n", priv->phydev->dev->name);
428 nwconfig = ZYNQ_GEM_NWCFG_INIT;
431 * Set SGMII enable PCS selection only if internal PCS/PMA
432 * core is used and interface is SGMII.
434 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
436 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
437 ZYNQ_GEM_NWCFG_PCS_SEL;
439 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
444 switch (priv->phydev->speed) {
446 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
448 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
451 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
453 clk_rate = ZYNQ_GEM_FREQUENCY_100;
456 clk_rate = ZYNQ_GEM_FREQUENCY_10;
460 ret = clk_set_rate(&priv->clk, clk_rate);
461 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
462 dev_err(dev, "failed to set tx clock rate\n");
466 ret = clk_enable(&priv->clk);
467 if (ret && ret != -ENOSYS) {
468 dev_err(dev, "failed to enable tx clock\n");
472 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
473 ZYNQ_GEM_NWCTRL_TXEN_MASK);
478 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
481 struct zynq_gem_priv *priv = dev_get_priv(dev);
482 struct zynq_gem_regs *regs = priv->iobase;
483 struct emac_bd *current_bd = &priv->tx_bd[1];
486 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
488 priv->tx_bd->addr = (ulong)ptr;
489 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
490 ZYNQ_GEM_TXBUF_LAST_MASK;
491 /* Dummy descriptor to mark it as the last in descriptor chain */
492 current_bd->addr = 0x0;
493 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
494 ZYNQ_GEM_TXBUF_LAST_MASK|
495 ZYNQ_GEM_TXBUF_USED_MASK;
498 writel((ulong)priv->tx_bd, ®s->txqbase);
501 addr &= ~(ARCH_DMA_MINALIGN - 1);
502 size = roundup(len, ARCH_DMA_MINALIGN);
503 flush_dcache_range(addr, addr + size);
505 addr = (ulong)priv->rxbuffers;
506 addr &= ~(ARCH_DMA_MINALIGN - 1);
507 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
508 flush_dcache_range(addr, addr + size);
512 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
514 /* Read TX BD status */
515 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
516 printf("TX buffers exhausted in mid frame\n");
518 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
522 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
523 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
527 struct zynq_gem_priv *priv = dev_get_priv(dev);
528 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
530 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
533 if (!(current_bd->status &
534 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
535 printf("GEM: SOF or EOF not set for last buffer received!\n");
539 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
541 printf("%s: Zero size packet?\n", __func__);
545 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
546 addr &= ~(ARCH_DMA_MINALIGN - 1);
547 *packetp = (uchar *)(uintptr_t)addr;
552 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
554 struct zynq_gem_priv *priv = dev_get_priv(dev);
555 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
556 struct emac_bd *first_bd;
558 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
559 priv->rx_first_buf = priv->rxbd_current;
561 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
562 current_bd->status = 0xF0000000; /* FIXME */
565 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
566 first_bd = &priv->rx_bd[priv->rx_first_buf];
567 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
568 first_bd->status = 0xF0000000;
571 if ((++priv->rxbd_current) >= RX_BUF)
572 priv->rxbd_current = 0;
577 static void zynq_gem_halt(struct udevice *dev)
579 struct zynq_gem_priv *priv = dev_get_priv(dev);
580 struct zynq_gem_regs *regs = priv->iobase;
582 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
583 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
586 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
591 static int zynq_gem_read_rom_mac(struct udevice *dev)
593 struct eth_pdata *pdata = dev_get_platdata(dev);
598 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
601 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
604 struct zynq_gem_priv *priv = bus->priv;
608 ret = phyread(priv, addr, reg, &val);
609 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
613 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
616 struct zynq_gem_priv *priv = bus->priv;
618 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
619 return phywrite(priv, addr, reg, value);
622 static int zynq_gem_probe(struct udevice *dev)
625 struct zynq_gem_priv *priv = dev_get_priv(dev);
628 /* Align rxbuffers to ARCH_DMA_MINALIGN */
629 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
630 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
632 /* Align bd_space to MMU_SECTION_SHIFT */
633 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
634 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
635 BD_SPACE, DCACHE_OFF);
637 /* Initialize the bd spaces for tx and rx bd's */
638 priv->tx_bd = (struct emac_bd *)bd_space;
639 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
641 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
643 dev_err(dev, "failed to get clock\n");
647 priv->bus = mdio_alloc();
648 priv->bus->read = zynq_gem_miiphy_read;
649 priv->bus->write = zynq_gem_miiphy_write;
650 priv->bus->priv = priv;
652 ret = mdio_register_seq(priv->bus, dev->seq);
656 return zynq_phy_init(dev);
659 static int zynq_gem_remove(struct udevice *dev)
661 struct zynq_gem_priv *priv = dev_get_priv(dev);
664 mdio_unregister(priv->bus);
665 mdio_free(priv->bus);
670 static const struct eth_ops zynq_gem_ops = {
671 .start = zynq_gem_init,
672 .send = zynq_gem_send,
673 .recv = zynq_gem_recv,
674 .free_pkt = zynq_gem_free_pkt,
675 .stop = zynq_gem_halt,
676 .write_hwaddr = zynq_gem_setup_mac,
677 .read_rom_hwaddr = zynq_gem_read_rom_mac,
680 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
682 struct eth_pdata *pdata = dev_get_platdata(dev);
683 struct zynq_gem_priv *priv = dev_get_priv(dev);
684 int node = dev_of_offset(dev);
685 const char *phy_mode;
687 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
688 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
689 /* Hardcode for now */
692 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
694 if (priv->phy_of_handle > 0)
695 priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
696 priv->phy_of_handle, "reg", -1);
698 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
700 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
701 if (pdata->phy_interface == -1) {
702 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
705 priv->interface = pdata->phy_interface;
707 priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
708 "is-internal-pcspma");
710 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
711 priv->phyaddr, phy_string_for_interface(priv->interface));
716 static const struct udevice_id zynq_gem_ids[] = {
717 { .compatible = "cdns,zynqmp-gem" },
718 { .compatible = "cdns,zynq-gem" },
719 { .compatible = "cdns,gem" },
723 U_BOOT_DRIVER(zynq_gem) = {
726 .of_match = zynq_gem_ids,
727 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
728 .probe = zynq_gem_probe,
729 .remove = zynq_gem_remove,
730 .ops = &zynq_gem_ops,
731 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
732 .platdata_auto_alloc_size = sizeof(struct eth_pdata),