2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
5 * Michal SIMEK <monstr@monstr.eu>
7 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm-generic/errno.h>
21 #include <linux/kernel.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define ENET_ADDR_LENGTH 6
27 #define ETH_FCS_LEN 4 /* Octets in the FCS */
30 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
31 /* Xmit interrupt enable bit */
32 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
33 /* Program the MAC address */
34 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
35 /* define for programming the MAC address into the EMAC Lite */
36 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
38 /* Transmit packet length upper byte */
39 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
40 /* Transmit packet length lower byte */
41 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
44 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
45 /* Recv interrupt enable bit */
46 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
48 /* MDIO Address Register Bit Masks */
49 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
50 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
51 #define XEL_MDIOADDR_PHYADR_SHIFT 5
52 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
54 /* MDIO Write Data Register Bit Masks */
55 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
57 /* MDIO Read Data Register Bit Masks */
58 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
60 /* MDIO Control Register Bit Masks */
61 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
62 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
64 struct emaclite_regs {
65 u32 tx_ping; /* 0x0 - TX Ping buffer */
67 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
68 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
69 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
70 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
71 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
72 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
73 u32 tx_ping_tsr; /* 0x7fc - Tx status */
74 u32 tx_pong; /* 0x800 - TX Pong buffer */
76 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
77 u32 reserved3; /* 0xff8 */
78 u32 tx_pong_tsr; /* 0xffc - Tx status */
79 u32 rx_ping; /* 0x1000 - Receive Buffer */
81 u32 rx_ping_rsr; /* 0x17fc - Rx status */
82 u32 rx_pong; /* 0x1800 - Receive Buffer */
84 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
88 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
89 u32 txpp; /* TX ping pong buffer */
90 u32 rxpp; /* RX ping pong buffer */
92 struct emaclite_regs *regs;
93 struct phy_device *phydev;
97 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
99 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
108 from32ptr = (u32 *) srcptr;
110 /* Word aligned buffer, no correction needed. */
111 to32ptr = (u32 *) destptr;
112 while (bytecount > 3) {
113 *to32ptr++ = *from32ptr++;
116 to8ptr = (u8 *) to32ptr;
118 alignbuffer = *from32ptr++;
119 from8ptr = (u8 *) &alignbuffer;
121 for (i = 0; i < bytecount; i++)
122 *to8ptr++ = *from8ptr++;
125 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
129 u32 *to32ptr = (u32 *) destptr;
134 from32ptr = (u32 *) srcptr;
135 while (bytecount > 3) {
137 *to32ptr++ = *from32ptr++;
142 to8ptr = (u8 *) &alignbuffer;
143 from8ptr = (u8 *) from32ptr;
145 for (i = 0; i < bytecount; i++)
146 *to8ptr++ = *from8ptr++;
148 *to32ptr++ = alignbuffer;
151 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
152 bool set, unsigned int timeout)
155 unsigned long start = get_timer(0);
163 if ((val & mask) == mask)
166 if (get_timer(start) > timeout)
177 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
178 func, reg, mask, set);
183 static int mdio_wait(struct emaclite_regs *regs)
185 return wait_for_bit(__func__, ®s->mdioctrl,
186 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
189 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
192 struct emaclite_regs *regs = emaclite->regs;
197 u32 ctrl_reg = in_be32(®s->mdioctrl);
198 out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
199 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
200 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
206 *data = in_be32(®s->mdiord);
210 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
213 struct emaclite_regs *regs = emaclite->regs;
219 * Write the PHY address, register number and clear the OP bit in the
220 * MDIO Address register and then write the value into the MDIO Write
221 * Data register. Finally, set the Status bit in the MDIO Control
222 * register to start a MDIO write transaction.
224 u32 ctrl_reg = in_be32(®s->mdioctrl);
225 out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
226 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
227 out_be32(®s->mdiowr, data);
228 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
236 static void emaclite_stop(struct udevice *dev)
241 /* Use MII register 1 (MII status register) to detect PHY */
242 #define PHY_DETECT_REG 1
244 /* Mask used to verify certain PHY features (or register contents)
245 * in the register above:
246 * 0x1000: 10Mbps full duplex support
247 * 0x0800: 10Mbps half duplex support
248 * 0x0008: Auto-negotiation support
250 #define PHY_DETECT_MASK 0x1808
252 static int setup_phy(struct udevice *dev)
256 struct xemaclite *emaclite = dev_get_priv(dev);
257 struct phy_device *phydev;
259 u32 supported = SUPPORTED_10baseT_Half |
260 SUPPORTED_10baseT_Full |
261 SUPPORTED_100baseT_Half |
262 SUPPORTED_100baseT_Full;
264 if (emaclite->phyaddr != -1) {
265 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
266 if ((phyreg != 0xFFFF) &&
267 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
268 /* Found a valid PHY address */
269 debug("Default phy address %d is valid\n",
272 debug("PHY address is not setup correctly %d\n",
274 emaclite->phyaddr = -1;
278 if (emaclite->phyaddr == -1) {
279 /* detect the PHY address */
280 for (i = 31; i >= 0; i--) {
281 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
282 if ((phyreg != 0xFFFF) &&
283 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
284 /* Found a valid PHY address */
285 emaclite->phyaddr = i;
286 debug("emaclite: Found valid phy address, %d\n",
293 /* interface - look at tsec */
294 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
295 PHY_INTERFACE_MODE_MII);
297 * Phy can support 1000baseT but device NOT that's why phydev->supported
298 * must be setup for 1000baseT. phydev->advertising setups what speeds
299 * will be used for autonegotiation where 1000baseT must be disabled.
301 phydev->supported = supported | SUPPORTED_1000baseT_Half |
302 SUPPORTED_1000baseT_Full;
303 phydev->advertising = supported;
304 emaclite->phydev = phydev;
306 ret = phy_startup(phydev);
311 printf("%s: No link.\n", phydev->dev->name);
315 /* Do not setup anything */
319 static int emaclite_start(struct udevice *dev)
321 struct xemaclite *emaclite = dev_get_priv(dev);
322 struct eth_pdata *pdata = dev_get_platdata(dev);
323 struct emaclite_regs *regs = emaclite->regs;
325 debug("EmacLite Initialization Started\n");
328 * TX - TX_PING & TX_PONG initialization
330 /* Restart PING TX */
331 out_be32(®s->tx_ping_tsr, 0);
332 /* Copy MAC address */
333 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
336 out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH);
337 /* Update the MAC address in the EMAC Lite */
338 out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
339 /* Wait for EMAC Lite to finish with the MAC address update */
340 while ((in_be32 (®s->tx_ping_tsr) &
341 XEL_TSR_PROG_MAC_ADDR) != 0)
344 if (emaclite->txpp) {
345 /* The same operation with PONG TX */
346 out_be32(®s->tx_pong_tsr, 0);
347 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
349 out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH);
350 out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
351 while ((in_be32(®s->tx_pong_tsr) &
352 XEL_TSR_PROG_MAC_ADDR) != 0)
357 * RX - RX_PING & RX_PONG initialization
359 /* Write out the value to flush the RX buffer */
360 out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
363 out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
365 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
366 if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
370 debug("EmacLite Initialization complete\n");
374 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
377 struct emaclite_regs *regs = emaclite->regs;
380 * Read the other buffer register
381 * and determine if the other buffer is available
383 tmp = ~in_be32(®s->tx_ping_tsr);
385 tmp |= ~in_be32(®s->tx_pong_tsr);
387 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
390 static int emaclite_send(struct udevice *dev, void *ptr, int len)
393 struct xemaclite *emaclite = dev_get_priv(dev);
394 struct emaclite_regs *regs = emaclite->regs;
401 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
407 printf("Error: Timeout waiting for ethernet TX buffer\n");
408 /* Restart PING TX */
409 out_be32(®s->tx_ping_tsr, 0);
410 if (emaclite->txpp) {
411 out_be32(®s->tx_pong_tsr, 0);
416 /* Determine if the expected buffer address is empty */
417 reg = in_be32(®s->tx_ping_tsr);
418 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
419 debug("Send packet from tx_ping buffer\n");
420 /* Write the frame to the buffer */
421 xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
422 out_be32(®s->tx_ping_tplr, len &
423 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
424 reg = in_be32(®s->tx_ping_tsr);
425 reg |= XEL_TSR_XMIT_BUSY_MASK;
426 out_be32(®s->tx_ping_tsr, reg);
430 if (emaclite->txpp) {
431 /* Determine if the expected buffer address is empty */
432 reg = in_be32(®s->tx_pong_tsr);
433 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
434 debug("Send packet from tx_pong buffer\n");
435 /* Write the frame to the buffer */
436 xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
437 out_be32(®s->tx_pong_tplr, len &
438 (XEL_TPLR_LENGTH_MASK_HI |
439 XEL_TPLR_LENGTH_MASK_LO));
440 reg = in_be32(®s->tx_pong_tsr);
441 reg |= XEL_TSR_XMIT_BUSY_MASK;
442 out_be32(®s->tx_pong_tsr, reg);
447 puts("Error while sending frame\n");
451 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
453 u32 length, first_read, reg, attempt = 0;
455 struct xemaclite *emaclite = dev->priv;
456 struct emaclite_regs *regs = emaclite->regs;
457 struct ethernet_hdr *eth;
458 struct ip_udp_hdr *ip;
461 if (!emaclite->use_rx_pong_buffer_next) {
462 reg = in_be32(®s->rx_ping_rsr);
463 debug("Testing data at rx_ping\n");
464 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
465 debug("Data found in rx_ping buffer\n");
466 addr = ®s->rx_ping;
467 ack = ®s->rx_ping_rsr;
469 debug("Data not found in rx_ping buffer\n");
470 /* Pong buffer is not available - return immediately */
474 /* Try pong buffer if this is first attempt */
477 emaclite->use_rx_pong_buffer_next =
478 !emaclite->use_rx_pong_buffer_next;
482 reg = in_be32(®s->rx_pong_rsr);
483 debug("Testing data at rx_pong\n");
484 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
485 debug("Data found in rx_pong buffer\n");
486 addr = ®s->rx_pong;
487 ack = ®s->rx_pong_rsr;
489 debug("Data not found in rx_pong buffer\n");
490 /* Try ping buffer if this is first attempt */
493 emaclite->use_rx_pong_buffer_next =
494 !emaclite->use_rx_pong_buffer_next;
499 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
500 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
501 xemaclite_alignedread(addr, etherrxbuff, first_read);
503 /* Detect real packet size */
504 eth = (struct ethernet_hdr *)etherrxbuff;
505 switch (ntohs(eth->et_protlen)) {
508 debug("ARP Packet %x\n", length);
511 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
512 length = ntohs(ip->ip_len);
513 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
514 debug("IP Packet %x\n", length);
517 debug("Other Packet\n");
522 /* Read the rest of the packet which is longer then first read */
523 if (length != first_read)
524 xemaclite_alignedread(addr + first_read,
525 etherrxbuff + first_read,
526 length - first_read);
528 /* Acknowledge the frame */
530 reg &= ~XEL_RSR_RECV_DONE_MASK;
533 debug("Packet receive from 0x%p, length %dB\n", addr, length);
534 *packetp = etherrxbuff;
538 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
544 ret = phyread(bus->priv, addr, reg, &val);
545 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
549 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
552 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
553 return phywrite(bus->priv, addr, reg, value);
556 static int emaclite_probe(struct udevice *dev)
558 struct xemaclite *emaclite = dev_get_priv(dev);
561 emaclite->bus = mdio_alloc();
562 emaclite->bus->read = emaclite_miiphy_read;
563 emaclite->bus->write = emaclite_miiphy_write;
564 emaclite->bus->priv = emaclite;
565 strcpy(emaclite->bus->name, "emaclite");
567 ret = mdio_register(emaclite->bus);
574 static int emaclite_remove(struct udevice *dev)
576 struct xemaclite *emaclite = dev_get_priv(dev);
578 free(emaclite->phydev);
579 mdio_unregister(emaclite->bus);
580 mdio_free(emaclite->bus);
585 static const struct eth_ops emaclite_ops = {
586 .start = emaclite_start,
587 .send = emaclite_send,
588 .recv = emaclite_recv,
589 .stop = emaclite_stop,
592 static int emaclite_ofdata_to_platdata(struct udevice *dev)
594 struct eth_pdata *pdata = dev_get_platdata(dev);
595 struct xemaclite *emaclite = dev_get_priv(dev);
598 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
599 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
602 emaclite->phyaddr = -1;
604 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
607 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
610 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
611 "xlnx,tx-ping-pong", 0);
612 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
613 "xlnx,rx-ping-pong", 0);
615 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
616 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
621 static const struct udevice_id emaclite_ids[] = {
622 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
626 U_BOOT_DRIVER(emaclite) = {
629 .of_match = emaclite_ids,
630 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
631 .probe = emaclite_probe,
632 .remove = emaclite_remove,
633 .ops = &emaclite_ops,
634 .priv_auto_alloc_size = sizeof(struct xemaclite),
635 .platdata_auto_alloc_size = sizeof(struct eth_pdata),