2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
5 * Michal SIMEK <monstr@monstr.eu>
7 * SPDX-License-Identifier: GPL-2.0+
20 #include <asm-generic/errno.h>
21 #include <linux/kernel.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define ENET_ADDR_LENGTH 6
26 #define ETH_FCS_LEN 4 /* Octets in the FCS */
29 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
30 /* Xmit interrupt enable bit */
31 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
32 /* Program the MAC address */
33 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
34 /* define for programming the MAC address into the EMAC Lite */
35 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
37 /* Transmit packet length upper byte */
38 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
39 /* Transmit packet length lower byte */
40 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
43 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
44 /* Recv interrupt enable bit */
45 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
47 /* MDIO Address Register Bit Masks */
48 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
49 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
50 #define XEL_MDIOADDR_PHYADR_SHIFT 5
51 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
53 /* MDIO Write Data Register Bit Masks */
54 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
56 /* MDIO Read Data Register Bit Masks */
57 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
59 /* MDIO Control Register Bit Masks */
60 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
61 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
63 struct emaclite_regs {
64 u32 tx_ping; /* 0x0 - TX Ping buffer */
66 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
67 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
68 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
69 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
70 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
71 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
72 u32 tx_ping_tsr; /* 0x7fc - Tx status */
73 u32 tx_pong; /* 0x800 - TX Pong buffer */
75 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
76 u32 reserved3; /* 0xff8 */
77 u32 tx_pong_tsr; /* 0xffc - Tx status */
78 u32 rx_ping; /* 0x1000 - Receive Buffer */
80 u32 rx_ping_rsr; /* 0x17fc - Rx status */
81 u32 rx_pong; /* 0x1800 - Receive Buffer */
83 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
87 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
88 u32 txpp; /* TX ping pong buffer */
89 u32 rxpp; /* RX ping pong buffer */
91 struct emaclite_regs *regs;
92 struct phy_device *phydev;
96 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
98 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
107 from32ptr = (u32 *) srcptr;
109 /* Word aligned buffer, no correction needed. */
110 to32ptr = (u32 *) destptr;
111 while (bytecount > 3) {
112 *to32ptr++ = *from32ptr++;
115 to8ptr = (u8 *) to32ptr;
117 alignbuffer = *from32ptr++;
118 from8ptr = (u8 *) &alignbuffer;
120 for (i = 0; i < bytecount; i++)
121 *to8ptr++ = *from8ptr++;
124 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
128 u32 *to32ptr = (u32 *) destptr;
133 from32ptr = (u32 *) srcptr;
134 while (bytecount > 3) {
136 *to32ptr++ = *from32ptr++;
141 to8ptr = (u8 *) &alignbuffer;
142 from8ptr = (u8 *) from32ptr;
144 for (i = 0; i < bytecount; i++)
145 *to8ptr++ = *from8ptr++;
147 *to32ptr++ = alignbuffer;
150 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
151 bool set, unsigned int timeout)
154 unsigned long start = get_timer(0);
162 if ((val & mask) == mask)
165 if (get_timer(start) > timeout)
176 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
177 func, reg, mask, set);
182 static int mdio_wait(struct emaclite_regs *regs)
184 return wait_for_bit(__func__, ®s->mdioctrl,
185 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
188 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
191 struct emaclite_regs *regs = emaclite->regs;
196 u32 ctrl_reg = in_be32(®s->mdioctrl);
197 out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK |
198 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
199 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
205 *data = in_be32(®s->mdiord);
209 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
212 struct emaclite_regs *regs = emaclite->regs;
218 * Write the PHY address, register number and clear the OP bit in the
219 * MDIO Address register and then write the value into the MDIO Write
220 * Data register. Finally, set the Status bit in the MDIO Control
221 * register to start a MDIO write transaction.
223 u32 ctrl_reg = in_be32(®s->mdioctrl);
224 out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
225 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
226 out_be32(®s->mdiowr, data);
227 out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);
235 static void emaclite_stop(struct udevice *dev)
240 /* Use MII register 1 (MII status register) to detect PHY */
241 #define PHY_DETECT_REG 1
243 /* Mask used to verify certain PHY features (or register contents)
244 * in the register above:
245 * 0x1000: 10Mbps full duplex support
246 * 0x0800: 10Mbps half duplex support
247 * 0x0008: Auto-negotiation support
249 #define PHY_DETECT_MASK 0x1808
251 static int setup_phy(struct udevice *dev)
255 struct xemaclite *emaclite = dev_get_priv(dev);
256 struct phy_device *phydev;
258 u32 supported = SUPPORTED_10baseT_Half |
259 SUPPORTED_10baseT_Full |
260 SUPPORTED_100baseT_Half |
261 SUPPORTED_100baseT_Full;
263 if (emaclite->phyaddr != -1) {
264 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
265 if ((phyreg != 0xFFFF) &&
266 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
267 /* Found a valid PHY address */
268 debug("Default phy address %d is valid\n",
271 debug("PHY address is not setup correctly %d\n",
273 emaclite->phyaddr = -1;
277 if (emaclite->phyaddr == -1) {
278 /* detect the PHY address */
279 for (i = 31; i >= 0; i--) {
280 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
281 if ((phyreg != 0xFFFF) &&
282 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
283 /* Found a valid PHY address */
284 emaclite->phyaddr = i;
285 debug("emaclite: Found valid phy address, %d\n",
292 /* interface - look at tsec */
293 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
294 PHY_INTERFACE_MODE_MII);
296 * Phy can support 1000baseT but device NOT that's why phydev->supported
297 * must be setup for 1000baseT. phydev->advertising setups what speeds
298 * will be used for autonegotiation where 1000baseT must be disabled.
300 phydev->supported = supported | SUPPORTED_1000baseT_Half |
301 SUPPORTED_1000baseT_Full;
302 phydev->advertising = supported;
303 emaclite->phydev = phydev;
305 ret = phy_startup(phydev);
310 printf("%s: No link.\n", phydev->dev->name);
314 /* Do not setup anything */
318 static int emaclite_start(struct udevice *dev)
320 struct xemaclite *emaclite = dev_get_priv(dev);
321 struct eth_pdata *pdata = dev_get_platdata(dev);
322 struct emaclite_regs *regs = emaclite->regs;
324 debug("EmacLite Initialization Started\n");
327 * TX - TX_PING & TX_PONG initialization
329 /* Restart PING TX */
330 out_be32(®s->tx_ping_tsr, 0);
331 /* Copy MAC address */
332 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
335 out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH);
336 /* Update the MAC address in the EMAC Lite */
337 out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
338 /* Wait for EMAC Lite to finish with the MAC address update */
339 while ((in_be32 (®s->tx_ping_tsr) &
340 XEL_TSR_PROG_MAC_ADDR) != 0)
343 if (emaclite->txpp) {
344 /* The same operation with PONG TX */
345 out_be32(®s->tx_pong_tsr, 0);
346 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
348 out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH);
349 out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
350 while ((in_be32(®s->tx_pong_tsr) &
351 XEL_TSR_PROG_MAC_ADDR) != 0)
356 * RX - RX_PING & RX_PONG initialization
358 /* Write out the value to flush the RX buffer */
359 out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
362 out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
364 out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
365 if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
369 debug("EmacLite Initialization complete\n");
373 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
376 struct emaclite_regs *regs = emaclite->regs;
379 * Read the other buffer register
380 * and determine if the other buffer is available
382 tmp = ~in_be32(®s->tx_ping_tsr);
384 tmp |= ~in_be32(®s->tx_pong_tsr);
386 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
389 static int emaclite_send(struct udevice *dev, void *ptr, int len)
392 struct xemaclite *emaclite = dev_get_priv(dev);
393 struct emaclite_regs *regs = emaclite->regs;
400 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
406 printf("Error: Timeout waiting for ethernet TX buffer\n");
407 /* Restart PING TX */
408 out_be32(®s->tx_ping_tsr, 0);
409 if (emaclite->txpp) {
410 out_be32(®s->tx_pong_tsr, 0);
415 /* Determine if the expected buffer address is empty */
416 reg = in_be32(®s->tx_ping_tsr);
417 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
418 debug("Send packet from tx_ping buffer\n");
419 /* Write the frame to the buffer */
420 xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
421 out_be32(®s->tx_ping_tplr, len &
422 (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO));
423 reg = in_be32(®s->tx_ping_tsr);
424 reg |= XEL_TSR_XMIT_BUSY_MASK;
425 out_be32(®s->tx_ping_tsr, reg);
429 if (emaclite->txpp) {
430 /* Determine if the expected buffer address is empty */
431 reg = in_be32(®s->tx_pong_tsr);
432 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
433 debug("Send packet from tx_pong buffer\n");
434 /* Write the frame to the buffer */
435 xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
436 out_be32(®s->tx_pong_tplr, len &
437 (XEL_TPLR_LENGTH_MASK_HI |
438 XEL_TPLR_LENGTH_MASK_LO));
439 reg = in_be32(®s->tx_pong_tsr);
440 reg |= XEL_TSR_XMIT_BUSY_MASK;
441 out_be32(®s->tx_pong_tsr, reg);
446 puts("Error while sending frame\n");
450 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
452 u32 length, first_read, reg, attempt = 0;
454 struct xemaclite *emaclite = dev->priv;
455 struct emaclite_regs *regs = emaclite->regs;
456 struct ethernet_hdr *eth;
457 struct ip_udp_hdr *ip;
460 if (!emaclite->use_rx_pong_buffer_next) {
461 reg = in_be32(®s->rx_ping_rsr);
462 debug("Testing data at rx_ping\n");
463 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
464 debug("Data found in rx_ping buffer\n");
465 addr = ®s->rx_ping;
466 ack = ®s->rx_ping_rsr;
468 debug("Data not found in rx_ping buffer\n");
469 /* Pong buffer is not available - return immediately */
473 /* Try pong buffer if this is first attempt */
476 emaclite->use_rx_pong_buffer_next =
477 !emaclite->use_rx_pong_buffer_next;
481 reg = in_be32(®s->rx_pong_rsr);
482 debug("Testing data at rx_pong\n");
483 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
484 debug("Data found in rx_pong buffer\n");
485 addr = ®s->rx_pong;
486 ack = ®s->rx_pong_rsr;
488 debug("Data not found in rx_pong buffer\n");
489 /* Try ping buffer if this is first attempt */
492 emaclite->use_rx_pong_buffer_next =
493 !emaclite->use_rx_pong_buffer_next;
498 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
499 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
500 xemaclite_alignedread(addr, etherrxbuff, first_read);
502 /* Detect real packet size */
503 eth = (struct ethernet_hdr *)etherrxbuff;
504 switch (ntohs(eth->et_protlen)) {
507 debug("ARP Packet %x\n", length);
510 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
511 length = ntohs(ip->ip_len);
512 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
513 debug("IP Packet %x\n", length);
516 debug("Other Packet\n");
521 /* Read the rest of the packet which is longer then first read */
522 if (length != first_read)
523 xemaclite_alignedread(addr + first_read,
524 etherrxbuff + first_read,
525 length - first_read);
527 /* Acknowledge the frame */
529 reg &= ~XEL_RSR_RECV_DONE_MASK;
532 debug("Packet receive from 0x%p, length %dB\n", addr, length);
533 *packetp = etherrxbuff;
537 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
543 ret = phyread(bus->priv, addr, reg, &val);
544 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
548 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
551 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
552 return phywrite(bus->priv, addr, reg, value);
555 static int emaclite_probe(struct udevice *dev)
557 struct xemaclite *emaclite = dev_get_priv(dev);
560 emaclite->bus = mdio_alloc();
561 emaclite->bus->read = emaclite_miiphy_read;
562 emaclite->bus->write = emaclite_miiphy_write;
563 emaclite->bus->priv = emaclite;
564 strcpy(emaclite->bus->name, "emaclite");
566 ret = mdio_register(emaclite->bus);
573 static int emaclite_remove(struct udevice *dev)
575 struct xemaclite *emaclite = dev_get_priv(dev);
577 free(emaclite->phydev);
578 mdio_unregister(emaclite->bus);
579 mdio_free(emaclite->bus);
584 static const struct eth_ops emaclite_ops = {
585 .start = emaclite_start,
586 .send = emaclite_send,
587 .recv = emaclite_recv,
588 .stop = emaclite_stop,
591 static int emaclite_ofdata_to_platdata(struct udevice *dev)
593 struct eth_pdata *pdata = dev_get_platdata(dev);
594 struct xemaclite *emaclite = dev_get_priv(dev);
597 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
598 emaclite->regs = (struct emaclite_regs *)pdata->iobase;
600 emaclite->phyaddr = -1;
602 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
605 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
608 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
609 "xlnx,tx-ping-pong", 0);
610 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
611 "xlnx,rx-ping-pong", 0);
613 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
614 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
619 static const struct udevice_id emaclite_ids[] = {
620 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
624 U_BOOT_DRIVER(emaclite) = {
627 .of_match = emaclite_ids,
628 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
629 .probe = emaclite_probe,
630 .remove = emaclite_remove,
631 .ops = &emaclite_ops,
632 .priv_auto_alloc_size = sizeof(struct xemaclite),
633 .platdata_auto_alloc_size = sizeof(struct eth_pdata),