1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011 PetaLogix
5 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
19 #include <linux/delay.h>
21 DECLARE_GLOBAL_DATA_PTR;
24 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
25 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
26 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
27 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
29 /* Interrupt Status/Enable/Mask Registers bit definitions */
30 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
31 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
33 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
34 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
36 /* Transmitter Configuration (TC) Register bit definitions */
37 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
39 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
41 /* MDIO Management Configuration (MC) Register bit definitions */
42 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
44 /* MDIO Management Control Register (MCR) Register bit definitions */
45 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
46 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
47 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
48 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
49 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
50 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
51 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
52 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
54 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
56 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
59 /* Bitmasks of XAXIDMA_CR_OFFSET register */
60 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
61 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
63 /* Bitmasks of XAXIDMA_SR_OFFSET register */
64 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
66 /* Bitmask for interrupts */
67 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
68 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
69 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
71 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
72 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
73 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
77 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
79 /* Reflect dma offsets */
81 u32 control; /* DMACR */
82 u32 status; /* DMASR */
83 u32 current; /* CURDESC low 32 bit */
84 u32 current_hi; /* CURDESC high 32 bit */
85 u32 tail; /* TAILDESC low 32 bit */
86 u32 tail_hi; /* TAILDESC high 32 bit */
89 /* Private driver structures */
91 struct axidma_reg *dmatx;
92 struct axidma_reg *dmarx;
94 struct axi_regs *iobase;
95 phy_interface_t interface;
96 struct phy_device *phydev;
104 u32 next; /* Next descriptor pointer */
106 u32 phys; /* Buffer address */
110 u32 cntrl; /* Control */
111 u32 status; /* Status */
113 u32 app1; /* TX start << 16 | insert */
114 u32 app2; /* TX csum seed */
122 /* Static BDs - driver uses only one BD */
123 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
124 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
128 u32 is; /* 0xC: Interrupt status */
130 u32 ie; /* 0x14: Interrupt enable */
132 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
133 u32 tc; /* 0x408: Tx Configuration */
135 u32 emmc; /* 0x410: EMAC mode configuration */
137 u32 mdio_mc; /* 0x500: MII Management Config */
138 u32 mdio_mcr; /* 0x504: MII Management Control */
139 u32 mdio_mwd; /* 0x508: MII Management Write Data */
140 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
142 u32 uaw0; /* 0x700: Unicast address word 0 */
143 u32 uaw1; /* 0x704: Unicast address word 1 */
146 /* Use MII register 1 (MII status register) to detect PHY */
147 #define PHY_DETECT_REG 1
150 * Mask used to verify certain PHY features (or register contents)
151 * in the register above:
152 * 0x1000: 10Mbps full duplex support
153 * 0x0800: 10Mbps half duplex support
154 * 0x0008: Auto-negotiation support
156 #define PHY_DETECT_MASK 0x1808
158 static inline int mdio_wait(struct axi_regs *regs)
162 /* Wait till MDIO interface is ready to accept a new transaction. */
163 while (timeout && (!(readl(®s->mdio_mcr)
164 & XAE_MDIO_MCR_READY_MASK))) {
169 printf("%s: Timeout\n", __func__);
176 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
177 * @bd: pointer to BD descriptor structure
178 * @desc: Address offset of DMA descriptors
180 * This function writes the value into the corresponding Axi DMA register.
182 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
184 #if defined(CONFIG_PHYS_64BIT)
187 writel((u32)bd, desc);
191 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
194 struct axi_regs *regs = priv->iobase;
200 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
201 XAE_MDIO_MCR_PHYAD_MASK) |
202 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
203 & XAE_MDIO_MCR_REGAD_MASK) |
204 XAE_MDIO_MCR_INITIATE_MASK |
205 XAE_MDIO_MCR_OP_READ_MASK;
207 writel(mdioctrlreg, ®s->mdio_mcr);
213 *val = readl(®s->mdio_mrd);
217 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
220 struct axi_regs *regs = priv->iobase;
226 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
227 XAE_MDIO_MCR_PHYAD_MASK) |
228 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
229 & XAE_MDIO_MCR_REGAD_MASK) |
230 XAE_MDIO_MCR_INITIATE_MASK |
231 XAE_MDIO_MCR_OP_WRITE_MASK;
234 writel(data, ®s->mdio_mwd);
236 writel(mdioctrlreg, ®s->mdio_mcr);
244 static int axiemac_phy_init(struct udevice *dev)
248 struct axidma_priv *priv = dev_get_priv(dev);
249 struct axi_regs *regs = priv->iobase;
250 struct phy_device *phydev;
252 u32 supported = SUPPORTED_10baseT_Half |
253 SUPPORTED_10baseT_Full |
254 SUPPORTED_100baseT_Half |
255 SUPPORTED_100baseT_Full |
256 SUPPORTED_1000baseT_Half |
257 SUPPORTED_1000baseT_Full;
259 /* Set default MDIO divisor */
260 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
262 if (priv->phyaddr == -1) {
263 /* Detect the PHY address */
264 for (i = 31; i >= 0; i--) {
265 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
266 if (!ret && (phyreg != 0xFFFF) &&
267 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
268 /* Found a valid PHY address */
270 debug("axiemac: Found valid phy address, %x\n",
277 /* Interface - look at tsec */
278 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
280 phydev->supported &= supported;
281 phydev->advertising = phydev->supported;
282 priv->phydev = phydev;
283 if (priv->phy_of_handle)
284 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
290 /* Setting axi emac and phy to proper setting */
291 static int setup_phy(struct udevice *dev)
294 u32 speed, emmc_reg, ret;
295 struct axidma_priv *priv = dev_get_priv(dev);
296 struct axi_regs *regs = priv->iobase;
297 struct phy_device *phydev = priv->phydev;
299 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
301 * In SGMII cases the isolate bit might set
302 * after DMA and ethernet resets and hence
303 * check and clear if set.
305 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
308 if (temp & BMCR_ISOLATE) {
309 temp &= ~BMCR_ISOLATE;
310 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
316 if (phy_startup(phydev)) {
317 printf("axiemac: could not initialize PHY %s\n",
322 printf("%s: No link.\n", phydev->dev->name);
326 switch (phydev->speed) {
328 speed = XAE_EMMC_LINKSPD_1000;
331 speed = XAE_EMMC_LINKSPD_100;
334 speed = XAE_EMMC_LINKSPD_10;
340 /* Setup the emac for the phy speed */
341 emmc_reg = readl(®s->emmc);
342 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
345 /* Write new speed setting out to Axi Ethernet */
346 writel(emmc_reg, ®s->emmc);
349 * Setting the operating speed of the MAC needs a delay. There
350 * doesn't seem to be register to poll, so please consider this
351 * during your application design.
358 /* STOP DMA transfers */
359 static void axiemac_stop(struct udevice *dev)
361 struct axidma_priv *priv = dev_get_priv(dev);
364 /* Stop the hardware */
365 temp = readl(&priv->dmatx->control);
366 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
367 writel(temp, &priv->dmatx->control);
369 temp = readl(&priv->dmarx->control);
370 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
371 writel(temp, &priv->dmarx->control);
373 debug("axiemac: Halted\n");
376 static int axi_ethernet_init(struct axidma_priv *priv)
378 struct axi_regs *regs = priv->iobase;
382 * Check the status of the MgtRdy bit in the interrupt status
383 * registers. This must be done to allow the MGT clock to become stable
384 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
385 * will be valid until this bit is valid.
386 * The bit is always a 1 for all other PHY interfaces.
387 * Interrupt status and enable registers are not available in non
388 * processor mode and hence bypass in this mode
390 if (!priv->eth_hasnobuf) {
391 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
394 printf("%s: Timeout\n", __func__);
399 * Stop the device and reset HW
402 writel(0, ®s->ie);
405 /* Disable the receiver */
406 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
409 * Stopping the receiver in mid-packet causes a dropped packet
410 * indication from HW. Clear it.
412 if (!priv->eth_hasnobuf) {
413 /* Set the interrupt status register to clear the interrupt */
414 writel(XAE_INT_RXRJECT_MASK, ®s->is);
418 /* Set default MDIO divisor */
419 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
421 debug("axiemac: InitHw done\n");
425 static int axiemac_write_hwaddr(struct udevice *dev)
427 struct eth_pdata *pdata = dev_get_platdata(dev);
428 struct axidma_priv *priv = dev_get_priv(dev);
429 struct axi_regs *regs = priv->iobase;
431 /* Set the MAC address */
432 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
433 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
434 writel(val, ®s->uaw0);
436 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
437 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
438 writel(val, ®s->uaw1);
442 /* Reset DMA engine */
443 static void axi_dma_init(struct axidma_priv *priv)
447 /* Reset the engine so the hardware starts from a known state */
448 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
449 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
451 /* At the initialization time, hardware should finish reset quickly */
453 /* Check transmit/receive channel */
454 /* Reset is done when the reset bit is low */
455 if (!((readl(&priv->dmatx->control) |
456 readl(&priv->dmarx->control))
457 & XAXIDMA_CR_RESET_MASK)) {
462 printf("%s: Timeout\n", __func__);
465 static int axiemac_start(struct udevice *dev)
467 struct axidma_priv *priv = dev_get_priv(dev);
468 struct axi_regs *regs = priv->iobase;
471 debug("axiemac: Init started\n");
473 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
474 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
475 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
476 * would ensure a reset of AxiEthernet.
480 /* Initialize AxiEthernet hardware. */
481 if (axi_ethernet_init(priv))
484 /* Disable all RX interrupts before RxBD space setup */
485 temp = readl(&priv->dmarx->control);
486 temp &= ~XAXIDMA_IRQ_ALL_MASK;
487 writel(temp, &priv->dmarx->control);
489 /* Start DMA RX channel. Now it's ready to receive data.*/
490 axienet_dma_write(&rx_bd, &priv->dmarx->current);
493 memset(&rx_bd, 0, sizeof(rx_bd));
494 rx_bd.next = (u32)&rx_bd;
495 rx_bd.phys = (u32)&rxframe;
496 rx_bd.cntrl = sizeof(rxframe);
497 /* Flush the last BD so DMA core could see the updates */
498 flush_cache((u32)&rx_bd, sizeof(rx_bd));
500 /* It is necessary to flush rxframe because if you don't do it
501 * then cache can contain uninitialized data */
502 flush_cache((u32)&rxframe, sizeof(rxframe));
504 /* Start the hardware */
505 temp = readl(&priv->dmarx->control);
506 temp |= XAXIDMA_CR_RUNSTOP_MASK;
507 writel(temp, &priv->dmarx->control);
509 /* Rx BD is ready - start */
510 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
513 writel(XAE_TC_TX_MASK, ®s->tc);
515 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
518 if (!setup_phy(dev)) {
523 debug("axiemac: Init complete\n");
527 static int axiemac_send(struct udevice *dev, void *ptr, int len)
529 struct axidma_priv *priv = dev_get_priv(dev);
532 if (len > PKTSIZE_ALIGN)
535 /* Flush packet to main memory to be trasfered by DMA */
536 flush_cache((u32)ptr, len);
539 memset(&tx_bd, 0, sizeof(tx_bd));
540 /* At the end of the ring, link the last BD back to the top */
541 tx_bd.next = (u32)&tx_bd;
542 tx_bd.phys = (u32)ptr;
544 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
545 XAXIDMA_BD_CTRL_TXEOF_MASK;
547 /* Flush the last BD so DMA core could see the updates */
548 flush_cache((u32)&tx_bd, sizeof(tx_bd));
550 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
552 axienet_dma_write(&tx_bd, &priv->dmatx->current);
553 /* Start the hardware */
554 temp = readl(&priv->dmatx->control);
555 temp |= XAXIDMA_CR_RUNSTOP_MASK;
556 writel(temp, &priv->dmatx->control);
560 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
562 /* Wait for transmission to complete */
563 debug("axiemac: Waiting for tx to be done\n");
565 while (timeout && (!(readl(&priv->dmatx->status) &
566 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
571 printf("%s: Timeout\n", __func__);
575 debug("axiemac: Sending complete\n");
579 static int isrxready(struct axidma_priv *priv)
583 /* Read pending interrupts */
584 status = readl(&priv->dmarx->status);
586 /* Acknowledge pending interrupts */
587 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
590 * If Reception done interrupt is asserted, call RX call back function
591 * to handle the processed BDs and then raise the according flag.
593 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
599 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
602 struct axidma_priv *priv = dev_get_priv(dev);
605 /* Wait for an incoming packet */
606 if (!isrxready(priv))
609 debug("axiemac: RX data ready\n");
611 /* Disable IRQ for a moment till packet is handled */
612 temp = readl(&priv->dmarx->control);
613 temp &= ~XAXIDMA_IRQ_ALL_MASK;
614 writel(temp, &priv->dmarx->control);
615 if (!priv->eth_hasnobuf)
616 length = rx_bd.app4 & 0xFFFF; /* max length mask */
618 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
621 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
628 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
630 struct axidma_priv *priv = dev_get_priv(dev);
633 /* It is useful to clear buffer to be sure that it is consistent */
634 memset(rxframe, 0, sizeof(rxframe));
637 /* Clear the whole buffer and setup it again - all flags are cleared */
638 memset(&rx_bd, 0, sizeof(rx_bd));
639 rx_bd.next = (u32)&rx_bd;
640 rx_bd.phys = (u32)&rxframe;
641 rx_bd.cntrl = sizeof(rxframe);
644 flush_cache((u32)&rx_bd, sizeof(rx_bd));
646 /* It is necessary to flush rxframe because if you don't do it
647 * then cache will contain previous packet */
648 flush_cache((u32)&rxframe, sizeof(rxframe));
650 /* Rx BD is ready - start again */
651 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
653 debug("axiemac: RX completed, framelength = %d\n", length);
658 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
664 ret = phyread(bus->priv, addr, reg, &value);
665 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
670 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
673 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
674 return phywrite(bus->priv, addr, reg, value);
677 static int axi_emac_probe(struct udevice *dev)
679 struct axidma_priv *priv = dev_get_priv(dev);
682 priv->bus = mdio_alloc();
683 priv->bus->read = axiemac_miiphy_read;
684 priv->bus->write = axiemac_miiphy_write;
685 priv->bus->priv = priv;
687 ret = mdio_register_seq(priv->bus, dev->seq);
691 axiemac_phy_init(dev);
696 static int axi_emac_remove(struct udevice *dev)
698 struct axidma_priv *priv = dev_get_priv(dev);
701 mdio_unregister(priv->bus);
702 mdio_free(priv->bus);
707 static const struct eth_ops axi_emac_ops = {
708 .start = axiemac_start,
709 .send = axiemac_send,
710 .recv = axiemac_recv,
711 .free_pkt = axiemac_free_pkt,
712 .stop = axiemac_stop,
713 .write_hwaddr = axiemac_write_hwaddr,
716 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
718 struct eth_pdata *pdata = dev_get_platdata(dev);
719 struct axidma_priv *priv = dev_get_priv(dev);
720 int node = dev_of_offset(dev);
722 const char *phy_mode;
724 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
725 priv->iobase = (struct axi_regs *)pdata->iobase;
727 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
728 "axistream-connected");
730 printf("%s: axistream is not found\n", __func__);
733 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
736 printf("%s: axi_dma register space not found\n", __func__);
739 /* RX channel offset is 0x30 */
740 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
744 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
746 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
747 priv->phy_of_handle = offset;
750 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
752 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
753 if (pdata->phy_interface == -1) {
754 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
757 priv->interface = pdata->phy_interface;
759 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
760 "xlnx,eth-hasnobuf");
762 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
763 priv->phyaddr, phy_string_for_interface(priv->interface));
768 static const struct udevice_id axi_emac_ids[] = {
769 { .compatible = "xlnx,axi-ethernet-1.00.a" },
773 U_BOOT_DRIVER(axi_emac) = {
776 .of_match = axi_emac_ids,
777 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
778 .probe = axi_emac_probe,
779 .remove = axi_emac_remove,
780 .ops = &axi_emac_ops,
781 .priv_auto_alloc_size = sizeof(struct axidma_priv),
782 .platdata_auto_alloc_size = sizeof(struct eth_pdata),