2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #if !defined(CONFIG_PHYLIB)
34 # error AXI_ETHERNET requires PHYLIB
38 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
39 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
40 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
41 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
43 /* Interrupt Status/Enable/Mask Registers bit definitions */
44 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
45 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
47 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
48 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
50 /* Transmitter Configuration (TC) Register bit definitions */
51 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
53 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
55 /* MDIO Management Configuration (MC) Register bit definitions */
56 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
58 /* MDIO Management Control Register (MCR) Register bit definitions */
59 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
60 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
61 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
62 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
63 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
64 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
65 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
66 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
68 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
71 /* Bitmasks of XAXIDMA_CR_OFFSET register */
72 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
73 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
75 /* Bitmasks of XAXIDMA_SR_OFFSET register */
76 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
78 /* Bitmask for interrupts */
79 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
80 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
81 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
83 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
84 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
85 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
89 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
91 /* Reflect dma offsets */
93 u32 control; /* DMACR */
94 u32 status; /* DMASR */
95 u32 current; /* CURDESC */
97 u32 tail; /* TAILDESC */
100 /* Private driver structures */
102 struct axidma_reg *dmatx;
103 struct axidma_reg *dmarx;
106 struct phy_device *phydev;
112 u32 next; /* Next descriptor pointer */
114 u32 phys; /* Buffer address */
118 u32 cntrl; /* Control */
119 u32 status; /* Status */
121 u32 app1; /* TX start << 16 | insert */
122 u32 app2; /* TX csum seed */
130 /* Static BDs - driver uses only one BD */
131 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
132 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
136 u32 is; /* 0xC: Interrupt status */
138 u32 ie; /* 0x14: Interrupt enable */
140 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
141 u32 tc; /* 0x408: Tx Configuration */
143 u32 emmc; /* 0x410: EMAC mode configuration */
145 u32 mdio_mc; /* 0x500: MII Management Config */
146 u32 mdio_mcr; /* 0x504: MII Management Control */
147 u32 mdio_mwd; /* 0x508: MII Management Write Data */
148 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
150 u32 uaw0; /* 0x700: Unicast address word 0 */
151 u32 uaw1; /* 0x704: Unicast address word 1 */
154 /* Use MII register 1 (MII status register) to detect PHY */
155 #define PHY_DETECT_REG 1
158 * Mask used to verify certain PHY features (or register contents)
159 * in the register above:
160 * 0x1000: 10Mbps full duplex support
161 * 0x0800: 10Mbps half duplex support
162 * 0x0008: Auto-negotiation support
164 #define PHY_DETECT_MASK 0x1808
166 static inline int mdio_wait(struct eth_device *dev)
168 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
171 /* Wait till MDIO interface is ready to accept a new transaction. */
172 while (timeout && (!(in_be32(®s->mdio_mcr)
173 & XAE_MDIO_MCR_READY_MASK))) {
178 printf("%s: Timeout\n", __func__);
184 static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
187 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
193 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
194 XAE_MDIO_MCR_PHYAD_MASK) |
195 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
196 & XAE_MDIO_MCR_REGAD_MASK) |
197 XAE_MDIO_MCR_INITIATE_MASK |
198 XAE_MDIO_MCR_OP_READ_MASK;
200 out_be32(®s->mdio_mcr, mdioctrlreg);
206 *val = in_be32(®s->mdio_mrd);
210 static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
213 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
219 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
220 XAE_MDIO_MCR_PHYAD_MASK) |
221 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
222 & XAE_MDIO_MCR_REGAD_MASK) |
223 XAE_MDIO_MCR_INITIATE_MASK |
224 XAE_MDIO_MCR_OP_WRITE_MASK;
227 out_be32(®s->mdio_mwd, data);
229 out_be32(®s->mdio_mcr, mdioctrlreg);
237 /* Setting axi emac and phy to proper setting */
238 static int setup_phy(struct eth_device *dev)
241 u32 i, speed, emmc_reg, ret;
242 struct axidma_priv *priv = dev->priv;
243 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
244 struct phy_device *phydev;
246 u32 supported = SUPPORTED_10baseT_Half |
247 SUPPORTED_10baseT_Full |
248 SUPPORTED_100baseT_Half |
249 SUPPORTED_100baseT_Full |
250 SUPPORTED_1000baseT_Half |
251 SUPPORTED_1000baseT_Full;
253 if (priv->phyaddr == -1) {
254 /* Detect the PHY address */
255 for (i = 31; i >= 0; i--) {
256 ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
257 if (!ret && (phyreg != 0xFFFF) &&
258 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
259 /* Found a valid PHY address */
261 debug("axiemac: Found valid phy address, %x\n",
268 /* Interface - look at tsec */
269 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
271 phydev->supported &= supported;
272 phydev->advertising = phydev->supported;
273 priv->phydev = phydev;
277 switch (phydev->speed) {
279 speed = XAE_EMMC_LINKSPD_1000;
282 speed = XAE_EMMC_LINKSPD_100;
285 speed = XAE_EMMC_LINKSPD_10;
291 /* Setup the emac for the phy speed */
292 emmc_reg = in_be32(®s->emmc);
293 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
296 /* Write new speed setting out to Axi Ethernet */
297 out_be32(®s->emmc, emmc_reg);
300 * Setting the operating speed of the MAC needs a delay. There
301 * doesn't seem to be register to poll, so please consider this
302 * during your application design.
309 /* STOP DMA transfers */
310 static void axiemac_halt(struct eth_device *dev)
312 struct axidma_priv *priv = dev->priv;
315 /* Stop the hardware */
316 temp = in_be32(&priv->dmatx->control);
317 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
318 out_be32(&priv->dmatx->control, temp);
320 temp = in_be32(&priv->dmarx->control);
321 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
322 out_be32(&priv->dmarx->control, temp);
324 debug("axiemac: Halted\n");
327 static int axi_ethernet_init(struct eth_device *dev)
329 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
333 * Check the status of the MgtRdy bit in the interrupt status
334 * registers. This must be done to allow the MGT clock to become stable
335 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
336 * will be valid until this bit is valid.
337 * The bit is always a 1 for all other PHY interfaces.
339 while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) {
344 printf("%s: Timeout\n", __func__);
348 /* Stop the device and reset HW */
349 /* Disable interrupts */
350 out_be32(®s->ie, 0);
352 /* Disable the receiver */
353 out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK);
356 * Stopping the receiver in mid-packet causes a dropped packet
357 * indication from HW. Clear it.
359 /* Set the interrupt status register to clear the interrupt */
360 out_be32(®s->is, XAE_INT_RXRJECT_MASK);
363 /* Set default MDIO divisor */
364 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
366 debug("axiemac: InitHw done\n");
370 static int axiemac_setup_mac(struct eth_device *dev)
372 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
374 /* Set the MAC address */
375 int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
376 (dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
377 out_be32(®s->uaw0, val);
379 val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
380 val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
381 out_be32(®s->uaw1, val);
385 /* Reset DMA engine */
386 static void axi_dma_init(struct eth_device *dev)
388 struct axidma_priv *priv = dev->priv;
391 /* Reset the engine so the hardware starts from a known state */
392 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
393 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
395 /* At the initialization time, hardware should finish reset quickly */
397 /* Check transmit/receive channel */
398 /* Reset is done when the reset bit is low */
399 if (!(in_be32(&priv->dmatx->control) |
400 in_be32(&priv->dmarx->control))
401 & XAXIDMA_CR_RESET_MASK) {
406 printf("%s: Timeout\n", __func__);
409 static int axiemac_init(struct eth_device *dev, bd_t * bis)
411 struct axidma_priv *priv = dev->priv;
412 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
415 debug("axiemac: Init started\n");
417 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
418 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
419 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
420 * would ensure a reset of AxiEthernet.
424 /* Initialize AxiEthernet hardware. */
425 if (axi_ethernet_init(dev))
428 /* Disable all RX interrupts before RxBD space setup */
429 temp = in_be32(&priv->dmarx->control);
430 temp &= ~XAXIDMA_IRQ_ALL_MASK;
431 out_be32(&priv->dmarx->control, temp);
433 /* Start DMA RX channel. Now it's ready to receive data.*/
434 out_be32(&priv->dmarx->current, (u32)&rx_bd);
437 memset(&rx_bd, 0, sizeof(rx_bd));
438 rx_bd.next = (u32)&rx_bd;
439 rx_bd.phys = (u32)&rxframe;
440 rx_bd.cntrl = sizeof(rxframe);
441 /* Flush the last BD so DMA core could see the updates */
442 flush_cache((u32)&rx_bd, sizeof(rx_bd));
444 /* It is necessary to flush rxframe because if you don't do it
445 * then cache can contain uninitialized data */
446 flush_cache((u32)&rxframe, sizeof(rxframe));
448 /* Start the hardware */
449 temp = in_be32(&priv->dmarx->control);
450 temp |= XAXIDMA_CR_RUNSTOP_MASK;
451 out_be32(&priv->dmarx->control, temp);
453 /* Rx BD is ready - start */
454 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
457 out_be32(®s->tc, XAE_TC_TX_MASK);
459 out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
462 if (!setup_phy(dev)) {
467 debug("axiemac: Init complete\n");
471 static int axiemac_send(struct eth_device *dev, volatile void *ptr, int len)
473 struct axidma_priv *priv = dev->priv;
476 if (len > PKTSIZE_ALIGN)
479 /* Flush packet to main memory to be trasfered by DMA */
480 flush_cache((u32)ptr, len);
483 memset(&tx_bd, 0, sizeof(tx_bd));
484 /* At the end of the ring, link the last BD back to the top */
485 tx_bd.next = (u32)&tx_bd;
486 tx_bd.phys = (u32)ptr;
488 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
489 XAXIDMA_BD_CTRL_TXEOF_MASK;
491 /* Flush the last BD so DMA core could see the updates */
492 flush_cache((u32)&tx_bd, sizeof(tx_bd));
494 if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
496 out_be32(&priv->dmatx->current, (u32)&tx_bd);
497 /* Start the hardware */
498 temp = in_be32(&priv->dmatx->control);
499 temp |= XAXIDMA_CR_RUNSTOP_MASK;
500 out_be32(&priv->dmatx->control, temp);
504 out_be32(&priv->dmatx->tail, (u32)&tx_bd);
506 /* Wait for transmission to complete */
507 debug("axiemac: Waiting for tx to be done\n");
509 while (timeout && (!in_be32(&priv->dmatx->status) &
510 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
515 printf("%s: Timeout\n", __func__);
519 debug("axiemac: Sending complete\n");
523 static int isrxready(struct eth_device *dev)
526 struct axidma_priv *priv = dev->priv;
528 /* Read pending interrupts */
529 status = in_be32(&priv->dmarx->status);
531 /* Acknowledge pending interrupts */
532 out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
535 * If Reception done interrupt is asserted, call RX call back function
536 * to handle the processed BDs and then raise the according flag.
538 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
544 static int axiemac_recv(struct eth_device *dev)
547 struct axidma_priv *priv = dev->priv;
550 /* Wait for an incoming packet */
554 debug("axiemac: RX data ready\n");
556 /* Disable IRQ for a moment till packet is handled */
557 temp = in_be32(&priv->dmarx->control);
558 temp &= ~XAXIDMA_IRQ_ALL_MASK;
559 out_be32(&priv->dmarx->control, temp);
561 length = rx_bd.app4 & 0xFFFF; /* max length mask */
563 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
565 /* Pass the received frame up for processing */
567 NetReceive(rxframe, length);
570 /* It is useful to clear buffer to be sure that it is consistent */
571 memset(rxframe, 0, sizeof(rxframe));
574 /* Clear the whole buffer and setup it again - all flags are cleared */
575 memset(&rx_bd, 0, sizeof(rx_bd));
576 rx_bd.next = (u32)&rx_bd;
577 rx_bd.phys = (u32)&rxframe;
578 rx_bd.cntrl = sizeof(rxframe);
581 flush_cache((u32)&rx_bd, sizeof(rx_bd));
583 /* It is necessary to flush rxframe because if you don't do it
584 * then cache will contain previous packet */
585 flush_cache((u32)&rxframe, sizeof(rxframe));
587 /* Rx BD is ready - start again */
588 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
590 debug("axiemac: RX completed, framelength = %d\n", length);
595 static int axiemac_miiphy_read(const char *devname, uchar addr,
596 uchar reg, ushort *val)
598 struct eth_device *dev = eth_get_dev();
601 ret = phyread(dev, addr, reg, val);
602 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
606 static int axiemac_miiphy_write(const char *devname, uchar addr,
607 uchar reg, ushort val)
609 struct eth_device *dev = eth_get_dev();
611 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
612 return phywrite(dev, addr, reg, val);
615 static int axiemac_bus_reset(struct mii_dev *bus)
617 debug("axiemac: Bus reset\n");
621 int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
622 unsigned long dma_addr)
624 struct eth_device *dev;
625 struct axidma_priv *priv;
627 dev = calloc(1, sizeof(struct eth_device));
631 dev->priv = calloc(1, sizeof(struct axidma_priv));
632 if (dev->priv == NULL) {
638 sprintf(dev->name, "aximac.%lx", base_addr);
640 dev->iobase = base_addr;
641 priv->dmatx = (struct axidma_reg *)dma_addr;
642 /* RX channel offset is 0x30 */
643 priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
644 dev->init = axiemac_init;
645 dev->halt = axiemac_halt;
646 dev->send = axiemac_send;
647 dev->recv = axiemac_recv;
648 dev->write_hwaddr = axiemac_setup_mac;
650 #ifdef CONFIG_PHY_ADDR
651 priv->phyaddr = CONFIG_PHY_ADDR;
658 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
659 miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
660 priv->bus = miiphy_get_dev_by_name(dev->name);
661 priv->bus->reset = axiemac_bus_reset;