1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011 PetaLogix
5 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
18 DECLARE_GLOBAL_DATA_PTR;
21 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
22 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
23 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
24 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
26 /* Interrupt Status/Enable/Mask Registers bit definitions */
27 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
28 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
30 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
31 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
33 /* Transmitter Configuration (TC) Register bit definitions */
34 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
36 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
38 /* MDIO Management Configuration (MC) Register bit definitions */
39 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
41 /* MDIO Management Control Register (MCR) Register bit definitions */
42 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
43 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
44 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
45 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
46 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
47 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
48 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
49 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
51 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
53 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
56 /* Bitmasks of XAXIDMA_CR_OFFSET register */
57 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
58 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
60 /* Bitmasks of XAXIDMA_SR_OFFSET register */
61 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
63 /* Bitmask for interrupts */
64 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
65 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
66 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
68 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
69 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
70 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
74 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
76 /* Reflect dma offsets */
78 u32 control; /* DMACR */
79 u32 status; /* DMASR */
80 u32 current; /* CURDESC low 32 bit */
81 u32 current_hi; /* CURDESC high 32 bit */
82 u32 tail; /* TAILDESC low 32 bit */
83 u32 tail_hi; /* TAILDESC high 32 bit */
86 /* Private driver structures */
88 struct axidma_reg *dmatx;
89 struct axidma_reg *dmarx;
91 struct axi_regs *iobase;
92 phy_interface_t interface;
93 struct phy_device *phydev;
101 u32 next; /* Next descriptor pointer */
103 u32 phys; /* Buffer address */
107 u32 cntrl; /* Control */
108 u32 status; /* Status */
110 u32 app1; /* TX start << 16 | insert */
111 u32 app2; /* TX csum seed */
119 /* Static BDs - driver uses only one BD */
120 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
121 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
125 u32 is; /* 0xC: Interrupt status */
127 u32 ie; /* 0x14: Interrupt enable */
129 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
130 u32 tc; /* 0x408: Tx Configuration */
132 u32 emmc; /* 0x410: EMAC mode configuration */
134 u32 mdio_mc; /* 0x500: MII Management Config */
135 u32 mdio_mcr; /* 0x504: MII Management Control */
136 u32 mdio_mwd; /* 0x508: MII Management Write Data */
137 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
139 u32 uaw0; /* 0x700: Unicast address word 0 */
140 u32 uaw1; /* 0x704: Unicast address word 1 */
143 /* Use MII register 1 (MII status register) to detect PHY */
144 #define PHY_DETECT_REG 1
147 * Mask used to verify certain PHY features (or register contents)
148 * in the register above:
149 * 0x1000: 10Mbps full duplex support
150 * 0x0800: 10Mbps half duplex support
151 * 0x0008: Auto-negotiation support
153 #define PHY_DETECT_MASK 0x1808
155 static inline int mdio_wait(struct axi_regs *regs)
159 /* Wait till MDIO interface is ready to accept a new transaction. */
160 while (timeout && (!(readl(®s->mdio_mcr)
161 & XAE_MDIO_MCR_READY_MASK))) {
166 printf("%s: Timeout\n", __func__);
173 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
174 * @bd: pointer to BD descriptor structure
175 * @desc: Address offset of DMA descriptors
177 * This function writes the value into the corresponding Axi DMA register.
179 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
181 #if defined(CONFIG_PHYS_64BIT)
184 writel((u32)bd, desc);
188 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
191 struct axi_regs *regs = priv->iobase;
197 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
198 XAE_MDIO_MCR_PHYAD_MASK) |
199 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
200 & XAE_MDIO_MCR_REGAD_MASK) |
201 XAE_MDIO_MCR_INITIATE_MASK |
202 XAE_MDIO_MCR_OP_READ_MASK;
204 writel(mdioctrlreg, ®s->mdio_mcr);
210 *val = readl(®s->mdio_mrd);
214 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
217 struct axi_regs *regs = priv->iobase;
223 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
224 XAE_MDIO_MCR_PHYAD_MASK) |
225 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
226 & XAE_MDIO_MCR_REGAD_MASK) |
227 XAE_MDIO_MCR_INITIATE_MASK |
228 XAE_MDIO_MCR_OP_WRITE_MASK;
231 writel(data, ®s->mdio_mwd);
233 writel(mdioctrlreg, ®s->mdio_mcr);
241 static int axiemac_phy_init(struct udevice *dev)
245 struct axidma_priv *priv = dev_get_priv(dev);
246 struct axi_regs *regs = priv->iobase;
247 struct phy_device *phydev;
249 u32 supported = SUPPORTED_10baseT_Half |
250 SUPPORTED_10baseT_Full |
251 SUPPORTED_100baseT_Half |
252 SUPPORTED_100baseT_Full |
253 SUPPORTED_1000baseT_Half |
254 SUPPORTED_1000baseT_Full;
256 /* Set default MDIO divisor */
257 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
259 if (priv->phyaddr == -1) {
260 /* Detect the PHY address */
261 for (i = 31; i >= 0; i--) {
262 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
263 if (!ret && (phyreg != 0xFFFF) &&
264 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
265 /* Found a valid PHY address */
267 debug("axiemac: Found valid phy address, %x\n",
274 /* Interface - look at tsec */
275 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
277 phydev->supported &= supported;
278 phydev->advertising = phydev->supported;
279 priv->phydev = phydev;
280 if (priv->phy_of_handle)
281 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
287 /* Setting axi emac and phy to proper setting */
288 static int setup_phy(struct udevice *dev)
291 u32 speed, emmc_reg, ret;
292 struct axidma_priv *priv = dev_get_priv(dev);
293 struct axi_regs *regs = priv->iobase;
294 struct phy_device *phydev = priv->phydev;
296 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
298 * In SGMII cases the isolate bit might set
299 * after DMA and ethernet resets and hence
300 * check and clear if set.
302 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
305 if (temp & BMCR_ISOLATE) {
306 temp &= ~BMCR_ISOLATE;
307 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
313 if (phy_startup(phydev)) {
314 printf("axiemac: could not initialize PHY %s\n",
319 printf("%s: No link.\n", phydev->dev->name);
323 switch (phydev->speed) {
325 speed = XAE_EMMC_LINKSPD_1000;
328 speed = XAE_EMMC_LINKSPD_100;
331 speed = XAE_EMMC_LINKSPD_10;
337 /* Setup the emac for the phy speed */
338 emmc_reg = readl(®s->emmc);
339 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
342 /* Write new speed setting out to Axi Ethernet */
343 writel(emmc_reg, ®s->emmc);
346 * Setting the operating speed of the MAC needs a delay. There
347 * doesn't seem to be register to poll, so please consider this
348 * during your application design.
355 /* STOP DMA transfers */
356 static void axiemac_stop(struct udevice *dev)
358 struct axidma_priv *priv = dev_get_priv(dev);
361 /* Stop the hardware */
362 temp = readl(&priv->dmatx->control);
363 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
364 writel(temp, &priv->dmatx->control);
366 temp = readl(&priv->dmarx->control);
367 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
368 writel(temp, &priv->dmarx->control);
370 debug("axiemac: Halted\n");
373 static int axi_ethernet_init(struct axidma_priv *priv)
375 struct axi_regs *regs = priv->iobase;
379 * Check the status of the MgtRdy bit in the interrupt status
380 * registers. This must be done to allow the MGT clock to become stable
381 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
382 * will be valid until this bit is valid.
383 * The bit is always a 1 for all other PHY interfaces.
384 * Interrupt status and enable registers are not available in non
385 * processor mode and hence bypass in this mode
387 if (!priv->eth_hasnobuf) {
388 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
391 printf("%s: Timeout\n", __func__);
396 * Stop the device and reset HW
399 writel(0, ®s->ie);
402 /* Disable the receiver */
403 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
406 * Stopping the receiver in mid-packet causes a dropped packet
407 * indication from HW. Clear it.
409 if (!priv->eth_hasnobuf) {
410 /* Set the interrupt status register to clear the interrupt */
411 writel(XAE_INT_RXRJECT_MASK, ®s->is);
415 /* Set default MDIO divisor */
416 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
418 debug("axiemac: InitHw done\n");
422 static int axiemac_write_hwaddr(struct udevice *dev)
424 struct eth_pdata *pdata = dev_get_platdata(dev);
425 struct axidma_priv *priv = dev_get_priv(dev);
426 struct axi_regs *regs = priv->iobase;
428 /* Set the MAC address */
429 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
430 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
431 writel(val, ®s->uaw0);
433 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
434 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
435 writel(val, ®s->uaw1);
439 /* Reset DMA engine */
440 static void axi_dma_init(struct axidma_priv *priv)
444 /* Reset the engine so the hardware starts from a known state */
445 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
446 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
448 /* At the initialization time, hardware should finish reset quickly */
450 /* Check transmit/receive channel */
451 /* Reset is done when the reset bit is low */
452 if (!((readl(&priv->dmatx->control) |
453 readl(&priv->dmarx->control))
454 & XAXIDMA_CR_RESET_MASK)) {
459 printf("%s: Timeout\n", __func__);
462 static int axiemac_start(struct udevice *dev)
464 struct axidma_priv *priv = dev_get_priv(dev);
465 struct axi_regs *regs = priv->iobase;
468 debug("axiemac: Init started\n");
470 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
471 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
472 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
473 * would ensure a reset of AxiEthernet.
477 /* Initialize AxiEthernet hardware. */
478 if (axi_ethernet_init(priv))
481 /* Disable all RX interrupts before RxBD space setup */
482 temp = readl(&priv->dmarx->control);
483 temp &= ~XAXIDMA_IRQ_ALL_MASK;
484 writel(temp, &priv->dmarx->control);
486 /* Start DMA RX channel. Now it's ready to receive data.*/
487 axienet_dma_write(&rx_bd, &priv->dmarx->current);
490 memset(&rx_bd, 0, sizeof(rx_bd));
491 rx_bd.next = (u32)&rx_bd;
492 rx_bd.phys = (u32)&rxframe;
493 rx_bd.cntrl = sizeof(rxframe);
494 /* Flush the last BD so DMA core could see the updates */
495 flush_cache((u32)&rx_bd, sizeof(rx_bd));
497 /* It is necessary to flush rxframe because if you don't do it
498 * then cache can contain uninitialized data */
499 flush_cache((u32)&rxframe, sizeof(rxframe));
501 /* Start the hardware */
502 temp = readl(&priv->dmarx->control);
503 temp |= XAXIDMA_CR_RUNSTOP_MASK;
504 writel(temp, &priv->dmarx->control);
506 /* Rx BD is ready - start */
507 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
510 writel(XAE_TC_TX_MASK, ®s->tc);
512 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
515 if (!setup_phy(dev)) {
520 debug("axiemac: Init complete\n");
524 static int axiemac_send(struct udevice *dev, void *ptr, int len)
526 struct axidma_priv *priv = dev_get_priv(dev);
529 if (len > PKTSIZE_ALIGN)
532 /* Flush packet to main memory to be trasfered by DMA */
533 flush_cache((u32)ptr, len);
536 memset(&tx_bd, 0, sizeof(tx_bd));
537 /* At the end of the ring, link the last BD back to the top */
538 tx_bd.next = (u32)&tx_bd;
539 tx_bd.phys = (u32)ptr;
541 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
542 XAXIDMA_BD_CTRL_TXEOF_MASK;
544 /* Flush the last BD so DMA core could see the updates */
545 flush_cache((u32)&tx_bd, sizeof(tx_bd));
547 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
549 axienet_dma_write(&tx_bd, &priv->dmatx->current);
550 /* Start the hardware */
551 temp = readl(&priv->dmatx->control);
552 temp |= XAXIDMA_CR_RUNSTOP_MASK;
553 writel(temp, &priv->dmatx->control);
557 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
559 /* Wait for transmission to complete */
560 debug("axiemac: Waiting for tx to be done\n");
562 while (timeout && (!(readl(&priv->dmatx->status) &
563 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
568 printf("%s: Timeout\n", __func__);
572 debug("axiemac: Sending complete\n");
576 static int isrxready(struct axidma_priv *priv)
580 /* Read pending interrupts */
581 status = readl(&priv->dmarx->status);
583 /* Acknowledge pending interrupts */
584 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
587 * If Reception done interrupt is asserted, call RX call back function
588 * to handle the processed BDs and then raise the according flag.
590 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
596 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
599 struct axidma_priv *priv = dev_get_priv(dev);
602 /* Wait for an incoming packet */
603 if (!isrxready(priv))
606 debug("axiemac: RX data ready\n");
608 /* Disable IRQ for a moment till packet is handled */
609 temp = readl(&priv->dmarx->control);
610 temp &= ~XAXIDMA_IRQ_ALL_MASK;
611 writel(temp, &priv->dmarx->control);
612 if (!priv->eth_hasnobuf)
613 length = rx_bd.app4 & 0xFFFF; /* max length mask */
615 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
618 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
625 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
627 struct axidma_priv *priv = dev_get_priv(dev);
630 /* It is useful to clear buffer to be sure that it is consistent */
631 memset(rxframe, 0, sizeof(rxframe));
634 /* Clear the whole buffer and setup it again - all flags are cleared */
635 memset(&rx_bd, 0, sizeof(rx_bd));
636 rx_bd.next = (u32)&rx_bd;
637 rx_bd.phys = (u32)&rxframe;
638 rx_bd.cntrl = sizeof(rxframe);
641 flush_cache((u32)&rx_bd, sizeof(rx_bd));
643 /* It is necessary to flush rxframe because if you don't do it
644 * then cache will contain previous packet */
645 flush_cache((u32)&rxframe, sizeof(rxframe));
647 /* Rx BD is ready - start again */
648 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
650 debug("axiemac: RX completed, framelength = %d\n", length);
655 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
661 ret = phyread(bus->priv, addr, reg, &value);
662 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
667 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
670 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
671 return phywrite(bus->priv, addr, reg, value);
674 static int axi_emac_probe(struct udevice *dev)
676 struct axidma_priv *priv = dev_get_priv(dev);
679 priv->bus = mdio_alloc();
680 priv->bus->read = axiemac_miiphy_read;
681 priv->bus->write = axiemac_miiphy_write;
682 priv->bus->priv = priv;
684 ret = mdio_register_seq(priv->bus, dev->seq);
688 axiemac_phy_init(dev);
693 static int axi_emac_remove(struct udevice *dev)
695 struct axidma_priv *priv = dev_get_priv(dev);
698 mdio_unregister(priv->bus);
699 mdio_free(priv->bus);
704 static const struct eth_ops axi_emac_ops = {
705 .start = axiemac_start,
706 .send = axiemac_send,
707 .recv = axiemac_recv,
708 .free_pkt = axiemac_free_pkt,
709 .stop = axiemac_stop,
710 .write_hwaddr = axiemac_write_hwaddr,
713 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
715 struct eth_pdata *pdata = dev_get_platdata(dev);
716 struct axidma_priv *priv = dev_get_priv(dev);
717 int node = dev_of_offset(dev);
719 const char *phy_mode;
721 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
722 priv->iobase = (struct axi_regs *)pdata->iobase;
724 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
725 "axistream-connected");
727 printf("%s: axistream is not found\n", __func__);
730 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
733 printf("%s: axi_dma register space not found\n", __func__);
736 /* RX channel offset is 0x30 */
737 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
741 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
743 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
744 priv->phy_of_handle = offset;
747 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
749 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
750 if (pdata->phy_interface == -1) {
751 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
754 priv->interface = pdata->phy_interface;
756 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
757 "xlnx,eth-hasnobuf");
759 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
760 priv->phyaddr, phy_string_for_interface(priv->interface));
765 static const struct udevice_id axi_emac_ids[] = {
766 { .compatible = "xlnx,axi-ethernet-1.00.a" },
770 U_BOOT_DRIVER(axi_emac) = {
773 .of_match = axi_emac_ids,
774 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
775 .probe = axi_emac_probe,
776 .remove = axi_emac_remove,
777 .ops = &axi_emac_ops,
778 .priv_auto_alloc_size = sizeof(struct axidma_priv),
779 .platdata_auto_alloc_size = sizeof(struct eth_pdata),