drivers/net/wireless/ti/wl12xx/main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This file is part of wl1271
   4  *
   5  * Copyright (C) 2008-2010 Nokia Corporation
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/mod_devicetable.h>
  10 #include <linux/platform_device.h>
  11
  12 #include <linux/err.h>
  13
  14 #include "../wlcore/wlcore.h"
  15 #include "../wlcore/debug.h"
  16 #include "../wlcore/io.h"
  17 #include "../wlcore/acx.h"
  18 #include "../wlcore/tx.h"
  19 #include "../wlcore/rx.h"
  20 #include "../wlcore/boot.h"
  21
  22 #include "wl12xx.h"
  23 #include "reg.h"
  24 #include "cmd.h"
  25 #include "acx.h"
  26 #include "scan.h"
  27 #include "event.h"
  28 #include "debugfs.h"
  29 #include "conf.h"
  30
  31 static char *fref_param;
  32 static char *tcxo_param;
  33
  34 static struct wlcore_conf wl12xx_conf = {
  35         .sg = {
  36                 .params = {
  37                         [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
  38                         [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
  39                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
  40                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
  41                         [WL12XX_CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
  42                         [WL12XX_CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
  43                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
  44                         [WL12XX_CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
  45                         [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
  46                         [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
  47                         [WL12XX_CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
  48                         [WL12XX_CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
  49                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
  50                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
  51                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
  52                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
  53                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
  54                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
  55                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
  56                         [WL12XX_CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
  57                         [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
  58                         [WL12XX_CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
  59                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
  60                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
  61                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
  62                         [WL12XX_CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
  63                         /* active scan params */
  64                         [WL12XX_CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
  65                         [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
  66                         [WL12XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
  67                         /* passive scan params */
  68                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_BR] = 800,
  69                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_A2DP_EDR] = 200,
  70                         [WL12XX_CONF_SG_PASSIVE_SCAN_DUR_FACTOR_HV3] = 200,
  71                         /* passive scan in dual antenna params */
  72                         [WL12XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
  73                         [WL12XX_CONF_SG_BCN_HV3_COLL_THR_IN_PASSIVE_SCAN] = 0,
  74                         [WL12XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN] = 0,
  75                         /* general params */
  76                         [WL12XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
  77                         [WL12XX_CONF_SG_ANTENNA_CONFIGURATION] = 0,
  78                         [WL12XX_CONF_SG_BEACON_MISS_PERCENT] = 60,
  79                         [WL12XX_CONF_SG_DHCP_TIME] = 5000,
  80                         [WL12XX_CONF_SG_RXT] = 1200,
  81                         [WL12XX_CONF_SG_TXT] = 1000,
  82                         [WL12XX_CONF_SG_ADAPTIVE_RXT_TXT] = 1,
  83                         [WL12XX_CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
  84                         [WL12XX_CONF_SG_HV3_MAX_SERVED] = 6,
  85                         [WL12XX_CONF_SG_PS_POLL_TIMEOUT] = 10,
  86                         [WL12XX_CONF_SG_UPSD_TIMEOUT] = 10,
  87                         [WL12XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
  88                         [WL12XX_CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
  89                         [WL12XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
  90                         /* AP params */
  91                         [WL12XX_CONF_AP_BEACON_MISS_TX] = 3,
  92                         [WL12XX_CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
  93                         [WL12XX_CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
  94                         [WL12XX_CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
  95                         [WL12XX_CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
  96                         [WL12XX_CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
  97                         /* CTS Diluting params */
  98                         [WL12XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
  99                         [WL12XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 100                 },
 101                 .state = CONF_SG_PROTECTIVE,
 102         },
 103         .rx = {
 104                 .rx_msdu_life_time           = 512000,
 105                 .packet_detection_threshold  = 0,
 106                 .ps_poll_timeout             = 15,
 107                 .upsd_timeout                = 15,
 108                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 109                 .rx_cca_threshold            = 0,
 110                 .irq_blk_threshold           = 0xFFFF,
 111                 .irq_pkt_threshold           = 0,
 112                 .irq_timeout                 = 600,
 113                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 114         },
 115         .tx = {
 116                 .tx_energy_detection         = 0,
 117                 .sta_rc_conf                 = {
 118                         .enabled_rates       = 0,
 119                         .short_retry_limit   = 10,
 120                         .long_retry_limit    = 10,
 121                         .aflags              = 0,
 122                 },
 123                 .ac_conf_count               = 4,
 124                 .ac_conf                     = {
 125                         [CONF_TX_AC_BE] = {
 126                                 .ac          = CONF_TX_AC_BE,
 127                                 .cw_min      = 15,
 128                                 .cw_max      = 63,
 129                                 .aifsn       = 3,
 130                                 .tx_op_limit = 0,
 131                         },
 132                         [CONF_TX_AC_BK] = {
 133                                 .ac          = CONF_TX_AC_BK,
 134                                 .cw_min      = 15,
 135                                 .cw_max      = 63,
 136                                 .aifsn       = 7,
 137                                 .tx_op_limit = 0,
 138                         },
 139                         [CONF_TX_AC_VI] = {
 140                                 .ac          = CONF_TX_AC_VI,
 141                                 .cw_min      = 15,
 142                                 .cw_max      = 63,
 143                                 .aifsn       = CONF_TX_AIFS_PIFS,
 144                                 .tx_op_limit = 3008,
 145                         },
 146                         [CONF_TX_AC_VO] = {
 147                                 .ac          = CONF_TX_AC_VO,
 148                                 .cw_min      = 15,
 149                                 .cw_max      = 63,
 150                                 .aifsn       = CONF_TX_AIFS_PIFS,
 151                                 .tx_op_limit = 1504,
 152                         },
 153                 },
 154                 .max_tx_retries = 100,
 155                 .ap_aging_period = 300,
 156                 .tid_conf_count = 4,
 157                 .tid_conf = {
 158                         [CONF_TX_AC_BE] = {
 159                                 .queue_id    = CONF_TX_AC_BE,
 160                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 161                                 .tsid        = CONF_TX_AC_BE,
 162                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 163                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 164                                 .apsd_conf   = {0, 0},
 165                         },
 166                         [CONF_TX_AC_BK] = {
 167                                 .queue_id    = CONF_TX_AC_BK,
 168                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 169                                 .tsid        = CONF_TX_AC_BK,
 170                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 171                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 172                                 .apsd_conf   = {0, 0},
 173                         },
 174                         [CONF_TX_AC_VI] = {
 175                                 .queue_id    = CONF_TX_AC_VI,
 176                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 177                                 .tsid        = CONF_TX_AC_VI,
 178                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 179                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 180                                 .apsd_conf   = {0, 0},
 181                         },
 182                         [CONF_TX_AC_VO] = {
 183                                 .queue_id    = CONF_TX_AC_VO,
 184                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 185                                 .tsid        = CONF_TX_AC_VO,
 186                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 187                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 188                                 .apsd_conf   = {0, 0},
 189                         },
 190                 },
 191                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 192                 .tx_compl_timeout            = 700,
 193                 .tx_compl_threshold          = 4,
 194                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 195                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 196                 .tmpl_short_retry_limit      = 10,
 197                 .tmpl_long_retry_limit       = 10,
 198                 .tx_watchdog_timeout         = 5000,
 199                 .slow_link_thold             = 3,
 200                 .fast_link_thold             = 10,
 201         },
 202         .conn = {
 203                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 204                 .listen_interval             = 1,
 205                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 206                 .suspend_listen_interval     = 3,
 207                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 208                 .bcn_filt_ie_count           = 3,
 209                 .bcn_filt_ie = {
 210                         [0] = {
 211                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 212                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 213                         },
 214                         [1] = {
 215                                 .ie          = WLAN_EID_HT_OPERATION,
 216                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 217                         },
 218                         [2] = {
 219                                 .ie          = WLAN_EID_ERP_INFO,
 220                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 221                         },
 222                 },
 223                 .synch_fail_thold            = 12,
 224                 .bss_lose_timeout            = 400,
 225                 .beacon_rx_timeout           = 10000,
 226                 .broadcast_timeout           = 20000,
 227                 .rx_broadcast_in_ps          = 1,
 228                 .ps_poll_threshold           = 10,
 229                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 230                 .bet_max_consecutive         = 50,
 231                 .psm_entry_retries           = 8,
 232                 .psm_exit_retries            = 16,
 233                 .psm_entry_nullfunc_retries  = 3,
 234                 .dynamic_ps_timeout          = 1500,
 235                 .forced_ps                   = false,
 236                 .keep_alive_interval         = 55000,
 237                 .max_listen_interval         = 20,
 238                 .sta_sleep_auth              = WL1271_PSM_ILLEGAL,
 239                 .suspend_rx_ba_activity      = 0,
 240         },
 241         .itrim = {
 242                 .enable = false,
 243                 .timeout = 50000,
 244         },
 245         .pm_config = {
 246                 .host_clk_settling_time = 5000,
 247                 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
 248         },
 249         .roam_trigger = {
 250                 .trigger_pacing               = 1,
 251                 .avg_weight_rssi_beacon       = 20,
 252                 .avg_weight_rssi_data         = 10,
 253                 .avg_weight_snr_beacon        = 20,
 254                 .avg_weight_snr_data          = 10,
 255         },
 256         .scan = {
 257                 .min_dwell_time_active        = 7500,
 258                 .max_dwell_time_active        = 30000,
 259                 .min_dwell_time_active_long   = 25000,
 260                 .max_dwell_time_active_long   = 50000,
 261                 .dwell_time_passive           = 100000,
 262                 .dwell_time_dfs               = 150000,
 263                 .num_probe_reqs               = 2,
 264                 .split_scan_timeout           = 50000,
 265         },
 266         .sched_scan = {
 267                 /*
 268                  * Values are in TU/1000 but since sched scan FW command
 269                  * params are in TUs rounding up may occur.
 270                  */
 271                 .base_dwell_time                = 7500,
 272                 .max_dwell_time_delta           = 22500,
 273                 /* based on 250bits per probe @1Mbps */
 274                 .dwell_time_delta_per_probe     = 2000,
 275                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 276                 .dwell_time_delta_per_probe_5   = 350,
 277                 .dwell_time_passive             = 100000,
 278                 .dwell_time_dfs                 = 150000,
 279                 .num_probe_reqs                 = 2,
 280                 .rssi_threshold                 = -90,
 281                 .snr_threshold                  = 0,
 282         },
 283         .ht = {
 284                 .rx_ba_win_size = 8,
 285                 .tx_ba_win_size = 64,
 286                 .inactivity_timeout = 10000,
 287                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 288         },
 289         /*
 290          * Memory config for wl127x chips is given in the
 291          * wl12xx_default_priv_conf struct. The below configuration is
 292          * for wl128x chips.
 293          */
 294         .mem = {
 295                 .num_stations                 = 1,
 296                 .ssid_profiles                = 1,
 297                 .rx_block_num                 = 40,
 298                 .tx_min_block_num             = 40,
 299                 .dynamic_memory               = 1,
 300                 .min_req_tx_blocks            = 45,
 301                 .min_req_rx_blocks            = 22,
 302                 .tx_min                       = 27,
 303         },
 304         .fm_coex = {
 305                 .enable                       = true,
 306                 .swallow_period               = 5,
 307                 .n_divider_fref_set_1         = 0xff,       /* default */
 308                 .n_divider_fref_set_2         = 12,
 309                 .m_divider_fref_set_1         = 0xffff,
 310                 .m_divider_fref_set_2         = 148,        /* default */
 311                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 312                 .ldo_stabilization_time       = 0xffff,     /* default */
 313                 .fm_disturbed_band_margin     = 0xff,       /* default */
 314                 .swallow_clk_diff             = 0xff,       /* default */
 315         },
 316         .rx_streaming = {
 317                 .duration                      = 150,
 318                 .queues                        = 0x1,
 319                 .interval                      = 20,
 320                 .always                        = 0,
 321         },
 322         .fwlog = {
 323                 .mode                         = WL12XX_FWLOG_CONTINUOUS,
 324                 .mem_blocks                   = 2,
 325                 .severity                     = 0,
 326                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 327                 .output                       = WL12XX_FWLOG_OUTPUT_DBG_PINS,
 328                 .threshold                    = 0,
 329         },
 330         .rate = {
 331                 .rate_retry_score = 32000,
 332                 .per_add = 8192,
 333                 .per_th1 = 2048,
 334                 .per_th2 = 4096,
 335                 .max_per = 8100,
 336                 .inverse_curiosity_factor = 5,
 337                 .tx_fail_low_th = 4,
 338                 .tx_fail_high_th = 10,
 339                 .per_alpha_shift = 4,
 340                 .per_add_shift = 13,
 341                 .per_beta1_shift = 10,
 342                 .per_beta2_shift = 8,
 343                 .rate_check_up = 2,
 344                 .rate_check_down = 12,
 345                 .rate_retry_policy = {
 346                         0x00, 0x00, 0x00, 0x00, 0x00,
 347                         0x00, 0x00, 0x00, 0x00, 0x00,
 348                         0x00, 0x00, 0x00,
 349                 },
 350         },
 351         .hangover = {
 352                 .recover_time               = 0,
 353                 .hangover_period            = 20,
 354                 .dynamic_mode               = 1,
 355                 .early_termination_mode     = 1,
 356                 .max_period                 = 20,
 357                 .min_period                 = 1,
 358                 .increase_delta             = 1,
 359                 .decrease_delta             = 2,
 360                 .quiet_time                 = 4,
 361                 .increase_time              = 1,
 362                 .window_size                = 16,
 363         },
 364         .recovery = {
 365                 .bug_on_recovery            = 0,
 366                 .no_recovery                = 0,
 367         },
 368 };
 369
 370 static struct wl12xx_priv_conf wl12xx_default_priv_conf = {
 371         .rf = {
 372                 .tx_per_channel_power_compensation_2 = {
 373                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 374                 },
 375                 .tx_per_channel_power_compensation_5 = {
 376                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 377                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 378                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 379                 },
 380         },
 381         .mem_wl127x = {
 382                 .num_stations                 = 1,
 383                 .ssid_profiles                = 1,
 384                 .rx_block_num                 = 70,
 385                 .tx_min_block_num             = 40,
 386                 .dynamic_memory               = 1,
 387                 .min_req_tx_blocks            = 100,
 388                 .min_req_rx_blocks            = 22,
 389                 .tx_min                       = 27,
 390         },
 391
 392 };
 393
 394 #define WL12XX_TX_HW_BLOCK_SPARE_DEFAULT        1
 395 #define WL12XX_TX_HW_BLOCK_GEM_SPARE            2
 396 #define WL12XX_TX_HW_BLOCK_SIZE                 252
 397
 398 static const u8 wl12xx_rate_to_idx_2ghz[] = {
 399         /* MCS rates are used only with 11n */
 400         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 401         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 402         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 403         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 404         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 405         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 406         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 407         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 408         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 409
 410         11,                            /* WL12XX_CONF_HW_RXTX_RATE_54   */
 411         10,                            /* WL12XX_CONF_HW_RXTX_RATE_48   */
 412         9,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 413         8,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 414
 415         /* TI-specific rate */
 416         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 417
 418         7,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 419         6,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 420         3,                             /* WL12XX_CONF_HW_RXTX_RATE_11   */
 421         5,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 422         4,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 423         2,                             /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 424         1,                             /* WL12XX_CONF_HW_RXTX_RATE_2    */
 425         0                              /* WL12XX_CONF_HW_RXTX_RATE_1    */
 426 };
 427
 428 static const u8 wl12xx_rate_to_idx_5ghz[] = {
 429         /* MCS rates are used only with 11n */
 430         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI */
 431         7,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS7 */
 432         6,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS6 */
 433         5,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS5 */
 434         4,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS4 */
 435         3,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS3 */
 436         2,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS2 */
 437         1,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS1 */
 438         0,                             /* WL12XX_CONF_HW_RXTX_RATE_MCS0 */
 439
 440         7,                             /* WL12XX_CONF_HW_RXTX_RATE_54   */
 441         6,                             /* WL12XX_CONF_HW_RXTX_RATE_48   */
 442         5,                             /* WL12XX_CONF_HW_RXTX_RATE_36   */
 443         4,                             /* WL12XX_CONF_HW_RXTX_RATE_24   */
 444
 445         /* TI-specific rate */
 446         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_22   */
 447
 448         3,                             /* WL12XX_CONF_HW_RXTX_RATE_18   */
 449         2,                             /* WL12XX_CONF_HW_RXTX_RATE_12   */
 450         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_11   */
 451         1,                             /* WL12XX_CONF_HW_RXTX_RATE_9    */
 452         0,                             /* WL12XX_CONF_HW_RXTX_RATE_6    */
 453         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_5_5  */
 454         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL12XX_CONF_HW_RXTX_RATE_2    */
 455         CONF_HW_RXTX_RATE_UNSUPPORTED  /* WL12XX_CONF_HW_RXTX_RATE_1    */
 456 };
 457
 458 static const u8 *wl12xx_band_rate_to_idx[] = {
 459         [NL80211_BAND_2GHZ] = wl12xx_rate_to_idx_2ghz,
 460         [NL80211_BAND_5GHZ] = wl12xx_rate_to_idx_5ghz
 461 };
 462
 463 enum wl12xx_hw_rates {
 464         WL12XX_CONF_HW_RXTX_RATE_MCS7_SGI = 0,
 465         WL12XX_CONF_HW_RXTX_RATE_MCS7,
 466         WL12XX_CONF_HW_RXTX_RATE_MCS6,
 467         WL12XX_CONF_HW_RXTX_RATE_MCS5,
 468         WL12XX_CONF_HW_RXTX_RATE_MCS4,
 469         WL12XX_CONF_HW_RXTX_RATE_MCS3,
 470         WL12XX_CONF_HW_RXTX_RATE_MCS2,
 471         WL12XX_CONF_HW_RXTX_RATE_MCS1,
 472         WL12XX_CONF_HW_RXTX_RATE_MCS0,
 473         WL12XX_CONF_HW_RXTX_RATE_54,
 474         WL12XX_CONF_HW_RXTX_RATE_48,
 475         WL12XX_CONF_HW_RXTX_RATE_36,
 476         WL12XX_CONF_HW_RXTX_RATE_24,
 477         WL12XX_CONF_HW_RXTX_RATE_22,
 478         WL12XX_CONF_HW_RXTX_RATE_18,
 479         WL12XX_CONF_HW_RXTX_RATE_12,
 480         WL12XX_CONF_HW_RXTX_RATE_11,
 481         WL12XX_CONF_HW_RXTX_RATE_9,
 482         WL12XX_CONF_HW_RXTX_RATE_6,
 483         WL12XX_CONF_HW_RXTX_RATE_5_5,
 484         WL12XX_CONF_HW_RXTX_RATE_2,
 485         WL12XX_CONF_HW_RXTX_RATE_1,
 486         WL12XX_CONF_HW_RXTX_RATE_MAX,
 487 };
 488
 489 static struct wlcore_partition_set wl12xx_ptable[PART_TABLE_LEN] = {
 490         [PART_DOWN] = {
 491                 .mem = {
 492                         .start = 0x00000000,
 493                         .size  = 0x000177c0
 494                 },
 495                 .reg = {
 496                         .start = REGISTERS_BASE,
 497                         .size  = 0x00008800
 498                 },
 499                 .mem2 = {
 500                         .start = 0x00000000,
 501                         .size  = 0x00000000
 502                 },
 503                 .mem3 = {
 504                         .start = 0x00000000,
 505                         .size  = 0x00000000
 506                 },
 507         },
 508
 509         [PART_BOOT] = { /* in wl12xx we can use a mix of work and down
 510                          * partition here */
 511                 .mem = {
 512                         .start = 0x00040000,
 513                         .size  = 0x00014fc0
 514                 },
 515                 .reg = {
 516                         .start = REGISTERS_BASE,
 517                         .size  = 0x00008800
 518                 },
 519                 .mem2 = {
 520                         .start = 0x00000000,
 521                         .size  = 0x00000000
 522                 },
 523                 .mem3 = {
 524                         .start = 0x00000000,
 525                         .size  = 0x00000000
 526                 },
 527         },
 528
 529         [PART_WORK] = {
 530                 .mem = {
 531                         .start = 0x00040000,
 532                         .size  = 0x00014fc0
 533                 },
 534                 .reg = {
 535                         .start = REGISTERS_BASE,
 536                         .size  = 0x0000a000
 537                 },
 538                 .mem2 = {
 539                         .start = 0x003004f8,
 540                         .size  = 0x00000004
 541                 },
 542                 .mem3 = {
 543                         .start = 0x00000000,
 544                         .size  = 0x00040404
 545                 },
 546         },
 547
 548         [PART_DRPW] = {
 549                 .mem = {
 550                         .start = 0x00040000,
 551                         .size  = 0x00014fc0
 552                 },
 553                 .reg = {
 554                         .start = DRPW_BASE,
 555                         .size  = 0x00006000
 556                 },
 557                 .mem2 = {
 558                         .start = 0x00000000,
 559                         .size  = 0x00000000
 560                 },
 561                 .mem3 = {
 562                         .start = 0x00000000,
 563                         .size  = 0x00000000
 564                 }
 565         }
 566 };
 567
 568 static const int wl12xx_rtable[REG_TABLE_LEN] = {
 569         [REG_ECPU_CONTROL]              = WL12XX_REG_ECPU_CONTROL,
 570         [REG_INTERRUPT_NO_CLEAR]        = WL12XX_REG_INTERRUPT_NO_CLEAR,
 571         [REG_INTERRUPT_ACK]             = WL12XX_REG_INTERRUPT_ACK,
 572         [REG_COMMAND_MAILBOX_PTR]       = WL12XX_REG_COMMAND_MAILBOX_PTR,
 573         [REG_EVENT_MAILBOX_PTR]         = WL12XX_REG_EVENT_MAILBOX_PTR,
 574         [REG_INTERRUPT_TRIG]            = WL12XX_REG_INTERRUPT_TRIG,
 575         [REG_INTERRUPT_MASK]            = WL12XX_REG_INTERRUPT_MASK,
 576         [REG_PC_ON_RECOVERY]            = WL12XX_SCR_PAD4,
 577         [REG_CHIP_ID_B]                 = WL12XX_CHIP_ID_B,
 578         [REG_CMD_MBOX_ADDRESS]          = WL12XX_CMD_MBOX_ADDRESS,
 579
 580         /* data access memory addresses, used with partition translation */
 581         [REG_SLV_MEM_DATA]              = WL1271_SLV_MEM_DATA,
 582         [REG_SLV_REG_DATA]              = WL1271_SLV_REG_DATA,
 583
 584         /* raw data access memory addresses */
 585         [REG_RAW_FW_STATUS_ADDR]        = FW_STATUS_ADDR,
 586 };
 587
 588 /* TODO: maybe move to a new header file? */
 589 #define WL127X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 590 #define WL127X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 591 #define WL127X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 592
 593 #define WL128X_FW_NAME_MULTI    "/*(DEBLOBBED)*/"
 594 #define WL128X_FW_NAME_SINGLE   "/*(DEBLOBBED)*/"
 595 #define WL128X_PLT_FW_NAME      "/*(DEBLOBBED)*/"
 596
 597 static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len)
 598 {
 599         int ret;
 600
 601         if (wl->chip.id != CHIP_ID_128X_PG20) {
 602                 struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
 603                 struct wl12xx_priv *priv = wl->priv;
 604
 605                 /*
 606                  * Choose the block we want to read
 607                  * For aggregated packets, only the first memory block
 608                  * should be retrieved. The FW takes care of the rest.
 609                  */
 610                 u32 mem_block = rx_desc & RX_MEM_BLOCK_MASK;
 611
 612                 priv->rx_mem_addr->addr = (mem_block << 8) +
 613                         le32_to_cpu(wl_mem_map->packet_memory_pool_start);
 614
 615                 priv->rx_mem_addr->addr_extra = priv->rx_mem_addr->addr + 4;
 616
 617                 ret = wlcore_write(wl, WL1271_SLV_REG_DATA, priv->rx_mem_addr,
 618                                    sizeof(*priv->rx_mem_addr), false);
 619                 if (ret < 0)
 620                         return ret;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int wl12xx_identify_chip(struct wl1271 *wl)
 627 {
 628         int ret = 0;
 629
 630         switch (wl->chip.id) {
 631         case CHIP_ID_127X_PG10:
 632                 wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
 633                                wl->chip.id);
 634
 635                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 636                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 637                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 638                               WLCORE_QUIRK_START_STA_FAILS |
 639                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 640                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 641                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 642                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 643                        sizeof(wl->conf.mem));
 644
 645                 /* read data preparation is only needed by wl127x */
 646                 wl->ops->prepare_read = wl127x_prepare_read;
 647
 648                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 649                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 650                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 651                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 652                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 653                 break;
 654
 655         case CHIP_ID_127X_PG20:
 656                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
 657                              wl->chip.id);
 658
 659                 wl->quirks |= WLCORE_QUIRK_LEGACY_NVS |
 660                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 661                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 662                               WLCORE_QUIRK_START_STA_FAILS |
 663                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 664                 wl->plt_fw_name = WL127X_PLT_FW_NAME;
 665                 wl->sr_fw_name = WL127X_FW_NAME_SINGLE;
 666                 wl->mr_fw_name = WL127X_FW_NAME_MULTI;
 667                 memcpy(&wl->conf.mem, &wl12xx_default_priv_conf.mem_wl127x,
 668                        sizeof(wl->conf.mem));
 669
 670                 /* read data preparation is only needed by wl127x */
 671                 wl->ops->prepare_read = wl127x_prepare_read;
 672
 673                 wlcore_set_min_fw_ver(wl, WL127X_CHIP_VER,
 674                               WL127X_IFTYPE_SR_VER,  WL127X_MAJOR_SR_VER,
 675                               WL127X_SUBTYPE_SR_VER, WL127X_MINOR_SR_VER,
 676                               WL127X_IFTYPE_MR_VER,  WL127X_MAJOR_MR_VER,
 677                               WL127X_SUBTYPE_MR_VER, WL127X_MINOR_MR_VER);
 678                 break;
 679
 680         case CHIP_ID_128X_PG20:
 681                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1283 PG20)",
 682                              wl->chip.id);
 683                 wl->plt_fw_name = WL128X_PLT_FW_NAME;
 684                 wl->sr_fw_name = WL128X_FW_NAME_SINGLE;
 685                 wl->mr_fw_name = WL128X_FW_NAME_MULTI;
 686
 687                 /* wl128x requires TX blocksize alignment */
 688                 wl->quirks |= WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
 689                               WLCORE_QUIRK_DUAL_PROBE_TMPL |
 690                               WLCORE_QUIRK_TKIP_HEADER_SPACE |
 691                               WLCORE_QUIRK_START_STA_FAILS |
 692                               WLCORE_QUIRK_AP_ZERO_SESSION_ID;
 693
 694                 wlcore_set_min_fw_ver(wl, WL128X_CHIP_VER,
 695                               WL128X_IFTYPE_SR_VER,  WL128X_MAJOR_SR_VER,
 696                               WL128X_SUBTYPE_SR_VER, WL128X_MINOR_SR_VER,
 697                               WL128X_IFTYPE_MR_VER,  WL128X_MAJOR_MR_VER,
 698                               WL128X_SUBTYPE_MR_VER, WL128X_MINOR_MR_VER);
 699                 break;
 700         case CHIP_ID_128X_PG10:
 701         default:
 702                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 703                 ret = -ENODEV;
 704                 goto out;
 705         }
 706
 707         wl->fw_mem_block_size = 256;
 708         wl->fwlog_end = 0x2000000;
 709
 710         /* common settings */
 711         wl->scan_templ_id_2_4 = CMD_TEMPL_APP_PROBE_REQ_2_4_LEGACY;
 712         wl->scan_templ_id_5 = CMD_TEMPL_APP_PROBE_REQ_5_LEGACY;
 713         wl->sched_scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
 714         wl->sched_scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
 715         wl->max_channels_5 = WL12XX_MAX_CHANNELS_5GHZ;
 716         wl->ba_rx_session_count_max = WL12XX_RX_BA_MAX_SESSIONS;
 717 out:
 718         return ret;
 719 }
 720
 721 static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr,
 722                                              u16 val)
 723 {
 724         int ret;
 725
 726         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 727         addr = (addr >> 1) + 0x30000;
 728         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 729         if (ret < 0)
 730                 goto out;
 731
 732         /* write value to OCP_POR_WDATA */
 733         ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val);
 734         if (ret < 0)
 735                 goto out;
 736
 737         /* write 1 to OCP_CMD */
 738         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE);
 739         if (ret < 0)
 740                 goto out;
 741
 742 out:
 743         return ret;
 744 }
 745
 746 static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr,
 747                                             u16 *out)
 748 {
 749         u32 val;
 750         int timeout = OCP_CMD_LOOP;
 751         int ret;
 752
 753         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 754         addr = (addr >> 1) + 0x30000;
 755         ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr);
 756         if (ret < 0)
 757                 return ret;
 758
 759         /* write 2 to OCP_CMD */
 760         ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ);
 761         if (ret < 0)
 762                 return ret;
 763
 764         /* poll for data ready */
 765         do {
 766                 ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val);
 767                 if (ret < 0)
 768                         return ret;
 769         } while (!(val & OCP_READY_MASK) && --timeout);
 770
 771         if (!timeout) {
 772                 wl1271_warning("Top register access timed out.");
 773                 return -ETIMEDOUT;
 774         }
 775
 776         /* check data status and return if OK */
 777         if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) {
 778                 wl1271_warning("Top register access returned error.");
 779                 return -EIO;
 780         }
 781
 782         if (out)
 783                 *out = val & 0xffff;
 784
 785         return 0;
 786 }
 787
 788 static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl)
 789 {
 790         u16 spare_reg;
 791         int ret;
 792
 793         /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
 794         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 795         if (ret < 0)
 796                 return ret;
 797
 798         if (spare_reg == 0xFFFF)
 799                 return -EFAULT;
 800         spare_reg |= (BIT(3) | BIT(5) | BIT(6));
 801         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 802         if (ret < 0)
 803                 return ret;
 804
 805         /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
 806         ret = wl12xx_top_reg_write(wl, SYS_CLK_CFG_REG,
 807                                    WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
 808         if (ret < 0)
 809                 return ret;
 810
 811         /* Delay execution for 15msec, to let the HW settle */
 812         mdelay(15);
 813
 814         return 0;
 815 }
 816
 817 static bool wl128x_is_tcxo_valid(struct wl1271 *wl)
 818 {
 819         u16 tcxo_detection;
 820         int ret;
 821
 822         ret = wl12xx_top_reg_read(wl, TCXO_CLK_DETECT_REG, &tcxo_detection);
 823         if (ret < 0)
 824                 return false;
 825
 826         if (tcxo_detection & TCXO_DET_FAILED)
 827                 return false;
 828
 829         return true;
 830 }
 831
 832 static bool wl128x_is_fref_valid(struct wl1271 *wl)
 833 {
 834         u16 fref_detection;
 835         int ret;
 836
 837         ret = wl12xx_top_reg_read(wl, FREF_CLK_DETECT_REG, &fref_detection);
 838         if (ret < 0)
 839                 return false;
 840
 841         if (fref_detection & FREF_CLK_DETECT_FAIL)
 842                 return false;
 843
 844         return true;
 845 }
 846
 847 static int wl128x_manually_configure_mcs_pll(struct wl1271 *wl)
 848 {
 849         int ret;
 850
 851         ret = wl12xx_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
 852         if (ret < 0)
 853                 goto out;
 854
 855         ret = wl12xx_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
 856         if (ret < 0)
 857                 goto out;
 858
 859         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG,
 860                                    MCS_PLL_CONFIG_REG_VAL);
 861
 862 out:
 863         return ret;
 864 }
 865
 866 static int wl128x_configure_mcs_pll(struct wl1271 *wl, int clk)
 867 {
 868         u16 spare_reg;
 869         u16 pll_config;
 870         u8 input_freq;
 871         struct wl12xx_priv *priv = wl->priv;
 872         int ret;
 873
 874         /* Mask bits [3:1] in the sys_clk_cfg register */
 875         ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg);
 876         if (ret < 0)
 877                 return ret;
 878
 879         if (spare_reg == 0xFFFF)
 880                 return -EFAULT;
 881         spare_reg |= BIT(2);
 882         ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg);
 883         if (ret < 0)
 884                 return ret;
 885
 886         /* Handle special cases of the TCXO clock */
 887         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_8 ||
 888             priv->tcxo_clock == WL12XX_TCXOCLOCK_33_6)
 889                 return wl128x_manually_configure_mcs_pll(wl);
 890
 891         /* Set the input frequency according to the selected clock source */
 892         input_freq = (clk & 1) + 1;
 893
 894         ret = wl12xx_top_reg_read(wl, MCS_PLL_CONFIG_REG, &pll_config);
 895         if (ret < 0)
 896                 return ret;
 897
 898         if (pll_config == 0xFFFF)
 899                 return -EFAULT;
 900         pll_config |= (input_freq << MCS_SEL_IN_FREQ_SHIFT);
 901         pll_config |= MCS_PLL_ENABLE_HP;
 902         ret = wl12xx_top_reg_write(wl, MCS_PLL_CONFIG_REG, pll_config);
 903
 904         return ret;
 905 }
 906
 907 /*
 908  * WL128x has two clocks input - TCXO and FREF.
 909  * TCXO is the main clock of the device, while FREF is used to sync
 910  * between the GPS and the cellular modem.
 911  * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
 912  * as the WLAN/BT main clock.
 913  */
 914 static int wl128x_boot_clk(struct wl1271 *wl, int *selected_clock)
 915 {
 916         struct wl12xx_priv *priv = wl->priv;
 917         u16 sys_clk_cfg;
 918         int ret;
 919
 920         /* For XTAL-only modes, FREF will be used after switching from TCXO */
 921         if (priv->ref_clock == WL12XX_REFCLOCK_26_XTAL ||
 922             priv->ref_clock == WL12XX_REFCLOCK_38_XTAL) {
 923                 if (!wl128x_switch_tcxo_to_fref(wl))
 924                         return -EINVAL;
 925                 goto fref_clk;
 926         }
 927
 928         /* Query the HW, to determine which clock source we should use */
 929         ret = wl12xx_top_reg_read(wl, SYS_CLK_CFG_REG, &sys_clk_cfg);
 930         if (ret < 0)
 931                 return ret;
 932
 933         if (sys_clk_cfg == 0xFFFF)
 934                 return -EINVAL;
 935         if (sys_clk_cfg & PRCM_CM_EN_MUX_WLAN_FREF)
 936                 goto fref_clk;
 937
 938         /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
 939         if (priv->tcxo_clock == WL12XX_TCXOCLOCK_16_368 ||
 940             priv->tcxo_clock == WL12XX_TCXOCLOCK_32_736) {
 941                 if (!wl128x_switch_tcxo_to_fref(wl))
 942                         return -EINVAL;
 943                 goto fref_clk;
 944         }
 945
 946         /* TCXO clock is selected */
 947         if (!wl128x_is_tcxo_valid(wl))
 948                 return -EINVAL;
 949         *selected_clock = priv->tcxo_clock;
 950         goto config_mcs_pll;
 951
 952 fref_clk:
 953         /* FREF clock is selected */
 954         if (!wl128x_is_fref_valid(wl))
 955                 return -EINVAL;
 956         *selected_clock = priv->ref_clock;
 957
 958 config_mcs_pll:
 959         return wl128x_configure_mcs_pll(wl, *selected_clock);
 960 }
 961
 962 static int wl127x_boot_clk(struct wl1271 *wl)
 963 {
 964         struct wl12xx_priv *priv = wl->priv;
 965         u32 pause;
 966         u32 clk;
 967         int ret;
 968
 969         if (WL127X_PG_GET_MAJOR(wl->hw_pg_ver) < 3)
 970                 wl->quirks |= WLCORE_QUIRK_END_OF_TRANSACTION;
 971
 972         if (priv->ref_clock == CONF_REF_CLK_19_2_E ||
 973             priv->ref_clock == CONF_REF_CLK_38_4_E ||
 974             priv->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
 975                 /* ref clk: 19.2/38.4/38.4-XTAL */
 976                 clk = 0x3;
 977         else if (priv->ref_clock == CONF_REF_CLK_26_E ||
 978                  priv->ref_clock == CONF_REF_CLK_26_M_XTAL ||
 979                  priv->ref_clock == CONF_REF_CLK_52_E)
 980                 /* ref clk: 26/52 */
 981                 clk = 0x5;
 982         else
 983                 return -EINVAL;
 984
 985         if (priv->ref_clock != CONF_REF_CLK_19_2_E) {
 986                 u16 val;
 987                 /* Set clock type (open drain) */
 988                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_TYPE, &val);
 989                 if (ret < 0)
 990                         goto out;
 991
 992                 val &= FREF_CLK_TYPE_BITS;
 993                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 994                 if (ret < 0)
 995                         goto out;
 996
 997                 /* Set clock pull mode (no pull) */
 998                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_PULL, &val);
 999                 if (ret < 0)
1000                         goto out;
1001
1002                 val |= NO_PULL;
1003                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_PULL, val);
1004                 if (ret < 0)
1005                         goto out;
1006         } else {
1007                 u16 val;
1008                 /* Set clock polarity */
1009                 ret = wl12xx_top_reg_read(wl, OCP_REG_CLK_POLARITY, &val);
1010                 if (ret < 0)
1011                         goto out;
1012
1013                 val &= FREF_CLK_POLARITY_BITS;
1014                 val |= CLK_REQ_OUTN_SEL;
1015                 ret = wl12xx_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
1016                 if (ret < 0)
1017                         goto out;
1018         }
1019
1020         ret = wlcore_write32(wl, WL12XX_PLL_PARAMETERS, clk);
1021         if (ret < 0)
1022                 goto out;
1023
1024         ret = wlcore_read32(wl, WL12XX_PLL_PARAMETERS, &pause);
1025         if (ret < 0)
1026                 goto out;
1027
1028         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
1029
1030         pause &= ~(WU_COUNTER_PAUSE_VAL);
1031         pause |= WU_COUNTER_PAUSE_VAL;
1032         ret = wlcore_write32(wl, WL12XX_WU_COUNTER_PAUSE, pause);
1033
1034 out:
1035         return ret;
1036 }
1037
1038 static int wl1271_boot_soft_reset(struct wl1271 *wl)
1039 {
1040         unsigned long timeout;
1041         u32 boot_data;
1042         int ret = 0;
1043
1044         /* perform soft reset */
1045         ret = wlcore_write32(wl, WL12XX_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
1046         if (ret < 0)
1047                 goto out;
1048
1049         /* SOFT_RESET is self clearing */
1050         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
1051         while (1) {
1052                 ret = wlcore_read32(wl, WL12XX_SLV_SOFT_RESET, &boot_data);
1053                 if (ret < 0)
1054                         goto out;
1055
1056                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
1057                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
1058                         break;
1059
1060                 if (time_after(jiffies, timeout)) {
1061                         /* 1.2 check pWhalBus->uSelfClearTime if the
1062                          * timeout was reached */
1063                         wl1271_error("soft reset timeout");
1064                         return -1;
1065                 }
1066
1067                 udelay(SOFT_RESET_STALL_TIME);
1068         }
1069
1070         /* disable Rx/Tx */
1071         ret = wlcore_write32(wl, WL12XX_ENABLE, 0x0);
1072         if (ret < 0)
1073                 goto out;
1074
1075         /* disable auto calibration on start*/
1076         ret = wlcore_write32(wl, WL12XX_SPARE_A2, 0xffff);
1077
1078 out:
1079         return ret;
1080 }
1081
1082 static int wl12xx_pre_boot(struct wl1271 *wl)
1083 {
1084         struct wl12xx_priv *priv = wl->priv;
1085         int ret = 0;
1086         u32 clk;
1087         int selected_clock = -1;
1088
1089         if (wl->chip.id == CHIP_ID_128X_PG20) {
1090                 ret = wl128x_boot_clk(wl, &selected_clock);
1091                 if (ret < 0)
1092                         goto out;
1093         } else {
1094                 ret = wl127x_boot_clk(wl);
1095                 if (ret < 0)
1096                         goto out;
1097         }
1098
1099         /* Continue the ELP wake up sequence */
1100         ret = wlcore_write32(wl, WL12XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
1101         if (ret < 0)
1102                 goto out;
1103
1104         udelay(500);
1105
1106         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1107         if (ret < 0)
1108                 goto out;
1109
1110         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
1111            to be used by DRPw FW. The RTRIM value will be added by the FW
1112            before taking DRPw out of reset */
1113
1114         ret = wlcore_read32(wl, WL12XX_DRPW_SCRATCH_START, &clk);
1115         if (ret < 0)
1116                 goto out;
1117
1118         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
1119
1120         if (wl->chip.id == CHIP_ID_128X_PG20)
1121                 clk |= ((selected_clock & 0x3) << 1) << 4;
1122         else
1123                 clk |= (priv->ref_clock << 1) << 4;
1124
1125         ret = wlcore_write32(wl, WL12XX_DRPW_SCRATCH_START, clk);
1126         if (ret < 0)
1127                 goto out;
1128
1129         ret = wlcore_set_partition(wl, &wl->ptable[PART_WORK]);
1130         if (ret < 0)
1131                 goto out;
1132
1133         /* Disable interrupts */
1134         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
1135         if (ret < 0)
1136                 goto out;
1137
1138         ret = wl1271_boot_soft_reset(wl);
1139         if (ret < 0)
1140                 goto out;
1141
1142 out:
1143         return ret;
1144 }
1145
1146 static int wl12xx_pre_upload(struct wl1271 *wl)
1147 {
1148         u32 tmp;
1149         u16 polarity;
1150         int ret;
1151
1152         /* write firmware's last address (ie. it's length) to
1153          * ACX_EEPROMLESS_IND_REG */
1154         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
1155
1156         ret = wlcore_write32(wl, WL12XX_EEPROMLESS_IND, WL12XX_EEPROMLESS_IND);
1157         if (ret < 0)
1158                 goto out;
1159
1160         ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
1161         if (ret < 0)
1162                 goto out;
1163
1164         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
1165
1166         /* 6. read the EEPROM parameters */
1167         ret = wlcore_read32(wl, WL12XX_SCR_PAD2, &tmp);
1168         if (ret < 0)
1169                 goto out;
1170
1171         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
1172          * to upload_fw) */
1173
1174         if (wl->chip.id == CHIP_ID_128X_PG20) {
1175                 ret = wl12xx_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
1176                 if (ret < 0)
1177                         goto out;
1178         }
1179
1180         /* polarity must be set before the firmware is loaded */
1181         ret = wl12xx_top_reg_read(wl, OCP_REG_POLARITY, &polarity);
1182         if (ret < 0)
1183                 goto out;
1184
1185         /* We use HIGH polarity, so unset the LOW bit */
1186         polarity &= ~POLARITY_LOW;
1187         ret = wl12xx_top_reg_write(wl, OCP_REG_POLARITY, polarity);
1188
1189 out:
1190         return ret;
1191 }
1192
1193 static int wl12xx_enable_interrupts(struct wl1271 *wl)
1194 {
1195         int ret;
1196
1197         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1198                                WL12XX_ACX_ALL_EVENTS_VECTOR);
1199         if (ret < 0)
1200                 goto out;
1201
1202         wlcore_enable_interrupts(wl);
1203         ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
1204                                WL1271_ACX_INTR_ALL & ~(WL12XX_INTR_MASK));
1205         if (ret < 0)
1206                 goto disable_interrupts;
1207
1208         ret = wlcore_write32(wl, WL12XX_HI_CFG, HI_CFG_DEF_VAL);
1209         if (ret < 0)
1210                 goto disable_interrupts;
1211
1212         return ret;
1213
1214 disable_interrupts:
1215         wlcore_disable_interrupts(wl);
1216
1217 out:
1218         return ret;
1219 }
1220
1221 static int wl12xx_boot(struct wl1271 *wl)
1222 {
1223         int ret;
1224
1225         ret = wl12xx_pre_boot(wl);
1226         if (ret < 0)
1227                 goto out;
1228
1229         ret = wlcore_boot_upload_nvs(wl);
1230         if (ret < 0)
1231                 goto out;
1232
1233         ret = wl12xx_pre_upload(wl);
1234         if (ret < 0)
1235                 goto out;
1236
1237         ret = wlcore_boot_upload_firmware(wl);
1238         if (ret < 0)
1239                 goto out;
1240
1241         wl->event_mask = BSS_LOSE_EVENT_ID |
1242                 REGAINED_BSS_EVENT_ID |
1243                 SCAN_COMPLETE_EVENT_ID |
1244                 ROLE_STOP_COMPLETE_EVENT_ID |
1245                 RSSI_SNR_TRIGGER_0_EVENT_ID |
1246                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
1247                 SOFT_GEMINI_SENSE_EVENT_ID |
1248                 PERIODIC_SCAN_REPORT_EVENT_ID |
1249                 PERIODIC_SCAN_COMPLETE_EVENT_ID |
1250                 DUMMY_PACKET_EVENT_ID |
1251                 PEER_REMOVE_COMPLETE_EVENT_ID |
1252                 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
1253                 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
1254                 INACTIVE_STA_EVENT_ID |
1255                 CHANNEL_SWITCH_COMPLETE_EVENT_ID;
1256
1257         wl->ap_event_mask = MAX_TX_RETRY_EVENT_ID;
1258
1259         ret = wlcore_boot_run_firmware(wl);
1260         if (ret < 0)
1261                 goto out;
1262
1263         ret = wl12xx_enable_interrupts(wl);
1264
1265 out:
1266         return ret;
1267 }
1268
1269 static int wl12xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
1270                                void *buf, size_t len)
1271 {
1272         int ret;
1273
1274         ret = wlcore_write(wl, cmd_box_addr, buf, len, false);
1275         if (ret < 0)
1276                 return ret;
1277
1278         ret = wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL12XX_INTR_TRIG_CMD);
1279
1280         return ret;
1281 }
1282
1283 static int wl12xx_ack_event(struct wl1271 *wl)
1284 {
1285         return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
1286                                 WL12XX_INTR_TRIG_EVENT_ACK);
1287 }
1288
1289 static u32 wl12xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
1290 {
1291         u32 blk_size = WL12XX_TX_HW_BLOCK_SIZE;
1292         u32 align_len = wlcore_calc_packet_alignment(wl, len);
1293
1294         return (align_len + blk_size - 1) / blk_size + spare_blks;
1295 }
1296
1297 static void
1298 wl12xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1299                           u32 blks, u32 spare_blks)
1300 {
1301         if (wl->chip.id == CHIP_ID_128X_PG20) {
1302                 desc->wl128x_mem.total_mem_blocks = blks;
1303         } else {
1304                 desc->wl127x_mem.extra_blocks = spare_blks;
1305                 desc->wl127x_mem.total_mem_blocks = blks;
1306         }
1307 }
1308
1309 static void
1310 wl12xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
1311                             struct sk_buff *skb)
1312 {
1313         u32 aligned_len = wlcore_calc_packet_alignment(wl, skb->len);
1314
1315         if (wl->chip.id == CHIP_ID_128X_PG20) {
1316                 desc->wl128x_mem.extra_bytes = aligned_len - skb->len;
1317                 desc->length = cpu_to_le16(aligned_len >> 2);
1318
1319                 wl1271_debug(DEBUG_TX,
1320                              "tx_fill_hdr: hlid: %d len: %d life: %d mem: %d extra: %d",
1321                              desc->hlid,
1322                              le16_to_cpu(desc->length),
1323                              le16_to_cpu(desc->life_time),
1324                              desc->wl128x_mem.total_mem_blocks,
1325                              desc->wl128x_mem.extra_bytes);
1326         } else {
1327                 /* calculate number of padding bytes */
1328                 int pad = aligned_len - skb->len;
1329                 desc->tx_attr |=
1330                         cpu_to_le16(pad << TX_HW_ATTR_OFST_LAST_WORD_PAD);
1331
1332                 /* Store the aligned length in terms of words */
1333                 desc->length = cpu_to_le16(aligned_len >> 2);
1334
1335                 wl1271_debug(DEBUG_TX,
1336                              "tx_fill_hdr: pad: %d hlid: %d len: %d life: %d mem: %d",
1337                              pad, desc->hlid,
1338                              le16_to_cpu(desc->length),
1339                              le16_to_cpu(desc->life_time),
1340                              desc->wl127x_mem.total_mem_blocks);
1341         }
1342 }
1343
1344 static enum wl_rx_buf_align
1345 wl12xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1346 {
1347         if (rx_desc & RX_BUF_UNALIGNED_PAYLOAD)
1348                 return WLCORE_RX_BUF_UNALIGNED;
1349
1350         return WLCORE_RX_BUF_ALIGNED;
1351 }
1352
1353 static u32 wl12xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1354                                     u32 data_len)
1355 {
1356         struct wl1271_rx_descriptor *desc = rx_data;
1357
1358         /* invalid packet */
1359         if (data_len < sizeof(*desc) ||
1360             data_len < sizeof(*desc) + desc->pad_len)
1361                 return 0;
1362
1363         return data_len - sizeof(*desc) - desc->pad_len;
1364 }
1365
1366 static int wl12xx_tx_delayed_compl(struct wl1271 *wl)
1367 {
1368         if (wl->fw_status->tx_results_counter ==
1369             (wl->tx_results_count & 0xff))
1370                 return 0;
1371
1372         return wlcore_tx_complete(wl);
1373 }
1374
1375 static int wl12xx_hw_init(struct wl1271 *wl)
1376 {
1377         int ret;
1378
1379         if (wl->chip.id == CHIP_ID_128X_PG20) {
1380                 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE;
1381
1382                 ret = wl128x_cmd_general_parms(wl);
1383                 if (ret < 0)
1384                         goto out;
1385
1386                 /*
1387                  * If we are in calibrator based auto detect then we got the FEM nr
1388                  * in wl->fem_manuf. No need to continue further
1389                  */
1390                 if (wl->plt_mode == PLT_FEM_DETECT)
1391                         goto out;
1392
1393                 ret = wl128x_cmd_radio_parms(wl);
1394                 if (ret < 0)
1395                         goto out;
1396
1397                 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN)
1398                         /* Enable SDIO padding */
1399                         host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1400
1401                 /* Must be before wl1271_acx_init_mem_config() */
1402                 ret = wl1271_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap);
1403                 if (ret < 0)
1404                         goto out;
1405         } else {
1406                 ret = wl1271_cmd_general_parms(wl);
1407                 if (ret < 0)
1408                         goto out;
1409
1410                 /*
1411                  * If we are in calibrator based auto detect then we got the FEM nr
1412                  * in wl->fem_manuf. No need to continue further
1413                  */
1414                 if (wl->plt_mode == PLT_FEM_DETECT)
1415                         goto out;
1416
1417                 ret = wl1271_cmd_radio_parms(wl);
1418                 if (ret < 0)
1419                         goto out;
1420                 ret = wl1271_cmd_ext_radio_parms(wl);
1421                 if (ret < 0)
1422                         goto out;
1423         }
1424 out:
1425         return ret;
1426 }
1427
1428 static void wl12xx_convert_fw_status(struct wl1271 *wl, void *raw_fw_status,
1429                                      struct wl_fw_status *fw_status)
1430 {
1431         struct wl12xx_fw_status *int_fw_status = raw_fw_status;
1432
1433         fw_status->intr = le32_to_cpu(int_fw_status->intr);
1434         fw_status->fw_rx_counter = int_fw_status->fw_rx_counter;
1435         fw_status->drv_rx_counter = int_fw_status->drv_rx_counter;
1436         fw_status->tx_results_counter = int_fw_status->tx_results_counter;
1437         fw_status->rx_pkt_descs = int_fw_status->rx_pkt_descs;
1438
1439         fw_status->fw_localtime = le32_to_cpu(int_fw_status->fw_localtime);
1440         fw_status->link_ps_bitmap = le32_to_cpu(int_fw_status->link_ps_bitmap);
1441         fw_status->link_fast_bitmap =
1442                         le32_to_cpu(int_fw_status->link_fast_bitmap);
1443         fw_status->total_released_blks =
1444                         le32_to_cpu(int_fw_status->total_released_blks);
1445         fw_status->tx_total = le32_to_cpu(int_fw_status->tx_total);
1446
1447         fw_status->counters.tx_released_pkts =
1448                         int_fw_status->counters.tx_released_pkts;
1449         fw_status->counters.tx_lnk_free_pkts =
1450                         int_fw_status->counters.tx_lnk_free_pkts;
1451         fw_status->counters.tx_voice_released_blks =
1452                         int_fw_status->counters.tx_voice_released_blks;
1453         fw_status->counters.tx_last_rate =
1454                         int_fw_status->counters.tx_last_rate;
1455
1456         fw_status->log_start_addr = le32_to_cpu(int_fw_status->log_start_addr);
1457 }
1458
1459 static u32 wl12xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1460                                        struct wl12xx_vif *wlvif)
1461 {
1462         return wlvif->rate_set;
1463 }
1464
1465 static void wl12xx_conf_init(struct wl1271 *wl)
1466 {
1467         struct wl12xx_priv *priv = wl->priv;
1468
1469         /* apply driver default configuration */
1470         memcpy(&wl->conf, &wl12xx_conf, sizeof(wl12xx_conf));
1471
1472         /* apply default private configuration */
1473         memcpy(&priv->conf, &wl12xx_default_priv_conf, sizeof(priv->conf));
1474 }
1475
1476 static bool wl12xx_mac_in_fuse(struct wl1271 *wl)
1477 {
1478         bool supported = false;
1479         u8 major, minor;
1480
1481         if (wl->chip.id == CHIP_ID_128X_PG20) {
1482                 major = WL128X_PG_GET_MAJOR(wl->hw_pg_ver);
1483                 minor = WL128X_PG_GET_MINOR(wl->hw_pg_ver);
1484
1485                 /* in wl128x we have the MAC address if the PG is >= (2, 1) */
1486                 if (major > 2 || (major == 2 && minor >= 1))
1487                         supported = true;
1488         } else {
1489                 major = WL127X_PG_GET_MAJOR(wl->hw_pg_ver);
1490                 minor = WL127X_PG_GET_MINOR(wl->hw_pg_ver);
1491
1492                 /* in wl127x we have the MAC address if the PG is >= (3, 1) */
1493                 if (major == 3 && minor >= 1)
1494                         supported = true;
1495         }
1496
1497         wl1271_debug(DEBUG_PROBE,
1498                      "PG Ver major = %d minor = %d, MAC %s present",
1499                      major, minor, supported ? "is" : "is not");
1500
1501         return supported;
1502 }
1503
1504 static int wl12xx_get_fuse_mac(struct wl1271 *wl)
1505 {
1506         u32 mac1, mac2;
1507         int ret;
1508
1509         ret = wlcore_set_partition(wl, &wl->ptable[PART_DRPW]);
1510         if (ret < 0)
1511                 goto out;
1512
1513         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_1, &mac1);
1514         if (ret < 0)
1515                 goto out;
1516
1517         ret = wlcore_read32(wl, WL12XX_REG_FUSE_BD_ADDR_2, &mac2);
1518         if (ret < 0)
1519                 goto out;
1520
1521         /* these are the two parts of the BD_ADDR */
1522         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1523                 ((mac1 & 0xff000000) >> 24);
1524         wl->fuse_nic_addr = mac1 & 0xffffff;
1525
1526         ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1527
1528 out:
1529         return ret;
1530 }
1531
1532 static int wl12xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1533 {
1534         u16 die_info;
1535         int ret;
1536
1537         if (wl->chip.id == CHIP_ID_128X_PG20)
1538                 ret = wl12xx_top_reg_read(wl, WL128X_REG_FUSE_DATA_2_1,
1539                                           &die_info);
1540         else
1541                 ret = wl12xx_top_reg_read(wl, WL127X_REG_FUSE_DATA_2_1,
1542                                           &die_info);
1543
1544         if (ret >= 0 && ver)
1545                 *ver = (s8)((die_info & PG_VER_MASK) >> PG_VER_OFFSET);
1546
1547         return ret;
1548 }
1549
1550 static int wl12xx_get_mac(struct wl1271 *wl)
1551 {
1552         if (wl12xx_mac_in_fuse(wl))
1553                 return wl12xx_get_fuse_mac(wl);
1554
1555         return 0;
1556 }
1557
1558 static void wl12xx_set_tx_desc_csum(struct wl1271 *wl,
1559                                     struct wl1271_tx_hw_descr *desc,
1560                                     struct sk_buff *skb)
1561 {
1562         desc->wl12xx_reserved = 0;
1563 }
1564
1565 static int wl12xx_plt_init(struct wl1271 *wl)
1566 {
1567         int ret;
1568
1569         ret = wl->ops->boot(wl);
1570         if (ret < 0)
1571                 goto out;
1572
1573         ret = wl->ops->hw_init(wl);
1574         if (ret < 0)
1575                 goto out_irq_disable;
1576
1577         /*
1578          * If we are in calibrator based auto detect then we got the FEM nr
1579          * in wl->fem_manuf. No need to continue further
1580          */
1581         if (wl->plt_mode == PLT_FEM_DETECT)
1582                 goto out;
1583
1584         ret = wl1271_acx_init_mem_config(wl);
1585         if (ret < 0)
1586                 goto out_irq_disable;
1587
1588         ret = wl12xx_acx_mem_cfg(wl);
1589         if (ret < 0)
1590                 goto out_free_memmap;
1591
1592         /* Enable data path */
1593         ret = wl1271_cmd_data_path(wl, 1);
1594         if (ret < 0)
1595                 goto out_free_memmap;
1596
1597         /* Configure for CAM power saving (ie. always active) */
1598         ret = wl1271_acx_sleep_auth(wl, WL1271_PSM_CAM);
1599         if (ret < 0)
1600                 goto out_free_memmap;
1601
1602         /* configure PM */
1603         ret = wl1271_acx_pm_config(wl);
1604         if (ret < 0)
1605                 goto out_free_memmap;
1606
1607         goto out;
1608
1609 out_free_memmap:
1610         kfree(wl->target_mem_map);
1611         wl->target_mem_map = NULL;
1612
1613 out_irq_disable:
1614         mutex_unlock(&wl->mutex);
1615         /* Unlocking the mutex in the middle of handling is
1616            inherently unsafe. In this case we deem it safe to do,
1617            because we need to let any possibly pending IRQ out of
1618            the system (and while we are WL1271_STATE_OFF the IRQ
1619            work function will not do anything.) Also, any other
1620            possible concurrent operations will fail due to the
1621            current state, hence the wl1271 struct should be safe. */
1622         wlcore_disable_interrupts(wl);
1623         mutex_lock(&wl->mutex);
1624 out:
1625         return ret;
1626 }
1627
1628 static int wl12xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1629 {
1630         if (is_gem)
1631                 return WL12XX_TX_HW_BLOCK_GEM_SPARE;
1632
1633         return WL12XX_TX_HW_BLOCK_SPARE_DEFAULT;
1634 }
1635
1636 static int wl12xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1637                           struct ieee80211_vif *vif,
1638                           struct ieee80211_sta *sta,
1639                           struct ieee80211_key_conf *key_conf)
1640 {
1641         return wlcore_set_key(wl, cmd, vif, sta, key_conf);
1642 }
1643
1644 static int wl12xx_set_peer_cap(struct wl1271 *wl,
1645                                struct ieee80211_sta_ht_cap *ht_cap,
1646                                bool allow_ht_operation,
1647                                u32 rate_set, u8 hlid)
1648 {
1649         return wl1271_acx_set_ht_capabilities(wl, ht_cap, allow_ht_operation,
1650                                               hlid);
1651 }
1652
1653 static bool wl12xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1654                                  struct wl1271_link *lnk)
1655 {
1656         u8 thold;
1657
1658         if (test_bit(hlid, &wl->fw_fast_lnk_map))
1659                 thold = wl->conf.tx.fast_link_thold;
1660         else
1661                 thold = wl->conf.tx.slow_link_thold;
1662
1663         return lnk->allocated_pkts < thold;
1664 }
1665
1666 static bool wl12xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1667                                 struct wl1271_link *lnk)
1668 {
1669         /* any link is good for low priority */
1670         return true;
1671 }
1672
1673 static u32 wl12xx_convert_hwaddr(struct wl1271 *wl, u32 hwaddr)
1674 {
1675         return hwaddr << 5;
1676 }
1677
1678 static int wl12xx_setup(struct wl1271 *wl);
1679
1680 static struct wlcore_ops wl12xx_ops = {
1681         .setup                  = wl12xx_setup,
1682         .identify_chip          = wl12xx_identify_chip,
1683         .boot                   = wl12xx_boot,
1684         .plt_init               = wl12xx_plt_init,
1685         .trigger_cmd            = wl12xx_trigger_cmd,
1686         .ack_event              = wl12xx_ack_event,
1687         .wait_for_event         = wl12xx_wait_for_event,
1688         .process_mailbox_events = wl12xx_process_mailbox_events,
1689         .calc_tx_blocks         = wl12xx_calc_tx_blocks,
1690         .set_tx_desc_blocks     = wl12xx_set_tx_desc_blocks,
1691         .set_tx_desc_data_len   = wl12xx_set_tx_desc_data_len,
1692         .get_rx_buf_align       = wl12xx_get_rx_buf_align,
1693         .get_rx_packet_len      = wl12xx_get_rx_packet_len,
1694         .tx_immediate_compl     = NULL,
1695         .tx_delayed_compl       = wl12xx_tx_delayed_compl,
1696         .hw_init                = wl12xx_hw_init,
1697         .init_vif               = NULL,
1698         .convert_fw_status      = wl12xx_convert_fw_status,
1699         .sta_get_ap_rate_mask   = wl12xx_sta_get_ap_rate_mask,
1700         .get_pg_ver             = wl12xx_get_pg_ver,
1701         .get_mac                = wl12xx_get_mac,
1702         .set_tx_desc_csum       = wl12xx_set_tx_desc_csum,
1703         .set_rx_csum            = NULL,
1704         .ap_get_mimo_wide_rate_mask = NULL,
1705         .debugfs_init           = wl12xx_debugfs_add_files,
1706         .scan_start             = wl12xx_scan_start,
1707         .scan_stop              = wl12xx_scan_stop,
1708         .sched_scan_start       = wl12xx_sched_scan_start,
1709         .sched_scan_stop        = wl12xx_scan_sched_scan_stop,
1710         .get_spare_blocks       = wl12xx_get_spare_blocks,
1711         .set_key                = wl12xx_set_key,
1712         .channel_switch         = wl12xx_cmd_channel_switch,
1713         .pre_pkt_send           = NULL,
1714         .set_peer_cap           = wl12xx_set_peer_cap,
1715         .convert_hwaddr         = wl12xx_convert_hwaddr,
1716         .lnk_high_prio          = wl12xx_lnk_high_prio,
1717         .lnk_low_prio           = wl12xx_lnk_low_prio,
1718         .interrupt_notify       = NULL,
1719         .rx_ba_filter           = NULL,
1720         .ap_sleep               = NULL,
1721 };
1722
1723 static struct ieee80211_sta_ht_cap wl12xx_ht_cap = {
1724         .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20 |
1725                (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT),
1726         .ht_supported = true,
1727         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K,
1728         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8,
1729         .mcs = {
1730                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1731                 .rx_highest = cpu_to_le16(72),
1732                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1733                 },
1734 };
1735
1736 static const struct ieee80211_iface_limit wl12xx_iface_limits[] = {
1737         {
1738                 .max = 3,
1739                 .types = BIT(NL80211_IFTYPE_STATION),
1740         },
1741         {
1742                 .max = 1,
1743                 .types = BIT(NL80211_IFTYPE_AP) |
1744                          BIT(NL80211_IFTYPE_P2P_GO) |
1745                          BIT(NL80211_IFTYPE_P2P_CLIENT),
1746         },
1747 };
1748
1749 static const struct ieee80211_iface_combination
1750 wl12xx_iface_combinations[] = {
1751         {
1752                 .max_interfaces = 3,
1753                 .limits = wl12xx_iface_limits,
1754                 .n_limits = ARRAY_SIZE(wl12xx_iface_limits),
1755                 .num_different_channels = 1,
1756         },
1757 };
1758
1759 static const struct wl12xx_clock wl12xx_refclock_table[] = {
1760         { 19200000,     false,  WL12XX_REFCLOCK_19      },
1761         { 26000000,     false,  WL12XX_REFCLOCK_26      },
1762         { 26000000,     true,   WL12XX_REFCLOCK_26_XTAL },
1763         { 38400000,     false,  WL12XX_REFCLOCK_38      },
1764         { 38400000,     true,   WL12XX_REFCLOCK_38_XTAL },
1765         { 52000000,     false,  WL12XX_REFCLOCK_52      },
1766         { 0,            false,  0 }
1767 };
1768
1769 static const struct wl12xx_clock wl12xx_tcxoclock_table[] = {
1770         { 16368000,     true,   WL12XX_TCXOCLOCK_16_368 },
1771         { 16800000,     true,   WL12XX_TCXOCLOCK_16_8   },
1772         { 19200000,     true,   WL12XX_TCXOCLOCK_19_2   },
1773         { 26000000,     true,   WL12XX_TCXOCLOCK_26     },
1774         { 32736000,     true,   WL12XX_TCXOCLOCK_32_736 },
1775         { 33600000,     true,   WL12XX_TCXOCLOCK_33_6   },
1776         { 38400000,     true,   WL12XX_TCXOCLOCK_38_4   },
1777         { 52000000,     true,   WL12XX_TCXOCLOCK_52     },
1778         { 0,            false,  0 }
1779 };
1780
1781 static int wl12xx_get_clock_idx(const struct wl12xx_clock *table,
1782                                 u32 freq, bool xtal)
1783 {
1784         int i;
1785
1786         for (i = 0; table[i].freq != 0; i++)
1787                 if ((table[i].freq == freq) && (table[i].xtal == xtal))
1788                         return table[i].hw_idx;
1789
1790         return -EINVAL;
1791 }
1792
1793 static int wl12xx_setup(struct wl1271 *wl)
1794 {
1795         struct wl12xx_priv *priv = wl->priv;
1796         struct wlcore_platdev_data *pdev_data = dev_get_platdata(&wl->pdev->dev);
1797
1798         BUILD_BUG_ON(WL12XX_MAX_LINKS > WLCORE_MAX_LINKS);
1799         BUILD_BUG_ON(WL12XX_MAX_AP_STATIONS > WL12XX_MAX_LINKS);
1800         BUILD_BUG_ON(WL12XX_CONF_SG_PARAMS_MAX > WLCORE_CONF_SG_PARAMS_MAX);
1801
1802         wl->rtable = wl12xx_rtable;
1803         wl->num_tx_desc = WL12XX_NUM_TX_DESCRIPTORS;
1804         wl->num_rx_desc = WL12XX_NUM_RX_DESCRIPTORS;
1805         wl->num_links = WL12XX_MAX_LINKS;
1806         wl->max_ap_stations = WL12XX_MAX_AP_STATIONS;
1807         wl->iface_combinations = wl12xx_iface_combinations;
1808         wl->n_iface_combinations = ARRAY_SIZE(wl12xx_iface_combinations);
1809         wl->num_mac_addr = WL12XX_NUM_MAC_ADDRESSES;
1810         wl->band_rate_to_idx = wl12xx_band_rate_to_idx;
1811         wl->hw_tx_rate_tbl_size = WL12XX_CONF_HW_RXTX_RATE_MAX;
1812         wl->hw_min_ht_rate = WL12XX_CONF_HW_RXTX_RATE_MCS0;
1813         wl->fw_status_len = sizeof(struct wl12xx_fw_status);
1814         wl->fw_status_priv_len = 0;
1815         wl->stats.fw_stats_len = sizeof(struct wl12xx_acx_statistics);
1816         wl->ofdm_only_ap = true;
1817         wlcore_set_ht_cap(wl, NL80211_BAND_2GHZ, &wl12xx_ht_cap);
1818         wlcore_set_ht_cap(wl, NL80211_BAND_5GHZ, &wl12xx_ht_cap);
1819         wl12xx_conf_init(wl);
1820
1821         if (!fref_param) {
1822                 priv->ref_clock = wl12xx_get_clock_idx(wl12xx_refclock_table,
1823                                                 pdev_data->ref_clock_freq,
1824                                                 pdev_data->ref_clock_xtal);
1825                 if (priv->ref_clock < 0) {
1826                         wl1271_error("Invalid ref_clock frequency (%d Hz, %s)",
1827                                      pdev_data->ref_clock_freq,
1828                                      pdev_data->ref_clock_xtal ?
1829                                      "XTAL" : "not XTAL");
1830
1831                         return priv->ref_clock;
1832                 }
1833         } else {
1834                 if (!strcmp(fref_param, "19.2"))
1835                         priv->ref_clock = WL12XX_REFCLOCK_19;
1836                 else if (!strcmp(fref_param, "26"))
1837                         priv->ref_clock = WL12XX_REFCLOCK_26;
1838                 else if (!strcmp(fref_param, "26x"))
1839                         priv->ref_clock = WL12XX_REFCLOCK_26_XTAL;
1840                 else if (!strcmp(fref_param, "38.4"))
1841                         priv->ref_clock = WL12XX_REFCLOCK_38;
1842                 else if (!strcmp(fref_param, "38.4x"))
1843                         priv->ref_clock = WL12XX_REFCLOCK_38_XTAL;
1844                 else if (!strcmp(fref_param, "52"))
1845                         priv->ref_clock = WL12XX_REFCLOCK_52;
1846                 else
1847                         wl1271_error("Invalid fref parameter %s", fref_param);
1848         }
1849
1850         if (!tcxo_param && pdev_data->tcxo_clock_freq) {
1851                 priv->tcxo_clock = wl12xx_get_clock_idx(wl12xx_tcxoclock_table,
1852                                                 pdev_data->tcxo_clock_freq,
1853                                                 true);
1854                 if (priv->tcxo_clock < 0) {
1855                         wl1271_error("Invalid tcxo_clock frequency (%d Hz)",
1856                                      pdev_data->tcxo_clock_freq);
1857
1858                         return priv->tcxo_clock;
1859                 }
1860         } else if (tcxo_param) {
1861                 if (!strcmp(tcxo_param, "19.2"))
1862                         priv->tcxo_clock = WL12XX_TCXOCLOCK_19_2;
1863                 else if (!strcmp(tcxo_param, "26"))
1864                         priv->tcxo_clock = WL12XX_TCXOCLOCK_26;
1865                 else if (!strcmp(tcxo_param, "38.4"))
1866                         priv->tcxo_clock = WL12XX_TCXOCLOCK_38_4;
1867                 else if (!strcmp(tcxo_param, "52"))
1868                         priv->tcxo_clock = WL12XX_TCXOCLOCK_52;
1869                 else if (!strcmp(tcxo_param, "16.368"))
1870                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_368;
1871                 else if (!strcmp(tcxo_param, "32.736"))
1872                         priv->tcxo_clock = WL12XX_TCXOCLOCK_32_736;
1873                 else if (!strcmp(tcxo_param, "16.8"))
1874                         priv->tcxo_clock = WL12XX_TCXOCLOCK_16_8;
1875                 else if (!strcmp(tcxo_param, "33.6"))
1876                         priv->tcxo_clock = WL12XX_TCXOCLOCK_33_6;
1877                 else
1878                         wl1271_error("Invalid tcxo parameter %s", tcxo_param);
1879         }
1880
1881         priv->rx_mem_addr = kmalloc(sizeof(*priv->rx_mem_addr), GFP_KERNEL);
1882         if (!priv->rx_mem_addr)
1883                 return -ENOMEM;
1884
1885         return 0;
1886 }
1887
1888 static int wl12xx_probe(struct platform_device *pdev)
1889 {
1890         struct wl1271 *wl;
1891         struct ieee80211_hw *hw;
1892         int ret;
1893
1894         hw = wlcore_alloc_hw(sizeof(struct wl12xx_priv),
1895                              WL12XX_AGGR_BUFFER_SIZE,
1896                              sizeof(struct wl12xx_event_mailbox));
1897         if (IS_ERR(hw)) {
1898                 wl1271_error("can't allocate hw");
1899                 ret = PTR_ERR(hw);
1900                 goto out;
1901         }
1902
1903         wl = hw->priv;
1904         wl->ops = &wl12xx_ops;
1905         wl->ptable = wl12xx_ptable;
1906         ret = wlcore_probe(wl, pdev);
1907         if (ret)
1908                 goto out_free;
1909
1910         return ret;
1911
1912 out_free:
1913         wlcore_free_hw(wl);
1914 out:
1915         return ret;
1916 }
1917
1918 static int wl12xx_remove(struct platform_device *pdev)
1919 {
1920         struct wl1271 *wl = platform_get_drvdata(pdev);
1921         struct wl12xx_priv *priv;
1922
1923         if (!wl)
1924                 goto out;
1925         priv = wl->priv;
1926
1927         kfree(priv->rx_mem_addr);
1928
1929 out:
1930         return wlcore_remove(pdev);
1931 }
1932
1933 static const struct platform_device_id wl12xx_id_table[] = {
1934         { "wl12xx", 0 },
1935         {  } /* Terminating Entry */
1936 };
1937 MODULE_DEVICE_TABLE(platform, wl12xx_id_table);
1938
1939 static struct platform_driver wl12xx_driver = {
1940         .probe          = wl12xx_probe,
1941         .remove         = wl12xx_remove,
1942         .id_table       = wl12xx_id_table,
1943         .driver = {
1944                 .name   = "wl12xx_driver",
1945         }
1946 };
1947
1948 module_platform_driver(wl12xx_driver);
1949
1950 module_param_named(fref, fref_param, charp, 0);
1951 MODULE_PARM_DESC(fref, "FREF clock: 19.2, 26, 26x, 38.4, 38.4x, 52");
1952
1953 module_param_named(tcxo, tcxo_param, charp, 0);
1954 MODULE_PARM_DESC(tcxo,
1955                  "TCXO clock: 19.2, 26, 38.4, 52, 16.368, 32.736, 16.8, 33.6");
1956
1957 MODULE_LICENSE("GPL v2");
1958 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1959 /*(DEBLOBBED)*/