1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
10 extern u8 rtw_cck_rates[];
11 extern u8 rtw_ofdm_rates[];
12 extern u8 rtw_ht_1s_rates[];
13 extern u8 rtw_ht_2s_rates[];
14 extern u8 rtw_vht_1s_rates[];
15 extern u8 rtw_vht_2s_rates[];
16 extern u8 *rtw_rate_section[];
17 extern u8 rtw_rate_size[];
19 void rtw_phy_init(struct rtw_dev *rtwdev);
20 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev);
21 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num);
22 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
24 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
25 u32 addr, u32 mask, u32 data);
26 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
27 u32 addr, u32 mask, u32 data);
28 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
29 u32 addr, u32 mask, u32 data);
30 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg);
31 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
32 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
33 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
34 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
36 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
38 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
40 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
42 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev);
43 void rtw_phy_load_tables(struct rtw_dev *rtwdev);
44 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel);
45 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal);
46 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal);
48 #define RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, path) \
49 const struct rtw_table name ## _tbl = { \
51 .size = ARRAY_SIZE(name), \
52 .parse = rtw_parse_tbl_phy_cond, \
57 #define RTW_DECL_TABLE_PHY_COND(name, cfg) \
58 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
60 #define RTW_DECL_TABLE_RF_RADIO(name, path) \
61 RTW_DECL_TABLE_PHY_COND_CORE(name, rtw_phy_cfg_rf, RF_PATH_ ## path)
63 #define RTW_DECL_TABLE_BB_PG(name) \
64 const struct rtw_table name ## _tbl = { \
66 .size = ARRAY_SIZE(name), \
67 .parse = rtw_parse_tbl_bb_pg, \
70 #define RTW_DECL_TABLE_TXPWR_LMT(name) \
71 const struct rtw_table name ## _tbl = { \
73 .size = ARRAY_SIZE(name), \
74 .parse = rtw_parse_tbl_txpwr_lmt, \
77 static inline const struct rtw_rfe_def *rtw_get_rfe_def(struct rtw_dev *rtwdev)
79 struct rtw_chip_info *chip = rtwdev->chip;
80 struct rtw_efuse *efuse = &rtwdev->efuse;
81 const struct rtw_rfe_def *rfe_def = NULL;
83 if (chip->rfe_defs_size == 0)
86 if (efuse->rfe_option < chip->rfe_defs_size)
87 rfe_def = &chip->rfe_defs[efuse->rfe_option];
89 rtw_dbg(rtwdev, RTW_DBG_PHY, "use rfe_def[%d]\n", efuse->rfe_option);
93 static inline int rtw_check_supported_rfe(struct rtw_dev *rtwdev)
95 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
97 if (!rfe_def || !rfe_def->phy_pg_tbl || !rfe_def->txpwr_lmt_tbl) {
98 rtw_err(rtwdev, "rfe %d isn't supported\n",
99 rtwdev->efuse.rfe_option);
106 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi);
108 struct rtw_power_params {
115 rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path,
116 u8 rate, u8 bw, u8 ch, u8 regd,
117 struct rtw_power_params *pwr_param);
119 #define MASKBYTE0 0xff
120 #define MASKBYTE1 0xff00
121 #define MASKBYTE2 0xff0000
122 #define MASKBYTE3 0xff000000
123 #define MASKHWORD 0xffff0000
124 #define MASKLWORD 0x0000ffff
125 #define MASKDWORD 0xffffffff
126 #define RFREG_MASK 0xfffff
128 #define MASK7BITS 0x7f
129 #define MASK12BITS 0xfff
130 #define MASKH4BITS 0xf0000000
131 #define MASK20BITS 0xfffff
132 #define MASK24BITS 0xffffff
134 #define MASKH3BYTES 0xffffff00
135 #define MASKL3BYTES 0x00ffffff
136 #define MASKBYTE2HIGHNIBBLE 0x00f00000
137 #define MASKBYTE3LOWNIBBLE 0x0f000000
138 #define MASKL3BYTES 0x00ffffff