1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
33 static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
35 void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
40 case HT_CHANNEL_WIDTH_20:
41 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
42 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
44 case HT_CHANNEL_WIDTH_20_40:
45 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
46 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
48 case HT_CHANNEL_WIDTH_80:
49 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
50 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
53 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
54 "unknown bandwidth: %#X\n", bandwidth);
59 void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_phy *rtlphy = &rtlpriv->phy;
64 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
65 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
66 u32 tx_agc[2] = {0, 0}, tmpval;
67 bool turbo_scanoff = false;
73 if (rtlefuse->eeprom_regulatory != 0)
76 if (mac->act_scanning) {
77 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
78 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
81 for (idx1 = RF90_PATH_A;
84 tx_agc[idx1] = ppowerlevel[idx1] |
85 (ppowerlevel[idx1] << 8) |
86 (ppowerlevel[idx1] << 16) |
87 (ppowerlevel[idx1] << 24);
91 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
92 tx_agc[idx1] = ppowerlevel[idx1] |
93 (ppowerlevel[idx1] << 8) |
94 (ppowerlevel[idx1] << 16) |
95 (ppowerlevel[idx1] << 24);
98 if (rtlefuse->eeprom_regulatory == 0) {
100 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
101 (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
103 tx_agc[RF90_PATH_A] += tmpval;
105 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
106 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
108 tx_agc[RF90_PATH_B] += tmpval;
112 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
113 ptr = (u8 *)(&tx_agc[idx1]);
114 for (idx2 = 0; idx2 < 4; idx2++) {
115 if (*ptr > RF6052_MAX_TX_PWR)
116 *ptr = RF6052_MAX_TX_PWR;
120 rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
121 if (direction == 1) {
122 tx_agc[0] += pwrtrac_value;
123 tx_agc[1] += pwrtrac_value;
124 } else if (direction == 2) {
125 tx_agc[0] -= pwrtrac_value;
126 tx_agc[1] -= pwrtrac_value;
128 tmpval = tx_agc[RF90_PATH_A];
129 rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval);
131 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
132 "CCK PWR 1~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
133 RTXAGC_A_CCK11_CCK1);
135 tmpval = tx_agc[RF90_PATH_B];
136 rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval);
138 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
139 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
140 RTXAGC_B_CCK11_CCK1);
143 static void rtl8821ae_phy_get_power_base(struct ieee80211_hw *hw,
144 u8 *ppowerlevel_ofdm,
145 u8 *ppowerlevel_bw20,
146 u8 *ppowerlevel_bw40, u8 channel,
147 u32 *ofdmbase, u32 *mcsbase)
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 struct rtl_phy *rtlphy = &rtlpriv->phy;
151 u32 powerbase0, powerbase1;
154 for (i = 0; i < 2; i++) {
155 powerbase0 = ppowerlevel_ofdm[i];
157 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
158 (powerbase0 << 8) | powerbase0;
159 *(ofdmbase + i) = powerbase0;
160 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
161 " [OFDM power base index rf(%c) = 0x%x]\n",
162 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
165 for (i = 0; i < 2; i++) {
166 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
167 powerlevel[i] = ppowerlevel_bw20[i];
169 powerlevel[i] = ppowerlevel_bw40[i];
171 powerbase1 = powerlevel[i];
172 powerbase1 = (powerbase1 << 24) |
173 (powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
175 *(mcsbase + i) = powerbase1;
177 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
178 " [MCS power base index rf(%c) = 0x%x]\n",
179 ((i == 0) ? 'A' : 'B'), *(mcsbase + i));
183 static void get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
184 u8 channel, u8 index,
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_phy *rtlphy = &rtlpriv->phy;
191 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
192 u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
193 u32 writeval, customer_limit, rf;
195 for (rf = 0; rf < 2; rf++) {
196 switch (rtlefuse->eeprom_regulatory) {
201 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
203 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
205 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
206 "RTK better performance, writeval(%c) = 0x%x\n",
207 ((rf == 0) ? 'A' : 'B'), writeval);
210 if (rtlphy->pwrgroup_cnt == 1) {
215 else if (channel < 6)
217 else if (channel < 9)
219 else if (channel < 12)
221 else if (channel < 14)
223 else if (channel == 14)
228 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
229 [index + (rf ? 8 : 0)] + ((index < 2) ?
233 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
234 "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
235 ((rf == 0) ? 'A' : 'B'), writeval);
240 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
242 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
243 "Better regulatory, writeval(%c) = 0x%x\n",
244 ((rf == 0) ? 'A' : 'B'), writeval);
249 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
250 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
251 "customer's limit, 40MHz rf(%c) = 0x%x\n",
252 ((rf == 0) ? 'A' : 'B'),
253 rtlefuse->pwrgroup_ht40[rf][channel -
256 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
257 "customer's limit, 20MHz rf(%c) = 0x%x\n",
258 ((rf == 0) ? 'A' : 'B'),
259 rtlefuse->pwrgroup_ht20[rf][channel -
264 pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
265 else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
267 rtlefuse->txpwr_ht20diff[rf][channel-1];
269 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
271 rtlefuse->pwrgroup_ht40[rf][channel-1];
274 rtlefuse->pwrgroup_ht20[rf][channel-1];
276 if (pwr_diff > customer_pwr_diff)
279 pwr_diff = customer_pwr_diff - pwr_diff;
281 for (i = 0; i < 4; i++) {
283 (u8)((rtlphy->mcs_txpwrlevel_origoffset
284 [chnlgroup][index + (rf ? 8 : 0)] &
285 (0x7f << (i * 8))) >> (i * 8));
287 if (pwr_diff_limit[i] > pwr_diff)
288 pwr_diff_limit[i] = pwr_diff;
291 customer_limit = (pwr_diff_limit[3] << 24) |
292 (pwr_diff_limit[2] << 16) |
293 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
295 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
296 "Customer's limit rf(%c) = 0x%x\n",
297 ((rf == 0) ? 'A' : 'B'), customer_limit);
299 writeval = customer_limit +
300 ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
302 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
303 "Customer, writeval rf(%c)= 0x%x\n",
304 ((rf == 0) ? 'A' : 'B'), writeval);
309 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
310 [index + (rf ? 8 : 0)]
311 + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
314 "RTK better performance, writeval rf(%c) = 0x%x\n",
315 ((rf == 0) ? 'A' : 'B'), writeval);
319 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
320 writeval = writeval - 0x06060606;
321 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
323 writeval = writeval - 0x0c0c0c0c;
324 *(p_outwriteval + rf) = writeval;
328 static void _rtl8821ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
329 u8 index, u32 *pvalue)
331 struct rtl_priv *rtlpriv = rtl_priv(hw);
332 u16 regoffset_a[6] = {
333 RTXAGC_A_OFDM18_OFDM6, RTXAGC_A_OFDM54_OFDM24,
334 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
335 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
337 u16 regoffset_b[6] = {
338 RTXAGC_B_OFDM18_OFDM6, RTXAGC_B_OFDM54_OFDM24,
339 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
340 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
342 u8 i, rf, pwr_val[4];
346 for (rf = 0; rf < 2; rf++) {
347 writeval = pvalue[rf];
348 for (i = 0; i < 4; i++) {
349 pwr_val[i] = (u8)((writeval & (0x7f <<
350 (i * 8))) >> (i * 8));
352 if (pwr_val[i] > RF6052_MAX_TX_PWR)
353 pwr_val[i] = RF6052_MAX_TX_PWR;
355 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
356 (pwr_val[1] << 8) | pwr_val[0];
359 regoffset = regoffset_a[index];
361 regoffset = regoffset_b[index];
362 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval);
364 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
365 "Set 0x%x = %08x\n", regoffset, writeval);
369 void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
370 u8 *ppowerlevel_ofdm,
371 u8 *ppowerlevel_bw20,
372 u8 *ppowerlevel_bw40,
375 u32 writeval[2], powerbase0[2], powerbase1[2];
380 rtl8821ae_phy_get_power_base(hw, ppowerlevel_ofdm,
387 rtl8821ae_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
389 for (index = 0; index < 6; index++) {
390 get_txpower_writeval_by_regulatory(hw, channel, index,
394 if (direction == 1) {
395 writeval[0] += pwrtrac_value;
396 writeval[1] += pwrtrac_value;
397 } else if (direction == 2) {
398 writeval[0] -= pwrtrac_value;
399 writeval[1] -= pwrtrac_value;
401 _rtl8821ae_write_ofdm_power_reg(hw, index, &writeval[0]);
405 bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw)
407 struct rtl_priv *rtlpriv = rtl_priv(hw);
408 struct rtl_phy *rtlphy = &rtlpriv->phy;
410 if (rtlphy->rf_type == RF_1T1R)
411 rtlphy->num_total_rfpath = 1;
413 rtlphy->num_total_rfpath = 2;
415 return _rtl8821ae_phy_rf6052_config_parafile(hw);
418 static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
420 struct rtl_priv *rtlpriv = rtl_priv(hw);
421 struct rtl_phy *rtlphy = &rtlpriv->phy;
422 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
424 bool rtstatus = true;
426 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
429 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
431 rtl8812ae_phy_config_rf_with_headerfile(hw,
432 (enum radio_path)rfpath);
435 rtl8821ae_phy_config_rf_with_headerfile(hw,
436 (enum radio_path)rfpath);
440 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
442 rtl8812ae_phy_config_rf_with_headerfile(hw,
443 (enum radio_path)rfpath);
446 rtl8821ae_phy_config_rf_with_headerfile(hw,
447 (enum radio_path)rfpath);
456 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
457 "Radio[%d] Fail!!\n", rfpath);
462 /*put arrays in dm.c*/
463 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");