drivers/net/wireless/realtek/rtlwifi/rtl8821ae/def.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2010  Realtek Corporation.*/
   3
   4 #ifndef __RTL8821AE_DEF_H__
   5 #define __RTL8821AE_DEF_H__
   6
   7 /*--------------------------Define -------------------------------------------*/
   8 #define USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN       1
   9
  10 /* BIT 7 HT Rate*/
  11 /*TxHT = 0*/
  12 #define MGN_1M                          0x02
  13 #define MGN_2M                          0x04
  14 #define MGN_5_5M                        0x0b
  15 #define MGN_11M                         0x16
  16
  17 #define MGN_6M                          0x0c
  18 #define MGN_9M                          0x12
  19 #define MGN_12M                         0x18
  20 #define MGN_18M                         0x24
  21 #define MGN_24M                         0x30
  22 #define MGN_36M                         0x48
  23 #define MGN_48M                         0x60
  24 #define MGN_54M                         0x6c
  25
  26 /* TxHT = 1 */
  27 #define MGN_MCS0                        0x80
  28 #define MGN_MCS1                        0x81
  29 #define MGN_MCS2                        0x82
  30 #define MGN_MCS3                        0x83
  31 #define MGN_MCS4                        0x84
  32 #define MGN_MCS5                        0x85
  33 #define MGN_MCS6                        0x86
  34 #define MGN_MCS7                        0x87
  35 #define MGN_MCS8                        0x88
  36 #define MGN_MCS9                        0x89
  37 #define MGN_MCS10                       0x8a
  38 #define MGN_MCS11                       0x8b
  39 #define MGN_MCS12                       0x8c
  40 #define MGN_MCS13                       0x8d
  41 #define MGN_MCS14                       0x8e
  42 #define MGN_MCS15                       0x8f
  43 /* VHT rate */
  44 #define MGN_VHT1SS_MCS0         0x90
  45 #define MGN_VHT1SS_MCS1         0x91
  46 #define MGN_VHT1SS_MCS2         0x92
  47 #define MGN_VHT1SS_MCS3         0x93
  48 #define MGN_VHT1SS_MCS4         0x94
  49 #define MGN_VHT1SS_MCS5         0x95
  50 #define MGN_VHT1SS_MCS6         0x96
  51 #define MGN_VHT1SS_MCS7         0x97
  52 #define MGN_VHT1SS_MCS8         0x98
  53 #define MGN_VHT1SS_MCS9         0x99
  54 #define MGN_VHT2SS_MCS0         0x9a
  55 #define MGN_VHT2SS_MCS1         0x9b
  56 #define MGN_VHT2SS_MCS2         0x9c
  57 #define MGN_VHT2SS_MCS3         0x9d
  58 #define MGN_VHT2SS_MCS4         0x9e
  59 #define MGN_VHT2SS_MCS5         0x9f
  60 #define MGN_VHT2SS_MCS6         0xa0
  61 #define MGN_VHT2SS_MCS7         0xa1
  62 #define MGN_VHT2SS_MCS8         0xa2
  63 #define MGN_VHT2SS_MCS9         0xa3
  64
  65 #define MGN_VHT3SS_MCS0         0xa4
  66 #define MGN_VHT3SS_MCS1         0xa5
  67 #define MGN_VHT3SS_MCS2         0xa6
  68 #define MGN_VHT3SS_MCS3         0xa7
  69 #define MGN_VHT3SS_MCS4         0xa8
  70 #define MGN_VHT3SS_MCS5         0xa9
  71 #define MGN_VHT3SS_MCS6         0xaa
  72 #define MGN_VHT3SS_MCS7         0xab
  73 #define MGN_VHT3SS_MCS8         0xac
  74 #define MGN_VHT3SS_MCS9         0xad
  75
  76 #define MGN_MCS0_SG                     0xc0
  77 #define MGN_MCS1_SG                     0xc1
  78 #define MGN_MCS2_SG                     0xc2
  79 #define MGN_MCS3_SG                     0xc3
  80 #define MGN_MCS4_SG                     0xc4
  81 #define MGN_MCS5_SG                     0xc5
  82 #define MGN_MCS6_SG                     0xc6
  83 #define MGN_MCS7_SG                     0xc7
  84 #define MGN_MCS8_SG                     0xc8
  85 #define MGN_MCS9_SG                     0xc9
  86 #define MGN_MCS10_SG            0xca
  87 #define MGN_MCS11_SG            0xcb
  88 #define MGN_MCS12_SG            0xcc
  89 #define MGN_MCS13_SG            0xcd
  90 #define MGN_MCS14_SG            0xce
  91 #define MGN_MCS15_SG            0xcf
  92
  93 #define MGN_UNKNOWN                     0xff
  94
  95 /* 30 ms */
  96 #define WIFI_NAV_UPPER_US                               30000
  97 #define HAL_92C_NAV_UPPER_UNIT                  128
  98
  99 #define MAX_RX_DMA_BUFFER_SIZE                          0x3E80
 100
 101 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 102 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 103 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 104
 105 #define RX_MPDU_QUEUE                                           0
 106 #define RX_CMD_QUEUE                                            1
 107
 108 #define MAX_RX_DMA_BUFFER_SIZE_8812     0x3E80
 109
 110 #define C2H_RX_CMD_HDR_LEN                                      8
 111 #define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
 112         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
 113 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
 114         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
 115 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
 116         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
 117 #define GET_C2H_CMD_CONTINUE(__prxhdr)          \
 118         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
 119 #define GET_C2H_CMD_CONTENT(__prxhdr)           \
 120         ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
 121
 122 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
 123         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
 124 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)               \
 125         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
 126 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
 127         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
 128 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
 129         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
 130 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)             \
 131         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
 132 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 133         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 134 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)               \
 135         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 136 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)              \
 137         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 138 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)               \
 139         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 140
 141 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 142
 143 #define CHIP_8812                               BIT(2)
 144 #define CHIP_8821                               (BIT(0)|BIT(2))
 145
 146 #define CHIP_8821A                              (BIT(0)|BIT(2))
 147 #define NORMAL_CHIP                             BIT(3)
 148 #define RF_TYPE_1T1R                            (~(BIT(4)|BIT(5)|BIT(6)))
 149 #define RF_TYPE_1T2R                            BIT(4)
 150 #define RF_TYPE_2T2R                            BIT(5)
 151 #define CHIP_VENDOR_UMC                         BIT(7)
 152 #define B_CUT_VERSION                           BIT(12)
 153 #define C_CUT_VERSION                           BIT(13)
 154 #define D_CUT_VERSION                           ((BIT(12)|BIT(13)))
 155 #define E_CUT_VERSION                           BIT(14)
 156 #define RF_RL_ID                        (BIT(31)|BIT(30)|BIT(29)|BIT(28))
 157
 158 enum version_8821ae {
 159         VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
 160         VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
 161         VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
 162         VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
 163         VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
 164         VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
 165         VERSION_TEST_CHIP_8821 = 0x0005,
 166         VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
 167         VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
 168         VERSION_UNKNOWN = 0xFF,
 169 };
 170
 171 enum vht_data_sc {
 172         VHT_DATA_SC_DONOT_CARE = 0,
 173         VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
 174         VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
 175         VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
 176         VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
 177         VHT_DATA_SC_20_RECV1 = 5,
 178         VHT_DATA_SC_20_RECV2 = 6,
 179         VHT_DATA_SC_20_RECV3 = 7,
 180         VHT_DATA_SC_20_RECV4 = 8,
 181         VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
 182         VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
 183 };
 184
 185 /* MASK */
 186 #define IC_TYPE_MASK                    (BIT(0)|BIT(1)|BIT(2))
 187 #define CHIP_TYPE_MASK                  BIT(3)
 188 #define RF_TYPE_MASK                    (BIT(4)|BIT(5)|BIT(6))
 189 #define MANUFACTUER_MASK                BIT(7)
 190 #define ROM_VERSION_MASK                (BIT(11)|BIT(10)|BIT(9)|BIT(8))
 191 #define CUT_VERSION_MASK                (BIT(15)|BIT(14)|BIT(13)|BIT(12))
 192
 193 /* Get element */
 194 #define GET_CVID_IC_TYPE(version)       ((version) & IC_TYPE_MASK)
 195 #define GET_CVID_CHIP_TYPE(version)     ((version) & CHIP_TYPE_MASK)
 196 #define GET_CVID_RF_TYPE(version)       ((version) & RF_TYPE_MASK)
 197 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
 198 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
 199 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
 200
 201 #define IS_1T1R(version)        ((GET_CVID_RF_TYPE(version)) ? false : true)
 202 #define IS_1T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
 203                                                         ? true : false)
 204 #define IS_2T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
 205                                                         ? true : false)
 206
 207 #define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? \
 208                                                                 true : false)
 209 #define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? \
 210                                                                 true : false)
 211
 212 #define IS_VENDOR_8812A_TEST_CHIP(version)      ((IS_8812_SERIES(version)) ? \
 213                                         ((IS_NORMAL_CHIP(version)) ? \
 214                                                 false : true) : false)
 215 #define IS_VENDOR_8812A_MP_CHIP(version)        ((IS_8812_SERIES(version)) ? \
 216                                         ((IS_NORMAL_CHIP(version)) ? \
 217                                                 true : false) : false)
 218 #define IS_VENDOR_8812A_C_CUT(version)          ((IS_8812_SERIES(version)) ? \
 219                                         ((GET_CVID_CUT_VERSION(version) == \
 220                                         C_CUT_VERSION) ? \
 221                                         true : false) : false)
 222
 223 #define IS_VENDOR_8821A_TEST_CHIP(version)      ((IS_8821_SERIES(version)) ? \
 224                                         ((IS_NORMAL_CHIP(version)) ? \
 225                                         false : true) : false)
 226 #define IS_VENDOR_8821A_MP_CHIP(version)        ((IS_8821_SERIES(version)) ? \
 227                                         ((IS_NORMAL_CHIP(version)) ? \
 228                                                 true : false) : false)
 229 #define IS_VENDOR_8821A_B_CUT(version)          ((IS_8821_SERIES(version)) ? \
 230                                         ((GET_CVID_CUT_VERSION(version) == \
 231                                         B_CUT_VERSION) ? \
 232                                         true : false) : false)
 233 enum board_type {
 234         ODM_BOARD_DEFAULT = 0,    /* The DEFAULT case. */
 235         ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */
 236         ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
 237         ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
 238         ODM_BOARD_EXT_PA = BIT(3), /* 1 = existing 2G ext-PA */
 239         ODM_BOARD_EXT_LNA = BIT(4), /* 1 = existing 2G ext-LNA */
 240         ODM_BOARD_EXT_TRSW = BIT(5), /* 1 = existing ext-TRSW */
 241         ODM_BOARD_EXT_PA_5G = BIT(6), /* 1 = existing 5G ext-PA */
 242         ODM_BOARD_EXT_LNA_5G = BIT(7), /* 1 = existing 5G ext-LNA */
 243 };
 244
 245 enum rf_optype {
 246         RF_OP_BY_SW_3WIRE = 0,
 247         RF_OP_BY_FW,
 248         RF_OP_MAX
 249 };
 250
 251 enum rf_power_state {
 252         RF_ON,
 253         RF_OFF,
 254         RF_SLEEP,
 255         RF_SHUT_DOWN,
 256 };
 257
 258 enum power_save_mode {
 259         POWER_SAVE_MODE_ACTIVE,
 260         POWER_SAVE_MODE_SAVE,
 261 };
 262
 263 enum power_polocy_config {
 264         POWERCFG_MAX_POWER_SAVINGS,
 265         POWERCFG_GLOBAL_POWER_SAVINGS,
 266         POWERCFG_LOCAL_POWER_SAVINGS,
 267         POWERCFG_LENOVO,
 268 };
 269
 270 enum interface_select_pci {
 271         INTF_SEL1_MINICARD = 0,
 272         INTF_SEL0_PCIE = 1,
 273         INTF_SEL2_RSV = 2,
 274         INTF_SEL3_RSV = 3,
 275 };
 276
 277 enum rtl_desc_qsel {
 278         QSLT_BK = 0x2,
 279         QSLT_BE = 0x0,
 280         QSLT_VI = 0x5,
 281         QSLT_VO = 0x7,
 282         QSLT_BEACON = 0x10,
 283         QSLT_HIGH = 0x11,
 284         QSLT_MGNT = 0x12,
 285         QSLT_CMD = 0x13,
 286 };
 287
 288 struct phy_sts_cck_8821ae_t {
 289         u8 adc_pwdb_X[4];
 290         u8 sq_rpt;
 291         u8 cck_agc_rpt;
 292 };
 293
 294 struct h2c_cmd_8821ae {
 295         u8 element_id;
 296         u32 cmd_len;
 297         u8 *p_cmdbuffer;
 298 };
 299
 300 #endif