drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "phy_common.h"
   6 #include "../rtl8723ae/reg.h"
   7 #include <linux/module.h>
   8
   9 /* These routines are common to RTL8723AE and RTL8723bE */
  10
  11 u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw,
  12                              u32 regaddr, u32 bitmask)
  13 {
  14         struct rtl_priv *rtlpriv = rtl_priv(hw);
  15         u32 returnvalue, originalvalue, bitshift;
  16
  17         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  18                  "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
  19         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  20         bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
  21         returnvalue = (originalvalue & bitmask) >> bitshift;
  22
  23         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  24                  "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
  25                  regaddr, originalvalue);
  26         return returnvalue;
  27 }
  28 EXPORT_SYMBOL_GPL(rtl8723_phy_query_bb_reg);
  29
  30 void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
  31                               u32 bitmask, u32 data)
  32 {
  33         struct rtl_priv *rtlpriv = rtl_priv(hw);
  34         u32 originalvalue, bitshift;
  35
  36         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  37                  "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
  38                  data);
  39
  40         if (bitmask != MASKDWORD) {
  41                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  42                 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
  43                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  44         }
  45
  46         rtl_write_dword(rtlpriv, regaddr, data);
  47
  48         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  49                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  50                  regaddr, bitmask, data);
  51 }
  52 EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg);
  53
  54 u32 rtl8723_phy_calculate_bit_shift(u32 bitmask)
  55 {
  56         u32 i;
  57
  58         for (i = 0; i <= 31; i++) {
  59                 if (((bitmask >> i) & 0x1) == 1)
  60                         break;
  61         }
  62         return i;
  63 }
  64 EXPORT_SYMBOL_GPL(rtl8723_phy_calculate_bit_shift);
  65
  66 u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw,
  67                                enum radio_path rfpath, u32 offset)
  68 {
  69         struct rtl_priv *rtlpriv = rtl_priv(hw);
  70         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  71         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
  72         u32 newoffset;
  73         u32 tmplong, tmplong2;
  74         u8 rfpi_enable = 0;
  75         u32 retvalue;
  76
  77         offset &= 0xff;
  78         newoffset = offset;
  79         if (RT_CANNOT_IO(hw)) {
  80                 pr_err("return all one\n");
  81                 return 0xFFFFFFFF;
  82         }
  83         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
  84         if (rfpath == RF90_PATH_A)
  85                 tmplong2 = tmplong;
  86         else
  87                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
  88         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
  89             (newoffset << 23) | BLSSIREADEDGE;
  90         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
  91                       tmplong & (~BLSSIREADEDGE));
  92         mdelay(1);
  93         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
  94         mdelay(1);
  95         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
  96                       tmplong | BLSSIREADEDGE);
  97         mdelay(1);
  98         if (rfpath == RF90_PATH_A)
  99                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 100                                                  BIT(8));
 101         else if (rfpath == RF90_PATH_B)
 102                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 103                                                  BIT(8));
 104         if (rfpi_enable)
 105                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 106                                          BLSSIREADBACKDATA);
 107         else
 108                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 109                                          BLSSIREADBACKDATA);
 110         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 111                  "RFR-%d Addr[0x%x]=0x%x\n",
 112                  rfpath, pphyreg->rf_rb, retvalue);
 113         return retvalue;
 114 }
 115 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_read);
 116
 117 void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw,
 118                                  enum radio_path rfpath,
 119                                  u32 offset, u32 data)
 120 {
 121         u32 data_and_addr;
 122         u32 newoffset;
 123         struct rtl_priv *rtlpriv = rtl_priv(hw);
 124         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 125         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 126
 127         if (RT_CANNOT_IO(hw)) {
 128                 pr_err("stop\n");
 129                 return;
 130         }
 131         offset &= 0xff;
 132         newoffset = offset;
 133         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 134         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 135         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 136                  "RFW-%d Addr[0x%x]=0x%x\n",
 137                  rfpath, pphyreg->rf3wire_offset,
 138                  data_and_addr);
 139 }
 140 EXPORT_SYMBOL_GPL(rtl8723_phy_rf_serial_write);
 141
 142 long rtl8723_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
 143                                   enum wireless_mode wirelessmode,
 144                                   u8 txpwridx)
 145 {
 146         long offset;
 147         long pwrout_dbm;
 148
 149         switch (wirelessmode) {
 150         case WIRELESS_MODE_B:
 151                 offset = -7;
 152                 break;
 153         case WIRELESS_MODE_G:
 154         case WIRELESS_MODE_N_24G:
 155                 offset = -8;
 156                 break;
 157         default:
 158                 offset = -8;
 159                 break;
 160         }
 161         pwrout_dbm = txpwridx / 2 + offset;
 162         return pwrout_dbm;
 163 }
 164 EXPORT_SYMBOL_GPL(rtl8723_phy_txpwr_idx_to_dbm);
 165
 166 void rtl8723_phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
 167 {
 168         struct rtl_priv *rtlpriv = rtl_priv(hw);
 169         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 170
 171         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 172         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 173         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 174         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 175
 176         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 177         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 178         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 179         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 180
 181         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 182         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 183
 184         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 185         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 186
 187         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 188             RFPGA0_XA_LSSIPARAMETER;
 189         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 190             RFPGA0_XB_LSSIPARAMETER;
 191
 192         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 193         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
 194         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 195         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
 196
 197         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 198         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 199         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 200         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 201
 202         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 203         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 204
 205         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 206         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 207
 208         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 209         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 210         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 211         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 212
 213         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 214         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 215         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 216         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 217
 218         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 219         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 220         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 221         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 222
 223         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 224         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 225         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
 226         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 227
 228         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 229         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 230         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 231         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 232
 233         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 234         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 235         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 236         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 237
 238         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 239         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 240         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 241         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 242
 243         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 244         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 245         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 246         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 247
 248         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
 249         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
 250
 251 }
 252 EXPORT_SYMBOL_GPL(rtl8723_phy_init_bb_rf_reg_def);
 253
 254 bool rtl8723_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 255                                       u32 cmdtableidx,
 256                                       u32 cmdtablesz,
 257                                       enum swchnlcmd_id cmdid,
 258                                       u32 para1, u32 para2,
 259                                       u32 msdelay)
 260 {
 261         struct swchnlcmd *pcmd;
 262
 263         if (cmdtable == NULL) {
 264                 WARN_ONCE(true, "rtl8723-common: cmdtable cannot be NULL.\n");
 265                 return false;
 266         }
 267
 268         if (cmdtableidx >= cmdtablesz)
 269                 return false;
 270
 271         pcmd = cmdtable + cmdtableidx;
 272         pcmd->cmdid = cmdid;
 273         pcmd->para1 = para1;
 274         pcmd->para2 = para2;
 275         pcmd->msdelay = msdelay;
 276         return true;
 277 }
 278 EXPORT_SYMBOL_GPL(rtl8723_phy_set_sw_chnl_cmdarray);
 279
 280 void rtl8723_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
 281                                         bool iqk_ok,
 282                                         long result[][8],
 283                                         u8 final_candidate,
 284                                         bool btxonly)
 285 {
 286         u32 oldval_0, x, tx0_a, reg;
 287         long y, tx0_c;
 288
 289         if (final_candidate == 0xFF) {
 290                 return;
 291         } else if (iqk_ok) {
 292                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 293                                           MASKDWORD) >> 22) & 0x3FF;
 294                 x = result[final_candidate][0];
 295                 if ((x & 0x00000200) != 0)
 296                         x = x | 0xFFFFFC00;
 297                 tx0_a = (x * oldval_0) >> 8;
 298                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
 299                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
 300                               ((x * oldval_0 >> 7) & 0x1));
 301                 y = result[final_candidate][1];
 302                 if ((y & 0x00000200) != 0)
 303                         y = y | 0xFFFFFC00;
 304                 tx0_c = (y * oldval_0) >> 8;
 305                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
 306                               ((tx0_c & 0x3C0) >> 6));
 307                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
 308                               (tx0_c & 0x3F));
 309                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
 310                               ((y * oldval_0 >> 7) & 0x1));
 311                 if (btxonly)
 312                         return;
 313                 reg = result[final_candidate][2];
 314                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
 315                 reg = result[final_candidate][3] & 0x3F;
 316                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
 317                 reg = (result[final_candidate][3] >> 6) & 0xF;
 318                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
 319         }
 320 }
 321 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_fill_iqk_matrix);
 322
 323 void rtl8723_save_adda_registers(struct ieee80211_hw *hw, u32 *addareg,
 324                                  u32 *addabackup, u32 registernum)
 325 {
 326         u32 i;
 327
 328         for (i = 0; i < registernum; i++)
 329                 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
 330 }
 331 EXPORT_SYMBOL_GPL(rtl8723_save_adda_registers);
 332
 333 void rtl8723_phy_save_mac_registers(struct ieee80211_hw *hw,
 334                                     u32 *macreg, u32 *macbackup)
 335 {
 336         struct rtl_priv *rtlpriv = rtl_priv(hw);
 337         u32 i;
 338
 339         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
 340                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
 341         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
 342 }
 343 EXPORT_SYMBOL_GPL(rtl8723_phy_save_mac_registers);
 344
 345 void rtl8723_phy_reload_adda_registers(struct ieee80211_hw *hw,
 346                                        u32 *addareg, u32 *addabackup,
 347                                        u32 regiesternum)
 348 {
 349         u32 i;
 350
 351         for (i = 0; i < regiesternum; i++)
 352                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
 353 }
 354 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_adda_registers);
 355
 356 void rtl8723_phy_reload_mac_registers(struct ieee80211_hw *hw,
 357                                       u32 *macreg, u32 *macbackup)
 358 {
 359         struct rtl_priv *rtlpriv = rtl_priv(hw);
 360         u32 i;
 361
 362         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
 363                 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
 364         rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
 365 }
 366 EXPORT_SYMBOL_GPL(rtl8723_phy_reload_mac_registers);
 367
 368 void rtl8723_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
 369                               bool is_patha_on, bool is2t)
 370 {
 371         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 372         u32 pathon;
 373         u32 i;
 374
 375         if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
 376                 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
 377                 if (!is2t) {
 378                         pathon = 0x0bdb25a0;
 379                         rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
 380                 } else {
 381                         rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
 382                 }
 383         } else {
 384                 /* rtl8723be */
 385                 pathon = 0x01c00014;
 386                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
 387         }
 388
 389         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
 390                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
 391 }
 392 EXPORT_SYMBOL_GPL(rtl8723_phy_path_adda_on);
 393
 394 void rtl8723_phy_mac_setting_calibration(struct ieee80211_hw *hw,
 395                                          u32 *macreg, u32 *macbackup)
 396 {
 397         struct rtl_priv *rtlpriv = rtl_priv(hw);
 398         u32 i = 0;
 399
 400         rtl_write_byte(rtlpriv, macreg[i], 0x3F);
 401
 402         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
 403                 rtl_write_byte(rtlpriv, macreg[i],
 404                                (u8) (macbackup[i] & (~BIT(3))));
 405         rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
 406 }
 407 EXPORT_SYMBOL_GPL(rtl8723_phy_mac_setting_calibration);
 408
 409 void rtl8723_phy_path_a_standby(struct ieee80211_hw *hw)
 410 {
 411         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
 412         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
 413         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
 414 }
 415 EXPORT_SYMBOL_GPL(rtl8723_phy_path_a_standby);
 416
 417 void rtl8723_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
 418 {
 419         u32 mode;
 420
 421         mode = pi_mode ? 0x01000100 : 0x01000000;
 422         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
 423         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
 424 }
 425 EXPORT_SYMBOL_GPL(rtl8723_phy_pi_mode_switch);