drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3
   4 #ifndef __RTL92E_PHY_H__
   5 #define __RTL92E_PHY_H__
   6
   7 /* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence
   8  * will be wrong.
   9  */
  10 #define MAX_TX_COUNT                            4
  11 #define TX_1S                                   0
  12 #define TX_2S                                   1
  13 #define TX_3S                                   2
  14 #define TX_4S                                   3
  15
  16 #define MAX_POWER_INDEX                         0x3f
  17
  18 #define MAX_PRECMD_CNT                          16
  19 #define MAX_RFDEPENDCMD_CNT                     16
  20 #define MAX_POSTCMD_CNT                         16
  21
  22 #define MAX_DOZE_WAITING_TIMES_9x               64
  23
  24 #define RT_CANNOT_IO(hw)                        false
  25 #define HIGHPOWER_RADIOA_ARRAYLEN               22
  26
  27 #define IQK_ADDA_REG_NUM                        16
  28 #define IQK_MAC_REG_NUM                         4
  29 #define IQK_BB_REG_NUM                          9
  30 #define MAX_TOLERANCE                           5
  31 #define IQK_DELAY_TIME                          10
  32 #define index_mapping_NUM                       15
  33
  34 #define APK_BB_REG_NUM                          5
  35 #define APK_AFE_REG_NUM                         16
  36 #define APK_CURVE_REG_NUM                       4
  37 #define PATH_NUM                                2
  38
  39 #define LOOP_LIMIT                              5
  40 #define MAX_STALL_TIME                          50
  41 #define ANTENNADIVERSITYVALUE                   0x80
  42 #define MAX_TXPWR_IDX_NMODE_92S                 63
  43 #define RESET_CNT_LIMIT                         3
  44
  45 #define RF6052_MAX_PATH                         2
  46
  47 #define CT_OFFSET_MAC_ADDR                      0X16
  48
  49 #define CT_OFFSET_CCK_TX_PWR_IDX                0x5A
  50 #define CT_OFFSET_HT401S_TX_PWR_IDX             0x60
  51 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF        0x66
  52 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF          0x69
  53 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF          0x6C
  54
  55 #define CT_OFFSET_HT40_MAX_PWR_OFFSET           0x6F
  56 #define CT_OFFSET_HT20_MAX_PWR_OFFSET           0x72
  57
  58 #define CT_OFFSET_CHANNEL_PLAH                  0x75
  59 #define CT_OFFSET_THERMAL_METER                 0x78
  60 #define CT_OFFSET_RF_OPTION                     0x79
  61 #define CT_OFFSET_VERSION                       0x7E
  62 #define CT_OFFSET_CUSTOMER_ID                   0x7F
  63
  64 #define RTL92C_MAX_PATH_NUM                     2
  65
  66 enum swchnlcmd_id {
  67         CMDID_END,
  68         CMDID_SET_TXPOWEROWER_LEVEL,
  69         CMDID_BBREGWRITE10,
  70         CMDID_WRITEPORT_ULONG,
  71         CMDID_WRITEPORT_USHORT,
  72         CMDID_WRITEPORT_UCHAR,
  73         CMDID_RF_WRITEREG,
  74 };
  75
  76 struct swchnlcmd {
  77         enum swchnlcmd_id cmdid;
  78         u32 para1;
  79         u32 para2;
  80         u32 msdelay;
  81 };
  82
  83 enum baseband_config_type {
  84         BASEBAND_CONFIG_PHY_REG = 0,
  85         BASEBAND_CONFIG_AGC_TAB = 1,
  86 };
  87
  88 enum ant_div_type {
  89         NO_ANTDIV = 0xFF,
  90         CG_TRX_HW_ANTDIV = 0x01,
  91         CGCS_RX_HW_ANTDIV = 0x02,
  92         FIXED_HW_ANTDIV = 0x03,
  93         CG_TRX_SMART_ANTDIV = 0x04,
  94         CGCS_RX_SW_ANTDIV = 0x05,
  95 };
  96
  97 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
  98                              u32 regaddr, u32 bitmask);
  99 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
 100                             u32 regaddr, u32 bitmask, u32 data);
 101 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
 102                              enum radio_path rfpath, u32 regaddr,
 103                              u32 bitmask);
 104 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
 105                             enum radio_path rfpath, u32 regaddr,
 106                             u32 bitmask, u32 data);
 107 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
 108 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
 109 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
 110 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
 111 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
 112                                    long *powerlevel);
 113 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
 114 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
 115                                        u8 operation);
 116 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
 117 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
 118                              enum nl80211_channel_type ch_type);
 119 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
 120 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
 121 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
 122 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
 123 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
 124 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
 125 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 126                                            enum radio_path rfpath);
 127 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
 128 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
 129                                     enum rf_pwrstate rfpwr_state);
 130
 131 #endif