drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4 #ifndef __RTL92D_PHY_H__
   5 #define __RTL92D_PHY_H__
   6
   7 #define MAX_PRECMD_CNT                          16
   8 #define MAX_RFDEPENDCMD_CNT                     16
   9 #define MAX_POSTCMD_CNT                         16
  10
  11 #define MAX_DOZE_WAITING_TIMES_9x               64
  12
  13 #define RT_CANNOT_IO(hw)                        false
  14 #define HIGHPOWER_RADIOA_ARRAYLEN               22
  15
  16 #define MAX_TOLERANCE                           5
  17
  18 #define APK_BB_REG_NUM                          5
  19 #define APK_AFE_REG_NUM                         16
  20 #define APK_CURVE_REG_NUM                       4
  21 #define PATH_NUM                                2
  22
  23 #define LOOP_LIMIT                              5
  24 #define MAX_STALL_TIME                          50
  25 #define ANTENNA_DIVERSITY_VALUE                 0x80
  26 #define MAX_TXPWR_IDX_NMODE_92S                 63
  27 #define RESET_CNT_LIMIT                         3
  28
  29 #define IQK_ADDA_REG_NUM                        16
  30 #define IQK_BB_REG_NUM                          10
  31 #define IQK_BB_REG_NUM_test                     6
  32 #define IQK_MAC_REG_NUM                         4
  33 #define RX_INDEX_MAPPING_NUM                    15
  34
  35 #define IQK_DELAY_TIME                          1
  36
  37 #define CT_OFFSET_MAC_ADDR                      0X16
  38
  39 #define CT_OFFSET_CCK_TX_PWR_IDX                0x5A
  40 #define CT_OFFSET_HT401S_TX_PWR_IDX             0x60
  41 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF        0x66
  42 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF          0x69
  43 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF          0x6C
  44
  45 #define CT_OFFSET_HT40_MAX_PWR_OFFSET           0x6F
  46 #define CT_OFFSET_HT20_MAX_PWR_OFFSET           0x72
  47
  48 #define CT_OFFSET_CHANNEL_PLAH                  0x75
  49 #define CT_OFFSET_THERMAL_METER                 0x78
  50 #define CT_OFFSET_RF_OPTION                     0x79
  51 #define CT_OFFSET_VERSION                       0x7E
  52 #define CT_OFFSET_CUSTOMER_ID                   0x7F
  53
  54 enum swchnlcmd_id {
  55         CMDID_END,
  56         CMDID_SET_TXPOWEROWER_LEVEL,
  57         CMDID_BBREGWRITE10,
  58         CMDID_WRITEPORT_ULONG,
  59         CMDID_WRITEPORT_USHORT,
  60         CMDID_WRITEPORT_UCHAR,
  61         CMDID_RF_WRITEREG,
  62 };
  63
  64 struct swchnlcmd {
  65         enum swchnlcmd_id cmdid;
  66         u32 para1;
  67         u32 para2;
  68         u32 msdelay;
  69 };
  70
  71 enum baseband_config_type {
  72         BASEBAND_CONFIG_PHY_REG = 0,
  73         BASEBAND_CONFIG_AGC_TAB = 1,
  74 };
  75
  76 enum rf_content {
  77         radioa_txt = 0,
  78         radiob_txt = 1,
  79         radioc_txt = 2,
  80         radiod_txt = 3
  81 };
  82
  83 static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
  84                                                      unsigned long *flag)
  85 {
  86         struct rtl_priv *rtlpriv = rtl_priv(hw);
  87
  88         if (rtlpriv->rtlhal.interfaceindex == 1)
  89                 spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
  90 }
  91
  92 static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
  93                                                      unsigned long *flag)
  94 {
  95         struct rtl_priv *rtlpriv = rtl_priv(hw);
  96
  97         if (rtlpriv->rtlhal.interfaceindex == 1)
  98                 spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
  99                         *flag);
 100 }
 101
 102 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
 103                             u32 regaddr, u32 bitmask);
 104 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
 105                            u32 regaddr, u32 bitmask, u32 data);
 106 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
 107                             enum radio_path rfpath, u32 regaddr,
 108                             u32 bitmask);
 109 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
 110                            enum radio_path rfpath, u32 regaddr,
 111                            u32 bitmask, u32 data);
 112 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
 113 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
 114 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
 115 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
 116                                           enum radio_path rfpath);
 117 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
 118 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
 119 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
 120                             enum nl80211_channel_type ch_type);
 121 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
 122 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 123                                           enum rf_content content,
 124                                           enum radio_path rfpath);
 125 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
 126 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
 127                                    enum rf_pwrstate rfpwr_state);
 128
 129 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
 130 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
 131 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
 132 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
 133 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
 134 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
 135 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
 136 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
 137 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
 138 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
 139 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
 140 void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
 141                                        unsigned long *flag);
 142 void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
 143                                        unsigned long *flag);
 144 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
 145 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
 146
 147 #endif