1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
17 #include "../rtl8192c/fw_common.h"
19 #include <linux/module.h>
21 /* macro to shorten lines */
23 #define LINK_Q ui_link_quality
24 #define RX_EVM rx_evm_percentage
25 #define RX_SIGQ rx_mimo_sig_qual
27 void rtl92c_read_chip_version(struct ieee80211_hw *hw)
29 struct rtl_priv *rtlpriv = rtl_priv(hw);
30 struct rtl_phy *rtlphy = &(rtlpriv->phy);
31 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
32 enum version_8192c chip_version = VERSION_UNKNOWN;
33 const char *versionid;
36 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
37 if (value32 & TRP_VAUX_EN) {
38 chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
39 VERSION_TEST_CHIP_88C;
41 /* Normal mass production chip. */
42 chip_version = NORMAL_CHIP;
43 chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
44 chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
45 if (IS_VENDOR_UMC(chip_version))
46 chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
47 CHIP_VENDOR_UMC_B_CUT : 0);
48 if (IS_92C_SERIAL(chip_version)) {
49 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
50 chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
51 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
54 rtlhal->version = (enum version_8192c)chip_version;
55 pr_info("Chip version 0x%x\n", chip_version);
56 switch (rtlhal->version) {
57 case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
58 versionid = "NORMAL_B_CHIP_92C";
60 case VERSION_NORMAL_TSMC_CHIP_92C:
61 versionid = "NORMAL_TSMC_CHIP_92C";
63 case VERSION_NORMAL_TSMC_CHIP_88C:
64 versionid = "NORMAL_TSMC_CHIP_88C";
66 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
67 versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT";
69 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
70 versionid = "NORMAL_UMC_CHIP_92C_A_CUT";
72 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
73 versionid = "NORMAL_UMC_CHIP_88C_A_CUT";
75 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
76 versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT";
78 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
79 versionid = "NORMAL_UMC_CHIP_92C_B_CUT";
81 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
82 versionid = "NORMAL_UMC_CHIP_88C_B_CUT";
84 case VERSION_TEST_CHIP_92C:
85 versionid = "TEST_CHIP_92C";
87 case VERSION_TEST_CHIP_88C:
88 versionid = "TEST_CHIP_88C";
91 versionid = "UNKNOWN";
94 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
95 "Chip Version ID: %s\n", versionid);
97 if (IS_92C_SERIAL(rtlhal->version))
99 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
101 rtlphy->rf_type = RF_1T1R;
102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
103 "Chip RF Type: %s\n",
104 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
105 if (get_rf_type(rtlphy) == RF_1T1R)
106 rtlpriv->dm.rfpath_rxenable[0] = true;
108 rtlpriv->dm.rfpath_rxenable[0] =
109 rtlpriv->dm.rfpath_rxenable[1] = true;
110 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
115 * writeLLT - LLT table write access
117 * @address: LLT logical address.
118 * @data: LLT data content
120 * Realtek hardware access function.
123 bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
125 struct rtl_priv *rtlpriv = rtl_priv(hw);
128 u32 value = _LLT_INIT_ADDR(address) |
129 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
131 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
133 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
134 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
136 if (count > POLLING_LLT_THRESHOLD) {
137 pr_err("Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n",
138 address, _LLT_OP_VALUE(value));
147 * rtl92c_init_LLT_table - Init LLT table
151 * Realtek hardware access function.
154 bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
159 for (i = 0; i < (boundary - 1); i++) {
160 rst = rtl92c_llt_write(hw, i , i + 1);
162 pr_err("===> %s #1 fail\n", __func__);
167 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
169 pr_err("===> %s #2 fail\n", __func__);
172 /* Make the other pages as ring buffer
173 * This ring buffer is used as beacon buffer if we config this MAC
174 * as two MAC transfer.
175 * Otherwise used as local loopback buffer.
177 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
178 rst = rtl92c_llt_write(hw, i, (i + 1));
180 pr_err("===> %s #3 fail\n", __func__);
184 /* Let last entry point to the start entry of ring buffer */
185 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
187 pr_err("===> %s #4 fail\n", __func__);
193 void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
194 u8 *p_macaddr, bool is_group, u8 enc_algo,
195 bool is_wepkey, bool clear_all)
197 struct rtl_priv *rtlpriv = rtl_priv(hw);
198 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
199 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
200 u8 *macaddr = p_macaddr;
202 bool is_pairwise = false;
203 static u8 cam_const_addr[4][6] = {
204 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
205 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
206 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
207 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
209 static u8 cam_const_broad[] = {
210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
218 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
219 for (idx = 0; idx < clear_number; idx++) {
220 rtl_cam_mark_invalid(hw, cam_offset + idx);
221 rtl_cam_empty_entry(hw, cam_offset + idx);
223 memset(rtlpriv->sec.key_buf[idx], 0,
225 rtlpriv->sec.key_len[idx] = 0;
230 case WEP40_ENCRYPTION:
231 enc_algo = CAM_WEP40;
233 case WEP104_ENCRYPTION:
234 enc_algo = CAM_WEP104;
236 case TKIP_ENCRYPTION:
239 case AESCCMP_ENCRYPTION:
243 pr_err("illegal switch case\n");
247 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
248 macaddr = cam_const_addr[key_index];
249 entry_id = key_index;
252 macaddr = cam_const_broad;
253 entry_id = key_index;
255 if (mac->opmode == NL80211_IFTYPE_AP ||
256 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
257 entry_id = rtl_cam_get_free_entry(hw,
259 if (entry_id >= TOTAL_CAM_ENTRY) {
260 pr_err("Can not find free hw security cam entry\n");
264 entry_id = CAM_PAIRWISE_KEY_POSITION;
267 key_index = PAIRWISE_KEYIDX;
271 if (rtlpriv->sec.key_len[key_index] == 0) {
272 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
273 "delete one entry\n");
274 if (mac->opmode == NL80211_IFTYPE_AP ||
275 mac->opmode == NL80211_IFTYPE_MESH_POINT)
276 rtl_cam_del_entry(hw, p_macaddr);
277 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
279 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
280 "The insert KEY length is %d\n",
281 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
282 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
283 "The insert KEY is %x %x\n",
284 rtlpriv->sec.key_buf[0][0],
285 rtlpriv->sec.key_buf[0][1]);
286 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
289 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
290 "Pairwise Key content",
291 rtlpriv->sec.pairwise_key,
293 key_len[PAIRWISE_KEYIDX]);
294 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
295 "set Pairwise key\n");
297 rtl_cam_add_one_entry(hw, macaddr, key_index,
303 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
305 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
306 rtl_cam_add_one_entry(hw,
309 CAM_PAIRWISE_KEY_POSITION,
315 rtl_cam_add_one_entry(hw, macaddr, key_index,
318 rtlpriv->sec.key_buf[entry_id]);
324 u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
326 struct rtl_priv *rtlpriv = rtl_priv(hw);
328 return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
331 void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
333 struct rtl_priv *rtlpriv = rtl_priv(hw);
334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
335 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
337 if (IS_HARDWARE_TYPE_8192CE(rtlpriv)) {
338 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
340 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
343 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
345 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
350 void rtl92c_init_interrupt(struct ieee80211_hw *hw)
352 rtl92c_enable_interrupt(hw);
355 void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
357 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
360 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
363 void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
365 struct rtl_priv *rtlpriv = rtl_priv(hw);
367 rtl92c_dm_init_edca_turbo(hw);
368 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci);
371 void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
375 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
378 int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
384 case NL80211_IFTYPE_UNSPECIFIED:
386 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
387 "Set Network type to NO LINK!\n");
389 case NL80211_IFTYPE_ADHOC:
390 value = NT_LINK_AD_HOC;
391 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
392 "Set Network type to Ad Hoc!\n");
394 case NL80211_IFTYPE_STATION:
396 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
397 "Set Network type to STA!\n");
399 case NL80211_IFTYPE_AP:
401 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
402 "Set Network type to AP!\n");
405 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
406 "Network type %d not supported!\n", type);
409 rtl_write_byte(rtlpriv, MSR, value);
413 void rtl92c_init_network_type(struct ieee80211_hw *hw)
415 rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
418 void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
422 struct rtl_priv *rtlpriv = rtl_priv(hw);
424 /* Response Rate Set */
425 value32 = rtl_read_dword(rtlpriv, REG_RRSR);
426 value32 &= ~RATE_BITMAP_ALL;
427 value32 |= RATE_RRSR_CCK_ONLY_1M;
428 rtl_write_dword(rtlpriv, REG_RRSR, value32);
429 /* SIFS (used in NAV) */
430 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
431 rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
433 value16 = _LRL(0x30) | _SRL(0x30);
434 rtl_write_dword(rtlpriv, REG_RL, value16);
437 void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
441 /* Set Data Auto Rate Fallback Retry Count register. */
442 rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);
443 rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404);
444 rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);
445 rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605);
448 static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
451 struct rtl_priv *rtlpriv = rtl_priv(hw);
453 rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
454 rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
457 static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
460 struct rtl_priv *rtlpriv = rtl_priv(hw);
462 rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
463 rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
466 void rtl92c_init_edca_param(struct ieee80211_hw *hw,
467 u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
469 /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
470 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 value |= ((u32)cw_min & 0xF) << 8;
477 value |= ((u32)cw_max & 0xF) << 12;
478 value |= (u32)txop << 16;
479 /* 92C hardware register sequence is the same as queue number. */
480 rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
483 void rtl92c_init_edca(struct ieee80211_hw *hw)
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
488 /* disable EDCCA count down, to reduce collison and retry */
489 value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
490 value16 |= DIS_EDCA_CNT_DWN;
491 rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
492 /* Update SIFS timing. ??????????
493 * pHalData->SifsTime = 0x0e0e0a0a; */
494 rtl92c_set_cck_sifs(hw, 0xa, 0xa);
495 rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
496 /* Set CCK/OFDM SIFS to be 10us. */
497 rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
498 rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
499 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
500 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
502 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
503 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
504 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
505 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
507 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
508 /* AGGR BREAK TIME Register */
509 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
510 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
511 rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
512 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
515 void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
517 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
520 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
521 /* init AMPDU aggregation number, tuning for Tx's TP, */
522 rtl_write_word(rtlpriv, 0x4CA, 0x0708);
525 void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw)
527 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
532 void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
534 struct rtl_priv *rtlpriv = rtl_priv(hw);
536 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
537 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
538 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
541 void rtl92c_init_retry_function(struct ieee80211_hw *hw)
544 struct rtl_priv *rtlpriv = rtl_priv(hw);
546 value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
547 value8 |= EN_AMPDU_RTY_NEW;
548 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
549 /* Set ACK timeout */
550 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
553 void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
560 void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
562 struct rtl_priv *rtlpriv = rtl_priv(hw);
563 u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
565 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
568 /*==============================================================*/
570 static u8 _rtl92c_query_rxpwrpercentage(s8 antpower)
572 if ((antpower <= -100) || (antpower >= 20))
574 else if (antpower >= 0)
577 return 100 + antpower;
580 static u8 _rtl92c_evm_db_to_percentage(s8 value)
589 ret_val = 0 - ret_val;
596 static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw,
601 if (currsig >= 61 && currsig <= 100)
602 retsig = 90 + ((currsig - 60) / 4);
603 else if (currsig >= 41 && currsig <= 60)
604 retsig = 78 + ((currsig - 40) / 2);
605 else if (currsig >= 31 && currsig <= 40)
606 retsig = 66 + (currsig - 30);
607 else if (currsig >= 21 && currsig <= 30)
608 retsig = 54 + (currsig - 20);
609 else if (currsig >= 5 && currsig <= 20)
610 retsig = 42 + (((currsig - 5) * 2) / 3);
611 else if (currsig == 4)
613 else if (currsig == 3)
615 else if (currsig == 2)
617 else if (currsig == 1)
624 static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
625 struct rtl_stats *pstats,
626 struct rx_desc_92c *p_desc,
627 struct rx_fwinfo_92c *p_drvinfo,
628 bool packet_match_bssid,
632 struct rtl_priv *rtlpriv = rtl_priv(hw);
633 struct rtl_phy *rtlphy = &(rtlpriv->phy);
634 struct phy_sts_cck_8192s_t *cck_buf;
635 s8 rx_pwr_all = 0, rx_pwr[4];
636 u8 rf_rx_num = 0, evm, pwdb_all;
637 u8 i, max_spatial_stream;
638 u32 rssi, total_rssi = 0;
639 bool in_powersavemode = false;
641 u8 *pdesc = (u8 *)p_desc;
643 is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs);
644 pstats->packet_matchbssid = packet_match_bssid;
645 pstats->packet_toself = packet_toself;
646 pstats->packet_beacon = packet_beacon;
647 pstats->is_cck = is_cck_rate;
648 pstats->RX_SIGQ[0] = -1;
649 pstats->RX_SIGQ[1] = -1;
651 u8 report, cck_highpwr;
653 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
654 if (!in_powersavemode)
655 cck_highpwr = rtlphy->cck_high_power;
659 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
661 report = cck_buf->cck_agc_rpt & 0xc0;
662 report = report >> 6;
665 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
668 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
671 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
674 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
678 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
680 report = p_drvinfo->cfosho[0] & 0x60;
681 report = report >> 5;
684 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
687 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
690 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
693 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
697 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
698 pstats->rx_pwdb_all = pwdb_all;
699 pstats->recvsignalpower = rx_pwr_all;
700 if (packet_match_bssid) {
703 if (pstats->rx_pwdb_all > 40)
706 sq = cck_buf->sq_rpt;
712 sq = ((64 - sq) * 100) / 44;
714 pstats->signalquality = sq;
715 pstats->RX_SIGQ[0] = sq;
716 pstats->RX_SIGQ[1] = -1;
719 rtlpriv->dm.rfpath_rxenable[0] =
720 rtlpriv->dm.rfpath_rxenable[1] = true;
721 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
722 if (rtlpriv->dm.rfpath_rxenable[i])
725 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
726 rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
728 rtlpriv->stats.rx_snr_db[i] =
729 (long)(p_drvinfo->rxsnr[i] / 2);
731 if (packet_match_bssid)
732 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
734 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
735 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
736 pstats->rx_pwdb_all = pwdb_all;
737 pstats->rxpower = rx_pwr_all;
738 pstats->recvsignalpower = rx_pwr_all;
739 if (GET_RX_DESC_RX_MCS(pdesc) &&
740 GET_RX_DESC_RX_MCS(pdesc) >= DESC_RATEMCS8 &&
741 GET_RX_DESC_RX_MCS(pdesc) <= DESC_RATEMCS15)
742 max_spatial_stream = 2;
744 max_spatial_stream = 1;
745 for (i = 0; i < max_spatial_stream; i++) {
746 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
747 if (packet_match_bssid) {
749 pstats->signalquality =
757 pstats->signalstrength =
758 (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all));
759 else if (rf_rx_num != 0)
760 pstats->signalstrength =
761 (u8) (_rtl92c_signal_scale_mapping
762 (hw, total_rssi /= rf_rx_num));
765 void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
767 struct rtl_stats *pstats,
768 struct rx_desc_92c *pdesc,
769 struct rx_fwinfo_92c *p_drvinfo)
771 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
772 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
773 struct ieee80211_hdr *hdr;
778 bool packet_matchbssid, packet_toself, packet_beacon = false;
780 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
781 hdr = (struct ieee80211_hdr *)tmp_buf;
782 fc = hdr->frame_control;
783 cpu_fc = le16_to_cpu(fc);
784 type = WLAN_FC_GET_TYPE(fc);
787 ((IEEE80211_FTYPE_CTL != type) &&
788 ether_addr_equal(mac->bssid,
789 (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
790 (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
792 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
794 packet_toself = packet_matchbssid &&
795 ether_addr_equal(praddr, rtlefuse->dev_addr);
796 if (ieee80211_is_beacon(fc))
797 packet_beacon = true;
798 _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
799 packet_matchbssid, packet_toself,
801 rtl_process_phyinfo(hw, tmp_buf, pstats);