1 /* @file mwifiex_pcie.h
3 * @brief This file contains definitions for PCI-E interface.
6 * Copyright (C) 2011, Marvell International Ltd.
8 * This software file (the "File") is distributed by Marvell International
9 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
10 * (the "License"). You may use, redistribute and/or modify this File in
11 * accordance with the terms and conditions of the License, a copy of which
12 * is available by writing to the Free Software Foundation, Inc.,
13 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
14 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
16 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
18 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
19 * this warranty disclaimer.
22 #ifndef _MWIFIEX_PCIE_H
23 #define _MWIFIEX_PCIE_H
25 #include <linux/pci.h>
26 #include <linux/pcieport_if.h>
27 #include <linux/interrupt.h>
31 #define PCIE8766_DEFAULT_FW_NAME "/*(DEBLOBBED)*/"
32 #define PCIE8897_DEFAULT_FW_NAME "/*(DEBLOBBED)*/"
34 #define PCIE_VENDOR_ID_MARVELL (0x11ab)
35 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
36 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
38 /* Constants for Buffer Descriptor (BD) rings */
39 #define MWIFIEX_MAX_TXRX_BD 0x20
40 #define MWIFIEX_TXBD_MASK 0x3F
41 #define MWIFIEX_RXBD_MASK 0x3F
43 #define MWIFIEX_MAX_EVT_BD 0x04
44 #define MWIFIEX_EVTBD_MASK 0x07
46 /* PCIE INTERNAL REGISTERS */
47 #define PCIE_SCRATCH_0_REG 0xC10
48 #define PCIE_SCRATCH_1_REG 0xC14
49 #define PCIE_CPU_INT_EVENT 0xC18
50 #define PCIE_CPU_INT_STATUS 0xC1C
51 #define PCIE_HOST_INT_STATUS 0xC30
52 #define PCIE_HOST_INT_MASK 0xC34
53 #define PCIE_HOST_INT_STATUS_MASK 0xC3C
54 #define PCIE_SCRATCH_2_REG 0xC40
55 #define PCIE_SCRATCH_3_REG 0xC44
56 #define PCIE_SCRATCH_4_REG 0xCD0
57 #define PCIE_SCRATCH_5_REG 0xCD4
58 #define PCIE_SCRATCH_6_REG 0xCD8
59 #define PCIE_SCRATCH_7_REG 0xCDC
60 #define PCIE_SCRATCH_8_REG 0xCE0
61 #define PCIE_SCRATCH_9_REG 0xCE4
62 #define PCIE_SCRATCH_10_REG 0xCE8
63 #define PCIE_SCRATCH_11_REG 0xCEC
64 #define PCIE_SCRATCH_12_REG 0xCF0
65 #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
66 #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
68 #define CPU_INTR_DNLD_RDY BIT(0)
69 #define CPU_INTR_DOOR_BELL BIT(1)
70 #define CPU_INTR_SLEEP_CFM_DONE BIT(2)
71 #define CPU_INTR_RESET BIT(3)
73 #define HOST_INTR_DNLD_DONE BIT(0)
74 #define HOST_INTR_UPLD_RDY BIT(1)
75 #define HOST_INTR_CMD_DONE BIT(2)
76 #define HOST_INTR_EVENT_RDY BIT(3)
77 #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \
78 HOST_INTR_UPLD_RDY | \
79 HOST_INTR_CMD_DONE | \
82 #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
83 #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
84 #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
85 #define MWIFIEX_BD_FLAG_SOP BIT(0)
86 #define MWIFIEX_BD_FLAG_EOP BIT(1)
87 #define MWIFIEX_BD_FLAG_XS_SOP BIT(2)
88 #define MWIFIEX_BD_FLAG_XS_EOP BIT(3)
89 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7)
90 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10)
91 #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16)
92 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26)
94 /* Max retry number of command write */
95 #define MAX_WRITE_IOMEM_RETRY 2
96 /* Define PCIE block size for firmware download */
97 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
98 /* FW awake cookie after FW ready */
99 #define FW_AWAKE_COOKIE (0xAA55AA55)
100 #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF
101 #define MWIFIEX_MAX_DELAY_COUNT 5
103 struct mwifiex_pcie_card_reg {
124 u32 evt_rollover_ind;
129 u32 ring_tx_start_ptr;
134 static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
135 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
136 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
137 .cmd_size = PCIE_SCRATCH_2_REG,
138 .fw_status = PCIE_SCRATCH_3_REG,
139 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
140 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
141 .tx_rdptr = PCIE_SCRATCH_6_REG,
142 .tx_wrptr = PCIE_SCRATCH_7_REG,
143 .rx_rdptr = PCIE_SCRATCH_8_REG,
144 .rx_wrptr = PCIE_SCRATCH_9_REG,
145 .evt_rdptr = PCIE_SCRATCH_10_REG,
146 .evt_wrptr = PCIE_SCRATCH_11_REG,
147 .drv_rdy = PCIE_SCRATCH_12_REG,
149 .tx_mask = MWIFIEX_TXBD_MASK,
151 .rx_mask = MWIFIEX_RXBD_MASK,
153 .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
154 .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
155 .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
158 .ring_flag_xs_sop = 0,
159 .ring_flag_xs_eop = 0,
160 .ring_tx_start_ptr = 0,
165 static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
166 .cmd_addr_lo = PCIE_SCRATCH_0_REG,
167 .cmd_addr_hi = PCIE_SCRATCH_1_REG,
168 .cmd_size = PCIE_SCRATCH_2_REG,
169 .fw_status = PCIE_SCRATCH_3_REG,
170 .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
171 .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
172 .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
173 .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
174 .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
175 .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
176 .evt_rdptr = PCIE_SCRATCH_10_REG,
177 .evt_wrptr = PCIE_SCRATCH_11_REG,
178 .drv_rdy = PCIE_SCRATCH_12_REG,
180 .tx_mask = 0x03FF0000,
181 .tx_wrap_mask = 0x07FF0000,
182 .rx_mask = 0x000003FF,
183 .rx_wrap_mask = 0x000007FF,
184 .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
185 .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
186 .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
187 .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
188 .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
189 .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
190 .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
191 .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
196 struct mwifiex_pcie_device {
197 const char *firmware;
198 const struct mwifiex_pcie_card_reg *reg;
203 static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
204 .firmware = PCIE8766_DEFAULT_FW_NAME,
205 .reg = &mwifiex_reg_8766,
206 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
207 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
210 static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
211 .firmware = PCIE8897_DEFAULT_FW_NAME,
212 .reg = &mwifiex_reg_8897,
213 .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
214 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
217 struct mwifiex_evt_buf_desc {
223 struct mwifiex_pcie_buf_desc {
229 struct mwifiex_pfu_buf_desc {
238 struct pcie_service_card {
240 struct mwifiex_adapter *adapter;
241 struct mwifiex_pcie_device pcie;
248 dma_addr_t txbd_ring_pbase;
249 void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
250 struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
256 dma_addr_t rxbd_ring_pbase;
257 void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
258 struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
263 u8 *evtbd_ring_vbase;
264 dma_addr_t evtbd_ring_pbase;
265 void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
266 struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
268 struct sk_buff *cmd_buf;
269 struct sk_buff *cmdrsp_buf;
270 u8 *sleep_cookie_vbase;
271 dma_addr_t sleep_cookie_pbase;
272 void __iomem *pci_mmap;
273 void __iomem *pci_mmap1;
277 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
279 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
281 switch (card->dev->device) {
282 case PCIE_DEVICE_ID_MARVELL_88W8766P:
283 if (((card->txbd_wrptr & reg->tx_mask) ==
284 (rdptr & reg->tx_mask)) &&
285 ((card->txbd_wrptr & reg->tx_rollover_ind) !=
286 (rdptr & reg->tx_rollover_ind)))
289 case PCIE_DEVICE_ID_MARVELL_88W8897:
290 if (((card->txbd_wrptr & reg->tx_mask) ==
291 (rdptr & reg->tx_mask)) &&
292 ((card->txbd_wrptr & reg->tx_rollover_ind) ==
293 (rdptr & reg->tx_rollover_ind)))
302 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
304 const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
306 switch (card->dev->device) {
307 case PCIE_DEVICE_ID_MARVELL_88W8766P:
308 if (((card->txbd_wrptr & reg->tx_mask) !=
309 (card->txbd_rdptr & reg->tx_mask)) ||
310 ((card->txbd_wrptr & reg->tx_rollover_ind) !=
311 (card->txbd_rdptr & reg->tx_rollover_ind)))
314 case PCIE_DEVICE_ID_MARVELL_88W8897:
315 if (((card->txbd_wrptr & reg->tx_mask) !=
316 (card->txbd_rdptr & reg->tx_mask)) ||
317 ((card->txbd_wrptr & reg->tx_rollover_ind) ==
318 (card->txbd_rdptr & reg->tx_rollover_ind)))
325 #endif /* _MWIFIEX_PCIE_H */