2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004-2011 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
21 #include <asm/errno.h>
22 #include <asm/processor.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
37 static RTXBD rtx __attribute__ ((aligned(8)));
39 #error "rtx must be 64-bit aligned"
42 static int tsec_send(struct eth_device *dev, void *packet, int length);
44 /* Default initializations for TSEC controllers. */
46 static struct tsec_info_struct tsec_info[] = {
48 STD_TSEC_INFO(1), /* TSEC1 */
51 STD_TSEC_INFO(2), /* TSEC2 */
53 #ifdef CONFIG_MPC85XX_FEC
55 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
56 .devname = CONFIG_MPC85XX_FEC_NAME,
57 .phyaddr = FEC_PHY_ADDR,
59 .mii_devname = DEFAULT_MII_NAME
63 STD_TSEC_INFO(3), /* TSEC3 */
66 STD_TSEC_INFO(4), /* TSEC4 */
70 #define TBIANA_SETTINGS ( \
71 TBIANA_ASYMMETRIC_PAUSE \
72 | TBIANA_SYMMETRIC_PAUSE \
73 | TBIANA_FULL_DUPLEX \
76 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
77 #ifndef CONFIG_TSEC_TBICR_SETTINGS
78 #define CONFIG_TSEC_TBICR_SETTINGS ( \
84 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
86 /* Configure the TBI for SGMII operation */
87 static void tsec_configure_serdes(struct tsec_private *priv)
89 /* Access TBI PHY registers at given TSEC register offset as opposed
90 * to the register offset used for external PHY accesses */
91 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
92 0, TBI_ANA, TBIANA_SETTINGS);
93 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
94 0, TBI_TBICON, TBICON_CLK_SELECT);
95 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
96 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
99 #ifdef CONFIG_MCAST_TFTP
101 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
103 /* Set the appropriate hash bit for the given addr */
105 /* The algorithm works like so:
106 * 1) Take the Destination Address (ie the multicast address), and
107 * do a CRC on it (little endian), and reverse the bits of the
109 * 2) Use the 8 most significant bits as a hash into a 256-entry
110 * table. The table is controlled through 8 32-bit registers:
111 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
112 * 255. This means that the 3 most significant bits in the
113 * hash index which gaddr register to use, and the 5 other bits
114 * indicate which bit (assuming an IBM numbering scheme, which
115 * for PowerPC (tm) is usually the case) in the register holds
118 tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
120 struct tsec_private *priv = (struct tsec_private *)dev->priv;
121 struct tsec __iomem *regs = priv->regs;
123 u8 whichbit, whichreg;
125 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
126 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
127 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
129 value = 1 << (31-whichbit);
132 setbits_be32(®s->hash.gaddr0 + whichreg, value);
134 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
138 #endif /* Multicast TFTP ? */
140 /* Initialized required registers to appropriate values, zeroing
141 * those we don't care about (unless zero is bad, in which case,
142 * choose a more appropriate value)
144 static void init_registers(tsec_t *regs)
147 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
149 out_be32(®s->imask, IMASK_INIT_CLEAR);
151 out_be32(®s->hash.iaddr0, 0);
152 out_be32(®s->hash.iaddr1, 0);
153 out_be32(®s->hash.iaddr2, 0);
154 out_be32(®s->hash.iaddr3, 0);
155 out_be32(®s->hash.iaddr4, 0);
156 out_be32(®s->hash.iaddr5, 0);
157 out_be32(®s->hash.iaddr6, 0);
158 out_be32(®s->hash.iaddr7, 0);
160 out_be32(®s->hash.gaddr0, 0);
161 out_be32(®s->hash.gaddr1, 0);
162 out_be32(®s->hash.gaddr2, 0);
163 out_be32(®s->hash.gaddr3, 0);
164 out_be32(®s->hash.gaddr4, 0);
165 out_be32(®s->hash.gaddr5, 0);
166 out_be32(®s->hash.gaddr6, 0);
167 out_be32(®s->hash.gaddr7, 0);
169 out_be32(®s->rctrl, 0x00000000);
171 /* Init RMON mib registers */
172 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
174 out_be32(®s->rmon.cam1, 0xffffffff);
175 out_be32(®s->rmon.cam2, 0xffffffff);
177 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
179 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
181 out_be32(®s->attr, ATTR_INIT_SETTINGS);
182 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
186 /* Configure maccfg2 based on negotiated speed and duplex
187 * reported by PHY handling code
189 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
191 tsec_t *regs = priv->regs;
195 printf("%s: No link.\n", phydev->dev->name);
199 /* clear all bits relative with interface mode */
200 ecntrl = in_be32(®s->ecntrl);
201 ecntrl &= ~ECNTRL_R100;
203 maccfg2 = in_be32(®s->maccfg2);
204 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
207 maccfg2 |= MACCFG2_FULL_DUPLEX;
209 switch (phydev->speed) {
211 maccfg2 |= MACCFG2_GMII;
215 maccfg2 |= MACCFG2_MII;
217 /* Set R100 bit in all modes although
218 * it is only used in RGMII mode
220 if (phydev->speed == 100)
221 ecntrl |= ECNTRL_R100;
224 printf("%s: Speed was bad\n", phydev->dev->name);
228 out_be32(®s->ecntrl, ecntrl);
229 out_be32(®s->maccfg2, maccfg2);
231 printf("Speed: %d, %s duplex%s\n", phydev->speed,
232 (phydev->duplex) ? "full" : "half",
233 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
236 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
238 * When MACCFG1[Rx_EN] is enabled during system boot as part
239 * of the eTSEC port initialization sequence,
240 * the eTSEC Rx logic may not be properly initialized.
242 void redundant_init(struct eth_device *dev)
244 struct tsec_private *priv = dev->priv;
245 tsec_t *regs = priv->regs;
248 static const u8 pkt[] = {
249 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
250 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
251 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
252 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
253 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
254 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
255 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
256 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
257 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
258 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
259 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
260 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
261 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
264 /* Enable promiscuous mode */
265 setbits_be32(®s->rctrl, 0x8);
266 /* Enable loopback mode */
267 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
268 /* Enable transmit and receive */
269 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
271 /* Tell the DMA it is clear to go */
272 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
273 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
274 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
275 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
278 tsec_send(dev, (void *)pkt, sizeof(pkt));
280 /* Wait for buffer to be received */
281 for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
282 if (t >= 10 * TOUT_LOOP) {
283 printf("%s: tsec: rx error\n", dev->name);
288 if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
291 rtx.rxbd[rxIdx].length = 0;
292 rtx.rxbd[rxIdx].status =
293 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
294 rxIdx = (rxIdx + 1) % PKTBUFSRX;
296 if (in_be32(®s->ievent) & IEVENT_BSY) {
297 out_be32(®s->ievent, IEVENT_BSY);
298 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
301 printf("loopback recv packet error!\n");
302 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
304 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
306 } while ((count++ < 4) && (fail == 1));
309 panic("eTSEC init fail!\n");
310 /* Disable promiscuous mode */
311 clrbits_be32(®s->rctrl, 0x8);
312 /* Disable loopback mode */
313 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
317 /* Set up the buffers and their descriptors, and bring up the
320 static void startup_tsec(struct eth_device *dev)
323 struct tsec_private *priv = (struct tsec_private *)dev->priv;
324 tsec_t *regs = priv->regs;
326 /* reset the indices to zero */
329 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
333 /* Point to the buffer descriptors */
334 out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
335 out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
337 /* Initialize the Rx Buffer descriptors */
338 for (i = 0; i < PKTBUFSRX; i++) {
339 rtx.rxbd[i].status = RXBD_EMPTY;
340 rtx.rxbd[i].length = 0;
341 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
343 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
345 /* Initialize the TX Buffer Descriptors */
346 for (i = 0; i < TX_BUF_CNT; i++) {
347 rtx.txbd[i].status = 0;
348 rtx.txbd[i].length = 0;
349 rtx.txbd[i].bufPtr = 0;
351 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
353 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
355 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
358 /* Enable Transmit and Receive */
359 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
361 /* Tell the DMA it is clear to go */
362 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
363 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
364 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
365 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
368 /* This returns the status bits of the device. The return value
369 * is never checked, and this is what the 8260 driver did, so we
370 * do the same. Presumably, this would be zero if there were no
373 static int tsec_send(struct eth_device *dev, void *packet, int length)
377 struct tsec_private *priv = (struct tsec_private *)dev->priv;
378 tsec_t *regs = priv->regs;
380 /* Find an empty buffer descriptor */
381 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
382 if (i >= TOUT_LOOP) {
383 debug("%s: tsec: tx buffers full\n", dev->name);
388 rtx.txbd[txIdx].bufPtr = (uint) packet;
389 rtx.txbd[txIdx].length = length;
390 rtx.txbd[txIdx].status |=
391 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
393 /* Tell the DMA to go */
394 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
396 /* Wait for buffer to be transmitted */
397 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
398 if (i >= TOUT_LOOP) {
399 debug("%s: tsec: tx error\n", dev->name);
404 txIdx = (txIdx + 1) % TX_BUF_CNT;
405 result = rtx.txbd[txIdx].status & TXBD_STATS;
410 static int tsec_recv(struct eth_device *dev)
413 struct tsec_private *priv = (struct tsec_private *)dev->priv;
414 tsec_t *regs = priv->regs;
416 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
418 length = rtx.rxbd[rxIdx].length;
420 /* Send the packet up if there were no errors */
421 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
422 NetReceive(NetRxPackets[rxIdx], length - 4);
424 printf("Got error %x\n",
425 (rtx.rxbd[rxIdx].status & RXBD_STATS));
428 rtx.rxbd[rxIdx].length = 0;
430 /* Set the wrap bit if this is the last element in the list */
431 rtx.rxbd[rxIdx].status =
432 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
434 rxIdx = (rxIdx + 1) % PKTBUFSRX;
437 if (in_be32(®s->ievent) & IEVENT_BSY) {
438 out_be32(®s->ievent, IEVENT_BSY);
439 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
446 /* Stop the interface */
447 static void tsec_halt(struct eth_device *dev)
449 struct tsec_private *priv = (struct tsec_private *)dev->priv;
450 tsec_t *regs = priv->regs;
452 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
453 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
455 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
456 != (IEVENT_GRSC | IEVENT_GTSC))
459 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
461 /* Shut down the PHY, as needed */
462 phy_shutdown(priv->phydev);
465 /* Initializes data structures and registers for the controller,
466 * and brings the interface up. Returns the link status, meaning
467 * that it returns success if the link is up, failure otherwise.
468 * This allows u-boot to find the first active controller.
470 static int tsec_init(struct eth_device *dev, bd_t * bd)
473 char tmpbuf[MAC_ADDR_LEN];
475 struct tsec_private *priv = (struct tsec_private *)dev->priv;
476 tsec_t *regs = priv->regs;
479 /* Make sure the controller is stopped */
482 /* Init MACCFG2. Defaults to GMII */
483 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
486 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
488 /* Copy the station address into the address registers.
489 * Backwards, because little endian MACS are dumb */
490 for (i = 0; i < MAC_ADDR_LEN; i++)
491 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
493 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
496 out_be32(®s->macstnaddr1, tempval);
498 tempval = *((uint *) (tmpbuf + 4));
500 out_be32(®s->macstnaddr2, tempval);
502 /* Clear out (for the most part) the other registers */
503 init_registers(regs);
505 /* Ready the device for tx/rx */
508 /* Start up the PHY */
509 ret = phy_startup(priv->phydev);
511 printf("Could not initialize PHY %s\n",
512 priv->phydev->dev->name);
516 adjust_link(priv, priv->phydev);
518 /* If there's no link, fail */
519 return priv->phydev->link ? 0 : -1;
522 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
524 tsec_t *regs = priv->regs;
527 ecntrl = in_be32(®s->ecntrl);
529 if (ecntrl & ECNTRL_SGMII_MODE)
530 return PHY_INTERFACE_MODE_SGMII;
532 if (ecntrl & ECNTRL_TBI_MODE) {
533 if (ecntrl & ECNTRL_REDUCED_MODE)
534 return PHY_INTERFACE_MODE_RTBI;
536 return PHY_INTERFACE_MODE_TBI;
539 if (ecntrl & ECNTRL_REDUCED_MODE) {
540 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
541 return PHY_INTERFACE_MODE_RMII;
543 phy_interface_t interface = priv->interface;
546 * This isn't autodetected, so it must
547 * be set by the platform code.
549 if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
550 (interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
551 (interface == PHY_INTERFACE_MODE_RGMII_RXID))
554 return PHY_INTERFACE_MODE_RGMII;
558 if (priv->flags & TSEC_GIGABIT)
559 return PHY_INTERFACE_MODE_GMII;
561 return PHY_INTERFACE_MODE_MII;
565 /* Discover which PHY is attached to the device, and configure it
566 * properly. If the PHY is not recognized, then return 0
567 * (failure). Otherwise, return 1
569 static int init_phy(struct eth_device *dev)
571 struct tsec_private *priv = (struct tsec_private *)dev->priv;
572 struct phy_device *phydev;
573 tsec_t *regs = priv->regs;
574 u32 supported = (SUPPORTED_10baseT_Half |
575 SUPPORTED_10baseT_Full |
576 SUPPORTED_100baseT_Half |
577 SUPPORTED_100baseT_Full);
579 if (priv->flags & TSEC_GIGABIT)
580 supported |= SUPPORTED_1000baseT_Full;
582 /* Assign a Physical address to the TBI */
583 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
585 priv->interface = tsec_get_interface(priv);
587 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
588 tsec_configure_serdes(priv);
590 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
592 phydev->supported &= supported;
593 phydev->advertising = phydev->supported;
595 priv->phydev = phydev;
602 /* Initialize device structure. Returns success if PHY
603 * initialization succeeded (i.e. if it recognizes the PHY)
605 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
607 struct eth_device *dev;
609 struct tsec_private *priv;
611 dev = (struct eth_device *)malloc(sizeof *dev);
616 memset(dev, 0, sizeof *dev);
618 priv = (struct tsec_private *)malloc(sizeof(*priv));
623 priv->regs = tsec_info->regs;
624 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
626 priv->phyaddr = tsec_info->phyaddr;
627 priv->flags = tsec_info->flags;
629 sprintf(dev->name, tsec_info->devname);
630 priv->interface = tsec_info->interface;
631 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
634 dev->init = tsec_init;
635 dev->halt = tsec_halt;
636 dev->send = tsec_send;
637 dev->recv = tsec_recv;
638 #ifdef CONFIG_MCAST_TFTP
639 dev->mcast = tsec_mcast_addr;
642 /* Tell u-boot to get the addr from the env */
643 for (i = 0; i < 6; i++)
644 dev->enetaddr[i] = 0;
649 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
650 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
651 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
653 /* Try to initialize PHY here, and return */
654 return init_phy(dev);
658 * Initialize all the TSEC devices
660 * Returns the number of TSEC devices that were initialized
662 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
667 for (i = 0; i < num; i++) {
668 ret = tsec_initialize(bis, &tsecs[i]);
676 int tsec_standard_init(bd_t *bis)
678 struct fsl_pq_mdio_info info;
680 info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
681 info.name = DEFAULT_MII_NAME;
683 fsl_pq_mdio_init(bis, &info);
685 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));