2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004-2011 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #include <asm/errno.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 #define MAXCONTROLLERS (8)
38 static struct tsec_private *privlist[MAXCONTROLLERS];
39 static int num_tsecs = 0;
42 static RTXBD rtx __attribute__ ((aligned(8)));
44 #error "rtx must be 64-bit aligned"
47 static int tsec_send(struct eth_device *dev,
48 volatile void *packet, int length);
49 static int tsec_recv(struct eth_device *dev);
50 static int tsec_init(struct eth_device *dev, bd_t * bd);
51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
52 static void tsec_halt(struct eth_device *dev);
53 static void init_registers(tsec_t *regs);
54 static void startup_tsec(struct eth_device *dev);
55 static int init_phy(struct eth_device *dev);
56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
57 uint read_phy_reg(struct tsec_private *priv, uint regnum);
58 static struct phy_info *get_phy_info(struct eth_device *dev);
59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
60 static void adjust_link(struct eth_device *dev);
61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
62 && !defined(BITBANGMII)
63 static int tsec_miiphy_write(const char *devname, unsigned char addr,
64 unsigned char reg, unsigned short value);
65 static int tsec_miiphy_read(const char *devname, unsigned char addr,
66 unsigned char reg, unsigned short *value);
68 #ifdef CONFIG_MCAST_TFTP
69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
72 /* Default initializations for TSEC controllers. */
74 static struct tsec_info_struct tsec_info[] = {
76 STD_TSEC_INFO(1), /* TSEC1 */
79 STD_TSEC_INFO(2), /* TSEC2 */
81 #ifdef CONFIG_MPC85XX_FEC
83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
85 .devname = CONFIG_MPC85XX_FEC_NAME,
86 .phyaddr = FEC_PHY_ADDR,
91 STD_TSEC_INFO(3), /* TSEC3 */
94 STD_TSEC_INFO(4), /* TSEC4 */
99 * Initialize all the TSEC devices
101 * Returns the number of TSEC devices that were initialized
103 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
108 for (i = 0; i < num; i++) {
109 ret = tsec_initialize(bis, &tsecs[i]);
117 int tsec_standard_init(bd_t *bis)
119 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
122 /* Initialize device structure. Returns success if PHY
123 * initialization succeeded (i.e. if it recognizes the PHY)
125 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
127 struct eth_device *dev;
129 struct tsec_private *priv;
131 dev = (struct eth_device *)malloc(sizeof *dev);
136 memset(dev, 0, sizeof *dev);
138 priv = (struct tsec_private *)malloc(sizeof(*priv));
143 privlist[num_tsecs++] = priv;
144 priv->regs = tsec_info->regs;
145 priv->phyregs = tsec_info->miiregs;
146 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
148 priv->phyaddr = tsec_info->phyaddr;
149 priv->flags = tsec_info->flags;
151 sprintf(dev->name, tsec_info->devname);
154 dev->init = tsec_init;
155 dev->halt = tsec_halt;
156 dev->send = tsec_send;
157 dev->recv = tsec_recv;
158 #ifdef CONFIG_MCAST_TFTP
159 dev->mcast = tsec_mcast_addr;
162 /* Tell u-boot to get the addr from the env */
163 for (i = 0; i < 6; i++)
164 dev->enetaddr[i] = 0;
169 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
170 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
171 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
173 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
174 && !defined(BITBANGMII)
175 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
178 /* Try to initialize PHY here, and return */
179 return init_phy(dev);
182 /* Initializes data structures and registers for the controller,
183 * and brings the interface up. Returns the link status, meaning
184 * that it returns success if the link is up, failure otherwise.
185 * This allows u-boot to find the first active controller.
187 static int tsec_init(struct eth_device *dev, bd_t * bd)
190 char tmpbuf[MAC_ADDR_LEN];
192 struct tsec_private *priv = (struct tsec_private *)dev->priv;
193 tsec_t *regs = priv->regs;
195 /* Make sure the controller is stopped */
198 /* Init MACCFG2. Defaults to GMII */
199 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
202 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
204 /* Copy the station address into the address registers.
205 * Backwards, because little endian MACS are dumb */
206 for (i = 0; i < MAC_ADDR_LEN; i++) {
207 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
209 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
212 out_be32(®s->macstnaddr1, tempval);
214 tempval = *((uint *) (tmpbuf + 4));
216 out_be32(®s->macstnaddr2, tempval);
218 /* reset the indices to zero */
222 /* Clear out (for the most part) the other registers */
223 init_registers(regs);
225 /* Ready the device for tx/rx */
228 /* If there's no link, fail */
229 return (priv->link ? 0 : -1);
232 /* Writes the given phy's reg with value, using the specified MDIO regs */
233 static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
234 uint reg, uint value)
236 int timeout = 1000000;
238 out_be32(&phyregs->miimadd, (addr << 8) | reg);
239 out_be32(&phyregs->miimcon, value);
242 while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
247 /* Provide the default behavior of writing the PHY of this ethernet device */
248 #define write_phy_reg(priv, regnum, value) \
249 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
251 /* Reads register regnum on the device's PHY through the
252 * specified registers. It lowers and raises the read
253 * command, and waits for the data to become valid (miimind
254 * notvalid bit cleared), and the bus to cease activity (miimind
255 * busy bit cleared), and then returns the value
257 static uint tsec_local_mdio_read(tsec_mdio_t *phyregs, uint phyid, uint regnum)
261 /* Put the address of the phy, and the register
262 * number into MIIMADD */
263 out_be32(&phyregs->miimadd, (phyid << 8) | regnum);
265 /* Clear the command register, and wait */
266 out_be32(&phyregs->miimcom, 0);
268 /* Initiate a read command, and wait */
269 out_be32(&phyregs->miimcom, MIIM_READ_COMMAND);
271 /* Wait for the the indication that the read is done */
272 while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY)))
275 /* Grab the value read from the PHY */
276 value = in_be32(&phyregs->miimstat);
281 /* #define to provide old read_phy_reg functionality without duplicating code */
282 #define read_phy_reg(priv,regnum) \
283 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
285 #define TBIANA_SETTINGS ( \
286 TBIANA_ASYMMETRIC_PAUSE \
287 | TBIANA_SYMMETRIC_PAUSE \
288 | TBIANA_FULL_DUPLEX \
291 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
292 #ifndef CONFIG_TSEC_TBICR_SETTINGS
293 #define CONFIG_TSEC_TBICR_SETTINGS ( \
295 | TBICR_ANEG_ENABLE \
296 | TBICR_FULL_DUPLEX \
299 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
301 /* Configure the TBI for SGMII operation */
302 static void tsec_configure_serdes(struct tsec_private *priv)
304 /* Access TBI PHY registers at given TSEC register offset as opposed
305 * to the register offset used for external PHY accesses */
306 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
308 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
310 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
311 CONFIG_TSEC_TBICR_SETTINGS);
314 /* Discover which PHY is attached to the device, and configure it
315 * properly. If the PHY is not recognized, then return 0
316 * (failure). Otherwise, return 1
318 static int init_phy(struct eth_device *dev)
320 struct tsec_private *priv = (struct tsec_private *)dev->priv;
321 struct phy_info *curphy;
322 tsec_t *regs = priv->regs;
324 /* Assign a Physical address to the TBI */
325 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
327 /* Reset MII (due to new addresses) */
328 out_be32(&priv->phyregs->miimcfg, MIIMCFG_RESET);
329 out_be32(&priv->phyregs->miimcfg, MIIMCFG_INIT_VALUE);
330 while (in_be32(&priv->phyregs->miimind) & MIIMIND_BUSY)
333 /* Get the cmd structure corresponding to the attached
335 curphy = get_phy_info(dev);
337 if (curphy == NULL) {
338 priv->phyinfo = NULL;
339 printf("%s: No PHY found\n", dev->name);
344 if (in_be32(®s->ecntrl) & ECNTRL_SGMII_MODE)
345 tsec_configure_serdes(priv);
347 priv->phyinfo = curphy;
349 phy_run_commands(priv, priv->phyinfo->config);
355 * Returns which value to write to the control register.
356 * For 10/100, the value is slightly different
358 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
360 if (priv->flags & TSEC_GIGABIT)
361 return MIIM_CONTROL_INIT;
367 * Wait for auto-negotiation to complete, then determine link
369 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
372 * Wait if the link is up, and autonegotiation is in progress
373 * (ie - we're capable and it's not done)
375 mii_reg = read_phy_reg(priv, MIIM_STATUS);
376 if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
379 puts("Waiting for PHY auto negotiation to complete");
380 while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
384 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
385 puts(" TIMEOUT !\n");
391 puts("user interrupt!\n");
396 if ((i++ % 1000) == 0) {
399 udelay(1000); /* 1 ms */
400 mii_reg = read_phy_reg(priv, MIIM_STATUS);
404 /* Link status bit is latched low, read it again */
405 mii_reg = read_phy_reg(priv, MIIM_STATUS);
407 udelay(500000); /* another 500 ms (results in faster booting) */
410 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
415 /* Generic function which updates the speed and duplex. If
416 * autonegotiation is enabled, it uses the AND of the link
417 * partner's advertised capabilities and our advertised
418 * capabilities. If autonegotiation is disabled, we use the
419 * appropriate bits in the control register.
421 * Stolen from Linux's mii.c and phy_device.c
423 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
425 /* We're using autonegotiation */
426 if (mii_reg & BMSR_ANEGCAPABLE) {
430 /* Check for gigabit capability */
431 if (mii_reg & BMSR_ERCAP) {
432 /* We want a list of states supported by
433 * both PHYs in the link
435 gblpa = read_phy_reg(priv, MII_STAT1000);
436 gblpa &= read_phy_reg(priv, MII_CTRL1000) << 2;
439 /* Set the baseline so we only have to set them
440 * if they're different
445 /* Check the gigabit fields */
446 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
449 if (gblpa & PHY_1000BTSR_1000FD)
456 lpa = read_phy_reg(priv, MII_ADVERTISE);
457 lpa &= read_phy_reg(priv, MII_LPA);
459 if (lpa & (LPA_100FULL | LPA_100HALF)) {
462 if (lpa & LPA_100FULL)
465 } else if (lpa & LPA_10FULL)
468 uint bmcr = read_phy_reg(priv, MII_BMCR);
473 if (bmcr & BMCR_FULLDPLX)
476 if (bmcr & BMCR_SPEED1000)
478 else if (bmcr & BMCR_SPEED100)
486 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
487 * circumstances. eg a gigabit TSEC connected to a gigabit switch with
488 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
489 * link. "Ethernet@Wirespeed" reduces advertised speed until link
492 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
494 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
498 * Parse the BCM54xx status register for speed and duplex information.
499 * The linux sungem_phy has this information, but in a table format.
501 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
503 /* If there is no link, speed and duplex don't matter */
507 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
508 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
534 printf("Auto-neg error, defaulting to 10BT/HD\n");
544 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
545 * 0x42 - "Operating Mode Status Register"
547 static int BCM8482_is_serdes(struct tsec_private *priv)
552 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42);
553 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
555 switch (val & 0x1f) {
556 case 0x0d: /* RGMII-to-100Base-FX */
557 case 0x0e: /* RGMII-to-SGMII */
558 case 0x0f: /* RGMII-to-SerDes */
559 case 0x12: /* SGMII-to-SerDes */
560 case 0x13: /* SGMII-to-100Base-FX */
561 case 0x16: /* SerDes-to-Serdes */
564 case 0x6: /* RGMII-to-Copper */
565 case 0x14: /* SGMII-to-Copper */
566 case 0x17: /* SerDes-to-Copper */
569 printf("ERROR, invalid PHY mode (0x%x\n)", val);
577 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
578 * Mode Status Register"
580 uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv)
585 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
587 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL,
588 MIIM_BCM54XX_EXP_SEL_ER | 0x42);
589 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
599 udelay(1000); /* 1 ms */
603 switch ((val >> 13) & 0x3) {
615 priv->duplexity = (val & 0x1000) == 0x1000;
621 * Figure out if BCM5482 is in serdes or copper mode and determine link
622 * configuration accordingly
624 static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv)
626 if (BCM8482_is_serdes(priv)) {
627 mii_parse_BCM5482_serdes_sr(priv);
628 priv->flags |= TSEC_FIBER;
630 /* Wait for auto-negotiation to complete or fail */
631 mii_parse_sr(mii_reg, priv);
633 /* Parse BCM54xx copper aux status register */
634 mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS);
635 mii_parse_BCM54xx_sr(mii_reg, priv);
641 /* Parse the 88E1011's status register for speed and duplex
644 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
648 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
650 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
651 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
654 puts("Waiting for PHY realtime link");
655 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
656 /* Timeout reached ? */
657 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
658 puts(" TIMEOUT !\n");
663 if ((i++ % 1000) == 0) {
666 udelay(1000); /* 1 ms */
667 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
670 udelay(500000); /* another 500 ms (results in faster booting) */
672 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
678 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
683 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
686 case MIIM_88E1011_PHYSTAT_GBIT:
689 case MIIM_88E1011_PHYSTAT_100:
699 /* Parse the RTL8211B's status register for speed and duplex
702 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
706 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
707 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
710 /* in case of timeout ->link is cleared */
712 puts("Waiting for PHY realtime link");
713 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
714 /* Timeout reached ? */
715 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
716 puts(" TIMEOUT !\n");
721 if ((i++ % 1000) == 0) {
724 udelay(1000); /* 1 ms */
725 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
728 udelay(500000); /* another 500 ms (results in faster booting) */
730 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
736 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
741 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
744 case MIIM_RTL8211B_PHYSTAT_GBIT:
747 case MIIM_RTL8211B_PHYSTAT_100:
757 /* Parse the cis8201's status register for speed and duplex
760 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
764 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
769 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
771 case MIIM_CIS8201_AUXCONSTAT_GBIT:
774 case MIIM_CIS8201_AUXCONSTAT_100:
785 /* Parse the vsc8244's status register for speed and duplex
788 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
792 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
797 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
799 case MIIM_VSC8244_AUXCONSTAT_GBIT:
802 case MIIM_VSC8244_AUXCONSTAT_100:
813 /* Parse the DM9161's status register for speed and duplex
816 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
818 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
823 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
832 * Hack to write all 4 PHYs with the LED values
834 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
837 tsec_mdio_t *regbase = priv->phyregs;
838 int timeout = 1000000;
840 for (phyid = 0; phyid < 4; phyid++) {
841 out_be32(®base->miimadd, (phyid << 8) | mii_reg);
842 out_be32(®base->miimcon, MIIM_CIS8204_SLEDCON_INIT);
845 while ((in_be32(®base->miimind) & MIIMIND_BUSY) && timeout--)
849 return MIIM_CIS8204_SLEDCON_INIT;
852 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
854 if (priv->flags & TSEC_REDUCED)
855 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
857 return MIIM_CIS8204_EPHYCON_INIT;
860 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
862 uint mii_data = read_phy_reg(priv, mii_reg);
864 if (priv->flags & TSEC_REDUCED)
865 mii_data = (mii_data & 0xfff0) | 0x000b;
869 /* Initialized required registers to appropriate values, zeroing
870 * those we don't care about (unless zero is bad, in which case,
871 * choose a more appropriate value)
873 static void init_registers(tsec_t *regs)
876 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
878 out_be32(®s->imask, IMASK_INIT_CLEAR);
880 out_be32(®s->hash.iaddr0, 0);
881 out_be32(®s->hash.iaddr1, 0);
882 out_be32(®s->hash.iaddr2, 0);
883 out_be32(®s->hash.iaddr3, 0);
884 out_be32(®s->hash.iaddr4, 0);
885 out_be32(®s->hash.iaddr5, 0);
886 out_be32(®s->hash.iaddr6, 0);
887 out_be32(®s->hash.iaddr7, 0);
889 out_be32(®s->hash.gaddr0, 0);
890 out_be32(®s->hash.gaddr1, 0);
891 out_be32(®s->hash.gaddr2, 0);
892 out_be32(®s->hash.gaddr3, 0);
893 out_be32(®s->hash.gaddr4, 0);
894 out_be32(®s->hash.gaddr5, 0);
895 out_be32(®s->hash.gaddr6, 0);
896 out_be32(®s->hash.gaddr7, 0);
898 out_be32(®s->rctrl, 0x00000000);
900 /* Init RMON mib registers */
901 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
903 out_be32(®s->rmon.cam1, 0xffffffff);
904 out_be32(®s->rmon.cam2, 0xffffffff);
906 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
908 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
910 out_be32(®s->attr, ATTR_INIT_SETTINGS);
911 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
915 /* Configure maccfg2 based on negotiated speed and duplex
916 * reported by PHY handling code
918 static void adjust_link(struct eth_device *dev)
920 struct tsec_private *priv = (struct tsec_private *)dev->priv;
921 tsec_t *regs = priv->regs;
925 printf("%s: No link.\n", dev->name);
929 /* clear all bits relative with interface mode */
930 ecntrl = in_be32(®s->ecntrl);
931 ecntrl &= ~ECNTRL_R100;
933 maccfg2 = in_be32(®s->maccfg2);
934 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
937 maccfg2 |= MACCFG2_FULL_DUPLEX;
939 switch (priv->speed) {
941 maccfg2 |= MACCFG2_GMII;
945 maccfg2 |= MACCFG2_MII;
947 /* Set R100 bit in all modes although
948 * it is only used in RGMII mode
950 if (priv->speed == 100)
951 ecntrl |= ECNTRL_R100;
954 printf("%s: Speed was bad\n", dev->name);
958 out_be32(®s->ecntrl, ecntrl);
959 out_be32(®s->maccfg2, maccfg2);
961 printf("Speed: %d, %s duplex%s\n", priv->speed,
962 (priv->duplexity) ? "full" : "half",
963 (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
966 /* Set up the buffers and their descriptors, and bring up the
969 static void startup_tsec(struct eth_device *dev)
972 struct tsec_private *priv = (struct tsec_private *)dev->priv;
973 tsec_t *regs = priv->regs;
975 /* Point to the buffer descriptors */
976 out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
977 out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
979 /* Initialize the Rx Buffer descriptors */
980 for (i = 0; i < PKTBUFSRX; i++) {
981 rtx.rxbd[i].status = RXBD_EMPTY;
982 rtx.rxbd[i].length = 0;
983 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
985 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
987 /* Initialize the TX Buffer Descriptors */
988 for (i = 0; i < TX_BUF_CNT; i++) {
989 rtx.txbd[i].status = 0;
990 rtx.txbd[i].length = 0;
991 rtx.txbd[i].bufPtr = 0;
993 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
995 /* Start up the PHY */
997 phy_run_commands(priv, priv->phyinfo->startup);
1001 /* Enable Transmit and Receive */
1002 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
1004 /* Tell the DMA it is clear to go */
1005 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
1006 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
1007 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
1008 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
1011 /* This returns the status bits of the device. The return value
1012 * is never checked, and this is what the 8260 driver did, so we
1013 * do the same. Presumably, this would be zero if there were no
1016 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
1020 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1021 tsec_t *regs = priv->regs;
1023 /* Find an empty buffer descriptor */
1024 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
1025 if (i >= TOUT_LOOP) {
1026 debug("%s: tsec: tx buffers full\n", dev->name);
1031 rtx.txbd[txIdx].bufPtr = (uint) packet;
1032 rtx.txbd[txIdx].length = length;
1033 rtx.txbd[txIdx].status |=
1034 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
1036 /* Tell the DMA to go */
1037 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
1039 /* Wait for buffer to be transmitted */
1040 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
1041 if (i >= TOUT_LOOP) {
1042 debug("%s: tsec: tx error\n", dev->name);
1047 txIdx = (txIdx + 1) % TX_BUF_CNT;
1048 result = rtx.txbd[txIdx].status & TXBD_STATS;
1053 static int tsec_recv(struct eth_device *dev)
1056 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1057 tsec_t *regs = priv->regs;
1059 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
1061 length = rtx.rxbd[rxIdx].length;
1063 /* Send the packet up if there were no errors */
1064 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
1065 NetReceive(NetRxPackets[rxIdx], length - 4);
1067 printf("Got error %x\n",
1068 (rtx.rxbd[rxIdx].status & RXBD_STATS));
1071 rtx.rxbd[rxIdx].length = 0;
1073 /* Set the wrap bit if this is the last element in the list */
1074 rtx.rxbd[rxIdx].status =
1075 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
1077 rxIdx = (rxIdx + 1) % PKTBUFSRX;
1080 if (in_be32(®s->ievent) & IEVENT_BSY) {
1081 out_be32(®s->ievent, IEVENT_BSY);
1082 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
1089 /* Stop the interface */
1090 static void tsec_halt(struct eth_device *dev)
1092 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1093 tsec_t *regs = priv->regs;
1095 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
1096 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
1098 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
1099 != (IEVENT_GRSC | IEVENT_GTSC))
1102 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
1104 /* Shut down the PHY, as needed */
1106 phy_run_commands(priv, priv->phyinfo->shutdown);
1109 static struct phy_info phy_info_M88E1149S = {
1113 (struct phy_cmd[]) { /* config */
1114 /* Reset and configure the PHY */
1115 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1117 {0x1e, 0x200c, NULL},
1120 {0x1e, 0x100, NULL},
1121 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1122 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1123 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1124 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1127 (struct phy_cmd[]) { /* startup */
1128 /* Status is read once to clear old link state */
1129 {MIIM_STATUS, miim_read, NULL},
1130 /* Auto-negotiate */
1131 {MIIM_STATUS, miim_read, &mii_parse_sr},
1132 /* Read the status */
1133 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1136 (struct phy_cmd[]) { /* shutdown */
1141 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1142 static struct phy_info phy_info_BCM5461S = {
1143 0x02060c1, /* 5461 ID */
1144 "Broadcom BCM5461S",
1145 0, /* not clear to me what minor revisions we can shift away */
1146 (struct phy_cmd[]) { /* config */
1147 /* Reset and configure the PHY */
1148 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1149 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1150 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1151 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1152 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1155 (struct phy_cmd[]) { /* startup */
1156 /* Status is read once to clear old link state */
1157 {MIIM_STATUS, miim_read, NULL},
1158 /* Auto-negotiate */
1159 {MIIM_STATUS, miim_read, &mii_parse_sr},
1160 /* Read the status */
1161 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1164 (struct phy_cmd[]) { /* shutdown */
1169 static struct phy_info phy_info_BCM5464S = {
1170 0x02060b1, /* 5464 ID */
1171 "Broadcom BCM5464S",
1172 0, /* not clear to me what minor revisions we can shift away */
1173 (struct phy_cmd[]) { /* config */
1174 /* Reset and configure the PHY */
1175 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1176 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1177 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1178 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1179 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1182 (struct phy_cmd[]) { /* startup */
1183 /* Status is read once to clear old link state */
1184 {MIIM_STATUS, miim_read, NULL},
1185 /* Auto-negotiate */
1186 {MIIM_STATUS, miim_read, &mii_parse_sr},
1187 /* Read the status */
1188 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1191 (struct phy_cmd[]) { /* shutdown */
1196 static struct phy_info phy_info_BCM5482S = {
1198 "Broadcom BCM5482S",
1200 (struct phy_cmd[]) { /* config */
1201 /* Reset and configure the PHY */
1202 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1203 /* Setup read from auxilary control shadow register 7 */
1204 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1205 /* Read Misc Control register and or in Ethernet@Wirespeed */
1206 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1207 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1208 /* Initial config/enable of secondary SerDes interface */
1209 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL},
1210 /* Write intial value to secondary SerDes Contol */
1211 {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL},
1212 {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL},
1213 /* Enable copper/fiber auto-detect */
1214 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)},
1217 (struct phy_cmd[]) { /* startup */
1218 /* Status is read once to clear old link state */
1219 {MIIM_STATUS, miim_read, NULL},
1220 /* Determine copper/fiber, auto-negotiate, and read the result */
1221 {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr},
1224 (struct phy_cmd[]) { /* shutdown */
1229 static struct phy_info phy_info_M88E1011S = {
1233 (struct phy_cmd[]) { /* config */
1234 /* Reset and configure the PHY */
1235 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1237 {0x1e, 0x200c, NULL},
1240 {0x1e, 0x100, NULL},
1241 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1242 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1243 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1244 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1247 (struct phy_cmd[]) { /* startup */
1248 /* Status is read once to clear old link state */
1249 {MIIM_STATUS, miim_read, NULL},
1250 /* Auto-negotiate */
1251 {MIIM_STATUS, miim_read, &mii_parse_sr},
1252 /* Read the status */
1253 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1256 (struct phy_cmd[]) { /* shutdown */
1261 static struct phy_info phy_info_M88E1111S = {
1265 (struct phy_cmd[]) { /* config */
1266 /* Reset and configure the PHY */
1267 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1268 {0x1b, 0x848f, &mii_m88e1111s_setmode},
1269 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1270 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1271 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1272 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1273 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1276 (struct phy_cmd[]) { /* startup */
1277 /* Status is read once to clear old link state */
1278 {MIIM_STATUS, miim_read, NULL},
1279 /* Auto-negotiate */
1280 {MIIM_STATUS, miim_read, &mii_parse_sr},
1281 /* Read the status */
1282 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1285 (struct phy_cmd[]) { /* shutdown */
1290 static struct phy_info phy_info_M88E1118 = {
1294 (struct phy_cmd[]) { /* config */
1295 /* Reset and configure the PHY */
1296 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1297 {0x16, 0x0002, NULL}, /* Change Page Number */
1298 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1299 {0x16, 0x0003, NULL}, /* Change Page Number */
1300 {0x10, 0x021e, NULL}, /* Adjust LED control */
1301 {0x16, 0x0000, NULL}, /* Change Page Number */
1302 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1303 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1304 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1305 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1308 (struct phy_cmd[]) { /* startup */
1309 {0x16, 0x0000, NULL}, /* Change Page Number */
1310 /* Status is read once to clear old link state */
1311 {MIIM_STATUS, miim_read, NULL},
1312 /* Auto-negotiate */
1313 {MIIM_STATUS, miim_read, &mii_parse_sr},
1314 /* Read the status */
1315 {MIIM_88E1011_PHY_STATUS, miim_read,
1316 &mii_parse_88E1011_psr},
1319 (struct phy_cmd[]) { /* shutdown */
1325 * Since to access LED register we need do switch the page, we
1326 * do LED configuring in the miim_read-like function as follows
1328 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1332 /* Switch the page to access the led register */
1333 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1334 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1336 /* Configure leds */
1337 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1338 MIIM_88E1121_PHY_LED_DEF);
1340 /* Restore the page pointer */
1341 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1345 static struct phy_info phy_info_M88E1121R = {
1349 (struct phy_cmd[]) { /* config */
1350 /* Reset and configure the PHY */
1351 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1352 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1353 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1354 /* Configure leds */
1355 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led},
1356 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1357 /* Disable IRQs and de-assert interrupt */
1358 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1359 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1362 (struct phy_cmd[]) { /* startup */
1363 /* Status is read once to clear old link state */
1364 {MIIM_STATUS, miim_read, NULL},
1365 {MIIM_STATUS, miim_read, &mii_parse_sr},
1366 {MIIM_STATUS, miim_read, &mii_parse_link},
1369 (struct phy_cmd[]) { /* shutdown */
1374 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1376 uint mii_data = read_phy_reg(priv, mii_reg);
1378 /* Setting MIIM_88E1145_PHY_EXT_CR */
1379 if (priv->flags & TSEC_REDUCED)
1381 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1386 static struct phy_info phy_info_M88E1145 = {
1390 (struct phy_cmd[]) { /* config */
1392 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1400 /* Configure the PHY */
1401 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1402 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1403 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
1404 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1405 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1406 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1409 (struct phy_cmd[]) { /* startup */
1410 /* Status is read once to clear old link state */
1411 {MIIM_STATUS, miim_read, NULL},
1412 /* Auto-negotiate */
1413 {MIIM_STATUS, miim_read, &mii_parse_sr},
1414 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
1415 /* Read the Status */
1416 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1419 (struct phy_cmd[]) { /* shutdown */
1424 static struct phy_info phy_info_cis8204 = {
1428 (struct phy_cmd[]) { /* config */
1429 /* Override PHY config settings */
1430 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1431 /* Configure some basic stuff */
1432 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1433 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1434 &mii_cis8204_fixled},
1435 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1436 &mii_cis8204_setmode},
1439 (struct phy_cmd[]) { /* startup */
1440 /* Read the Status (2x to make sure link is right) */
1441 {MIIM_STATUS, miim_read, NULL},
1442 /* Auto-negotiate */
1443 {MIIM_STATUS, miim_read, &mii_parse_sr},
1444 /* Read the status */
1445 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1448 (struct phy_cmd[]) { /* shutdown */
1454 static struct phy_info phy_info_cis8201 = {
1458 (struct phy_cmd[]) { /* config */
1459 /* Override PHY config settings */
1460 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1461 /* Set up the interface mode */
1462 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1463 /* Configure some basic stuff */
1464 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1467 (struct phy_cmd[]) { /* startup */
1468 /* Read the Status (2x to make sure link is right) */
1469 {MIIM_STATUS, miim_read, NULL},
1470 /* Auto-negotiate */
1471 {MIIM_STATUS, miim_read, &mii_parse_sr},
1472 /* Read the status */
1473 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1476 (struct phy_cmd[]) { /* shutdown */
1481 static struct phy_info phy_info_VSC8211 = {
1485 (struct phy_cmd[]) { /* config */
1486 /* Override PHY config settings */
1487 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1488 /* Set up the interface mode */
1489 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1490 /* Configure some basic stuff */
1491 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1494 (struct phy_cmd[]) { /* startup */
1495 /* Read the Status (2x to make sure link is right) */
1496 {MIIM_STATUS, miim_read, NULL},
1497 /* Auto-negotiate */
1498 {MIIM_STATUS, miim_read, &mii_parse_sr},
1499 /* Read the status */
1500 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1503 (struct phy_cmd[]) { /* shutdown */
1508 static struct phy_info phy_info_VSC8244 = {
1512 (struct phy_cmd[]) { /* config */
1513 /* Override PHY config settings */
1514 /* Configure some basic stuff */
1515 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1518 (struct phy_cmd[]) { /* startup */
1519 /* Read the Status (2x to make sure link is right) */
1520 {MIIM_STATUS, miim_read, NULL},
1521 /* Auto-negotiate */
1522 {MIIM_STATUS, miim_read, &mii_parse_sr},
1523 /* Read the status */
1524 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1527 (struct phy_cmd[]) { /* shutdown */
1532 static struct phy_info phy_info_VSC8641 = {
1536 (struct phy_cmd[]) { /* config */
1537 /* Configure some basic stuff */
1538 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1541 (struct phy_cmd[]) { /* startup */
1542 /* Read the Status (2x to make sure link is right) */
1543 {MIIM_STATUS, miim_read, NULL},
1544 /* Auto-negotiate */
1545 {MIIM_STATUS, miim_read, &mii_parse_sr},
1546 /* Read the status */
1547 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1550 (struct phy_cmd[]) { /* shutdown */
1555 static struct phy_info phy_info_VSC8221 = {
1559 (struct phy_cmd[]) { /* config */
1560 /* Configure some basic stuff */
1561 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1564 (struct phy_cmd[]) { /* startup */
1565 /* Read the Status (2x to make sure link is right) */
1566 {MIIM_STATUS, miim_read, NULL},
1567 /* Auto-negotiate */
1568 {MIIM_STATUS, miim_read, &mii_parse_sr},
1569 /* Read the status */
1570 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1573 (struct phy_cmd[]) { /* shutdown */
1578 static struct phy_info phy_info_VSC8601 = {
1582 (struct phy_cmd[]) { /* config */
1583 /* Override PHY config settings */
1584 /* Configure some basic stuff */
1585 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1586 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1587 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1588 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1589 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1590 #define VSC8101_SKEW \
1591 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12)
1592 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1593 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1596 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1597 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1600 (struct phy_cmd[]) { /* startup */
1601 /* Read the Status (2x to make sure link is right) */
1602 {MIIM_STATUS, miim_read, NULL},
1603 /* Auto-negotiate */
1604 {MIIM_STATUS, miim_read, &mii_parse_sr},
1605 /* Read the status */
1606 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1609 (struct phy_cmd[]) { /* shutdown */
1614 static struct phy_info phy_info_dm9161 = {
1618 (struct phy_cmd[]) { /* config */
1619 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1620 /* Do not bypass the scrambler/descrambler */
1621 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1622 /* Clear 10BTCSR to default */
1623 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
1624 /* Configure some basic stuff */
1625 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1626 /* Restart Auto Negotiation */
1627 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1630 (struct phy_cmd[]) { /* startup */
1631 /* Status is read once to clear old link state */
1632 {MIIM_STATUS, miim_read, NULL},
1633 /* Auto-negotiate */
1634 {MIIM_STATUS, miim_read, &mii_parse_sr},
1635 /* Read the status */
1636 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
1639 (struct phy_cmd[]) { /* shutdown */
1645 static struct phy_info phy_info_ksz804 = {
1647 "Micrel KSZ804 PHY",
1649 (struct phy_cmd[]) { /* config */
1650 {MII_BMCR, BMCR_RESET, NULL},
1651 {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
1654 (struct phy_cmd[]) { /* startup */
1655 {MII_BMSR, miim_read, NULL},
1656 {MII_BMSR, miim_read, &mii_parse_sr},
1657 {MII_BMSR, miim_read, &mii_parse_link},
1660 (struct phy_cmd[]) { /* shutdown */
1665 /* a generic flavor. */
1666 static struct phy_info phy_info_generic = {
1668 "Unknown/Generic PHY",
1670 (struct phy_cmd[]) { /* config */
1671 {MII_BMCR, BMCR_RESET, NULL},
1672 {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
1675 (struct phy_cmd[]) { /* startup */
1676 {MII_BMSR, miim_read, NULL},
1677 {MII_BMSR, miim_read, &mii_parse_sr},
1678 {MII_BMSR, miim_read, &mii_parse_link},
1681 (struct phy_cmd[]) { /* shutdown */
1686 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1690 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1693 case MIIM_LXT971_SR2_10HDX:
1695 priv->duplexity = 0;
1697 case MIIM_LXT971_SR2_10FDX:
1699 priv->duplexity = 1;
1701 case MIIM_LXT971_SR2_100HDX:
1703 priv->duplexity = 0;
1707 priv->duplexity = 1;
1711 priv->duplexity = 0;
1717 static struct phy_info phy_info_lxt971 = {
1721 (struct phy_cmd[]) { /* config */
1722 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1725 (struct phy_cmd[]) { /* startup - enable interrupts */
1726 /* { 0x12, 0x00f2, NULL }, */
1727 {MIIM_STATUS, miim_read, NULL},
1728 {MIIM_STATUS, miim_read, &mii_parse_sr},
1729 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1732 (struct phy_cmd[]) { /* shutdown - disable interrupts */
1737 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1740 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1742 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1744 case MIIM_DP83865_SPD_1000:
1748 case MIIM_DP83865_SPD_100:
1758 if (mii_reg & MIIM_DP83865_DPX_FULL)
1759 priv->duplexity = 1;
1761 priv->duplexity = 0;
1766 static struct phy_info phy_info_dp83865 = {
1770 (struct phy_cmd[]) { /* config */
1771 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1774 (struct phy_cmd[]) { /* startup */
1775 /* Status is read once to clear old link state */
1776 {MIIM_STATUS, miim_read, NULL},
1777 /* Auto-negotiate */
1778 {MIIM_STATUS, miim_read, &mii_parse_sr},
1779 /* Read the link and auto-neg status */
1780 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
1783 (struct phy_cmd[]) { /* shutdown */
1788 static struct phy_info phy_info_rtl8211b = {
1792 (struct phy_cmd[]) { /* config */
1793 /* Reset and configure the PHY */
1794 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1795 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1796 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1797 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1798 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1801 (struct phy_cmd[]) { /* startup */
1802 /* Status is read once to clear old link state */
1803 {MIIM_STATUS, miim_read, NULL},
1804 /* Auto-negotiate */
1805 {MIIM_STATUS, miim_read, &mii_parse_sr},
1806 /* Read the status */
1807 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1810 (struct phy_cmd[]) { /* shutdown */
1815 struct phy_info phy_info_AR8021 = {
1819 (struct phy_cmd[]) { /* config */
1820 {MII_BMCR, BMCR_RESET, NULL},
1821 {MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART, NULL},
1823 {0x1e, 0x3D47, NULL},
1826 (struct phy_cmd[]) { /* startup */
1827 {MII_BMSR, miim_read, NULL},
1828 {MII_BMSR, miim_read, &mii_parse_sr},
1829 {MII_BMSR, miim_read, &mii_parse_link},
1832 (struct phy_cmd[]) { /* shutdown */
1837 static struct phy_info *phy_info[] = {
1843 &phy_info_M88E1011S,
1844 &phy_info_M88E1111S,
1846 &phy_info_M88E1121R,
1848 &phy_info_M88E1149S,
1860 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
1864 /* Grab the identifier of the device's PHY, and search through
1865 * all of the known PHYs to see if one matches. If so, return
1866 * it, if not, return NULL
1868 static struct phy_info *get_phy_info(struct eth_device *dev)
1870 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1871 uint phy_reg, phy_ID;
1873 struct phy_info *theInfo = NULL;
1875 /* Grab the bits from PHYIR1, and put them in the upper half */
1876 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1877 phy_ID = (phy_reg & 0xffff) << 16;
1879 /* Grab the bits from PHYIR2, and put them in the lower half */
1880 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1881 phy_ID |= (phy_reg & 0xffff);
1883 /* loop through all the known PHY types, and find one that */
1884 /* matches the ID we read from the PHY. */
1885 for (i = 0; phy_info[i]; i++) {
1886 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1887 theInfo = phy_info[i];
1892 if (theInfo == &phy_info_generic) {
1893 printf("%s: No support for PHY id %x; assuming generic\n",
1896 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1902 /* Execute the given series of commands on the given device's
1903 * PHY, running functions as necessary
1905 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1909 tsec_mdio_t *phyregs = priv->phyregs;
1911 out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
1913 out_be32(&phyregs->miimcfg, MIIMCFG_INIT_VALUE);
1915 while (in_be32(&phyregs->miimind) & MIIMIND_BUSY)
1918 for (i = 0; cmd->mii_reg != miim_end; i++) {
1919 if (cmd->mii_data == miim_read) {
1920 result = read_phy_reg(priv, cmd->mii_reg);
1922 if (cmd->funct != NULL)
1923 (*(cmd->funct)) (result, priv);
1926 if (cmd->funct != NULL)
1927 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1929 result = cmd->mii_data;
1931 write_phy_reg(priv, cmd->mii_reg, result);
1938 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1939 && !defined(BITBANGMII)
1942 * Read a MII PHY register.
1947 static int tsec_miiphy_read(const char *devname, unsigned char addr,
1948 unsigned char reg, unsigned short *value)
1951 struct tsec_private *priv = privlist[0];
1954 printf("Can't read PHY at address %d\n", addr);
1958 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1965 * Write a MII PHY register.
1970 static int tsec_miiphy_write(const char *devname, unsigned char addr,
1971 unsigned char reg, unsigned short value)
1973 struct tsec_private *priv = privlist[0];
1976 printf("Can't write PHY at address %d\n", addr);
1980 tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1987 #ifdef CONFIG_MCAST_TFTP
1989 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1991 /* Set the appropriate hash bit for the given addr */
1993 /* The algorithm works like so:
1994 * 1) Take the Destination Address (ie the multicast address), and
1995 * do a CRC on it (little endian), and reverse the bits of the
1997 * 2) Use the 8 most significant bits as a hash into a 256-entry
1998 * table. The table is controlled through 8 32-bit registers:
1999 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2000 * gaddr7. This means that the 3 most significant bits in the
2001 * hash index which gaddr register to use, and the 5 other bits
2002 * indicate which bit (assuming an IBM numbering scheme, which
2003 * for PowerPC (tm) is usually the case) in the tregister holds
2006 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
2008 struct tsec_private *priv = privlist[1];
2009 volatile tsec_t *regs = priv->regs;
2010 volatile u32 *reg_array, value;
2011 u8 result, whichbit, whichreg;
2013 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
2014 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
2015 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
2016 value = (1 << (31-whichbit));
2018 reg_array = &(regs->hash.gaddr0);
2021 reg_array[whichreg] |= value;
2023 reg_array[whichreg] &= ~value;
2027 #endif /* Multicast TFTP ? */