2 * Freescale Three Speed Ethernet Controller driver
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
8 * Copyright 2004-2009 Freescale Semiconductor, Inc.
9 * (C) Copyright 2003, Motorola, Inc.
20 #include <asm/errno.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 #define MAXCONTROLLERS (8)
38 static struct tsec_private *privlist[MAXCONTROLLERS];
39 static int num_tsecs = 0;
42 static RTXBD rtx __attribute__ ((aligned(8)));
44 #error "rtx must be 64-bit aligned"
47 static int tsec_send(struct eth_device *dev,
48 volatile void *packet, int length);
49 static int tsec_recv(struct eth_device *dev);
50 static int tsec_init(struct eth_device *dev, bd_t * bd);
51 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
52 static void tsec_halt(struct eth_device *dev);
53 static void init_registers(volatile tsec_t * regs);
54 static void startup_tsec(struct eth_device *dev);
55 static int init_phy(struct eth_device *dev);
56 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
57 uint read_phy_reg(struct tsec_private *priv, uint regnum);
58 static struct phy_info *get_phy_info(struct eth_device *dev);
59 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
60 static void adjust_link(struct eth_device *dev);
61 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
62 && !defined(BITBANGMII)
63 static int tsec_miiphy_write(const char *devname, unsigned char addr,
64 unsigned char reg, unsigned short value);
65 static int tsec_miiphy_read(const char *devname, unsigned char addr,
66 unsigned char reg, unsigned short *value);
68 #ifdef CONFIG_MCAST_TFTP
69 static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
72 /* Default initializations for TSEC controllers. */
74 static struct tsec_info_struct tsec_info[] = {
76 STD_TSEC_INFO(1), /* TSEC1 */
79 STD_TSEC_INFO(2), /* TSEC2 */
81 #ifdef CONFIG_MPC85XX_FEC
83 .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
84 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
85 .devname = CONFIG_MPC85XX_FEC_NAME,
86 .phyaddr = FEC_PHY_ADDR,
91 STD_TSEC_INFO(3), /* TSEC3 */
94 STD_TSEC_INFO(4), /* TSEC4 */
99 * Initialize all the TSEC devices
101 * Returns the number of TSEC devices that were initialized
103 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
108 for (i = 0; i < num; i++) {
109 ret = tsec_initialize(bis, &tsecs[i]);
117 int tsec_standard_init(bd_t *bis)
119 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
122 /* Initialize device structure. Returns success if PHY
123 * initialization succeeded (i.e. if it recognizes the PHY)
125 static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
127 struct eth_device *dev;
129 struct tsec_private *priv;
131 dev = (struct eth_device *)malloc(sizeof *dev);
136 memset(dev, 0, sizeof *dev);
138 priv = (struct tsec_private *)malloc(sizeof(*priv));
143 privlist[num_tsecs++] = priv;
144 priv->regs = tsec_info->regs;
145 priv->phyregs = tsec_info->miiregs;
146 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
148 priv->phyaddr = tsec_info->phyaddr;
149 priv->flags = tsec_info->flags;
151 sprintf(dev->name, tsec_info->devname);
154 dev->init = tsec_init;
155 dev->halt = tsec_halt;
156 dev->send = tsec_send;
157 dev->recv = tsec_recv;
158 #ifdef CONFIG_MCAST_TFTP
159 dev->mcast = tsec_mcast_addr;
162 /* Tell u-boot to get the addr from the env */
163 for (i = 0; i < 6; i++)
164 dev->enetaddr[i] = 0;
169 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
170 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
171 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
173 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
174 && !defined(BITBANGMII)
175 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
178 /* Try to initialize PHY here, and return */
179 return init_phy(dev);
182 /* Initializes data structures and registers for the controller,
183 * and brings the interface up. Returns the link status, meaning
184 * that it returns success if the link is up, failure otherwise.
185 * This allows u-boot to find the first active controller.
187 static int tsec_init(struct eth_device *dev, bd_t * bd)
190 char tmpbuf[MAC_ADDR_LEN];
192 struct tsec_private *priv = (struct tsec_private *)dev->priv;
193 volatile tsec_t *regs = priv->regs;
195 /* Make sure the controller is stopped */
198 /* Init MACCFG2. Defaults to GMII */
199 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
202 regs->ecntrl = ECNTRL_INIT_SETTINGS;
204 /* Copy the station address into the address registers.
205 * Backwards, because little endian MACS are dumb */
206 for (i = 0; i < MAC_ADDR_LEN; i++) {
207 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
209 tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
212 regs->macstnaddr1 = tempval;
214 tempval = *((uint *) (tmpbuf + 4));
216 regs->macstnaddr2 = tempval;
218 /* reset the indices to zero */
222 /* Clear out (for the most part) the other registers */
223 init_registers(regs);
225 /* Ready the device for tx/rx */
228 /* If there's no link, fail */
229 return (priv->link ? 0 : -1);
232 /* Writes the given phy's reg with value, using the specified MDIO regs */
233 static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
234 uint reg, uint value)
236 int timeout = 1000000;
238 phyregs->miimadd = (addr << 8) | reg;
239 phyregs->miimcon = value;
243 while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
247 /* Provide the default behavior of writing the PHY of this ethernet device */
248 #define write_phy_reg(priv, regnum, value) \
249 tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
251 /* Reads register regnum on the device's PHY through the
252 * specified registers. It lowers and raises the read
253 * command, and waits for the data to become valid (miimind
254 * notvalid bit cleared), and the bus to cease activity (miimind
255 * busy bit cleared), and then returns the value
257 static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
258 uint phyid, uint regnum)
262 /* Put the address of the phy, and the register
263 * number into MIIMADD */
264 phyregs->miimadd = (phyid << 8) | regnum;
266 /* Clear the command register, and wait */
267 phyregs->miimcom = 0;
270 /* Initiate a read command, and wait */
271 phyregs->miimcom = MIIM_READ_COMMAND;
274 /* Wait for the the indication that the read is done */
275 while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
277 /* Grab the value read from the PHY */
278 value = phyregs->miimstat;
283 /* #define to provide old read_phy_reg functionality without duplicating code */
284 #define read_phy_reg(priv,regnum) \
285 tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
287 #define TBIANA_SETTINGS ( \
288 TBIANA_ASYMMETRIC_PAUSE \
289 | TBIANA_SYMMETRIC_PAUSE \
290 | TBIANA_FULL_DUPLEX \
293 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
294 #ifndef CONFIG_TSEC_TBICR_SETTINGS
295 #define TBICR_SETTINGS ( \
297 | TBICR_FULL_DUPLEX \
301 #define TBICR_SETTINGS CONFIG_TSEC_TBICR_SETTINGS
302 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
304 /* Configure the TBI for SGMII operation */
305 static void tsec_configure_serdes(struct tsec_private *priv)
307 /* Access TBI PHY registers at given TSEC register offset as opposed
308 * to the register offset used for external PHY accesses */
309 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
311 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_TBICON,
313 tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
317 /* Discover which PHY is attached to the device, and configure it
318 * properly. If the PHY is not recognized, then return 0
319 * (failure). Otherwise, return 1
321 static int init_phy(struct eth_device *dev)
323 struct tsec_private *priv = (struct tsec_private *)dev->priv;
324 struct phy_info *curphy;
325 volatile tsec_t *regs = priv->regs;
327 /* Assign a Physical address to the TBI */
328 regs->tbipa = CONFIG_SYS_TBIPA_VALUE;
331 /* Reset MII (due to new addresses) */
332 priv->phyregs->miimcfg = MIIMCFG_RESET;
334 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
336 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
338 /* Get the cmd structure corresponding to the attached
340 curphy = get_phy_info(dev);
342 if (curphy == NULL) {
343 priv->phyinfo = NULL;
344 printf("%s: No PHY found\n", dev->name);
349 if (regs->ecntrl & ECNTRL_SGMII_MODE)
350 tsec_configure_serdes(priv);
352 priv->phyinfo = curphy;
354 phy_run_commands(priv, priv->phyinfo->config);
360 * Returns which value to write to the control register.
361 * For 10/100, the value is slightly different
363 static uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
365 if (priv->flags & TSEC_GIGABIT)
366 return MIIM_CONTROL_INIT;
372 * Wait for auto-negotiation to complete, then determine link
374 static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
377 * Wait if the link is up, and autonegotiation is in progress
378 * (ie - we're capable and it's not done)
380 mii_reg = read_phy_reg(priv, MIIM_STATUS);
381 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
384 puts("Waiting for PHY auto negotiation to complete");
385 while (!(mii_reg & PHY_BMSR_AUTN_COMP)) {
389 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
390 puts(" TIMEOUT !\n");
396 puts("user interrupt!\n");
401 if ((i++ % 1000) == 0) {
404 udelay(1000); /* 1 ms */
405 mii_reg = read_phy_reg(priv, MIIM_STATUS);
409 /* Link status bit is latched low, read it again */
410 mii_reg = read_phy_reg(priv, MIIM_STATUS);
412 udelay(500000); /* another 500 ms (results in faster booting) */
415 priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0;
420 /* Generic function which updates the speed and duplex. If
421 * autonegotiation is enabled, it uses the AND of the link
422 * partner's advertised capabilities and our advertised
423 * capabilities. If autonegotiation is disabled, we use the
424 * appropriate bits in the control register.
426 * Stolen from Linux's mii.c and phy_device.c
428 static uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
430 /* We're using autonegotiation */
431 if (mii_reg & PHY_BMSR_AUTN_ABLE) {
435 /* Check for gigabit capability */
436 if (mii_reg & PHY_BMSR_EXT) {
437 /* We want a list of states supported by
438 * both PHYs in the link
440 gblpa = read_phy_reg(priv, PHY_1000BTSR);
441 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
444 /* Set the baseline so we only have to set them
445 * if they're different
450 /* Check the gigabit fields */
451 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
454 if (gblpa & PHY_1000BTSR_1000FD)
461 lpa = read_phy_reg(priv, PHY_ANAR);
462 lpa &= read_phy_reg(priv, PHY_ANLPAR);
464 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
467 if (lpa & PHY_ANLPAR_TXFD)
470 } else if (lpa & PHY_ANLPAR_10FD)
473 uint bmcr = read_phy_reg(priv, PHY_BMCR);
478 if (bmcr & PHY_BMCR_DPLX)
481 if (bmcr & PHY_BMCR_1000_MBPS)
483 else if (bmcr & PHY_BMCR_100_MBPS)
491 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
492 * circumstances. eg a gigabit TSEC connected to a gigabit switch with
493 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
494 * link. "Ethernet@Wirespeed" reduces advertised speed until link
497 static uint mii_BCM54xx_wirespeed(uint mii_reg, struct tsec_private *priv)
499 return (read_phy_reg(priv, mii_reg) & 0x8FFF) | 0x8010;
503 * Parse the BCM54xx status register for speed and duplex information.
504 * The linux sungem_phy has this information, but in a table format.
506 static uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
508 /* If there is no link, speed and duplex don't matter */
512 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
513 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
539 printf("Auto-neg error, defaulting to 10BT/HD\n");
549 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
550 * 0x42 - "Operating Mode Status Register"
552 static int BCM8482_is_serdes(struct tsec_private *priv)
557 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_ER | 0x42);
558 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
560 switch (val & 0x1f) {
561 case 0x0d: /* RGMII-to-100Base-FX */
562 case 0x0e: /* RGMII-to-SGMII */
563 case 0x0f: /* RGMII-to-SerDes */
564 case 0x12: /* SGMII-to-SerDes */
565 case 0x13: /* SGMII-to-100Base-FX */
566 case 0x16: /* SerDes-to-Serdes */
569 case 0x6: /* RGMII-to-Copper */
570 case 0x14: /* SGMII-to-Copper */
571 case 0x17: /* SerDes-to-Copper */
574 printf("ERROR, invalid PHY mode (0x%x\n)", val);
582 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
583 * Mode Status Register"
585 uint mii_parse_BCM5482_serdes_sr(struct tsec_private *priv)
590 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */
592 write_phy_reg(priv, MIIM_BCM54XX_EXP_SEL,
593 MIIM_BCM54XX_EXP_SEL_ER | 0x42);
594 val = read_phy_reg(priv, MIIM_BCM54XX_EXP_DATA);
604 udelay(1000); /* 1 ms */
608 switch ((val >> 13) & 0x3) {
620 priv->duplexity = (val & 0x1000) == 0x1000;
626 * Figure out if BCM5482 is in serdes or copper mode and determine link
627 * configuration accordingly
629 static uint mii_parse_BCM5482_sr(uint mii_reg, struct tsec_private *priv)
631 if (BCM8482_is_serdes(priv)) {
632 mii_parse_BCM5482_serdes_sr(priv);
633 priv->flags |= TSEC_FIBER;
635 /* Wait for auto-negotiation to complete or fail */
636 mii_parse_sr(mii_reg, priv);
638 /* Parse BCM54xx copper aux status register */
639 mii_reg = read_phy_reg(priv, MIIM_BCM54xx_AUXSTATUS);
640 mii_parse_BCM54xx_sr(mii_reg, priv);
646 /* Parse the 88E1011's status register for speed and duplex
649 static uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
653 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
655 if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
656 !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
659 puts("Waiting for PHY realtime link");
660 while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
661 /* Timeout reached ? */
662 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
663 puts(" TIMEOUT !\n");
668 if ((i++ % 1000) == 0) {
671 udelay(1000); /* 1 ms */
672 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
675 udelay(500000); /* another 500 ms (results in faster booting) */
677 if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
683 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
688 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
691 case MIIM_88E1011_PHYSTAT_GBIT:
694 case MIIM_88E1011_PHYSTAT_100:
704 /* Parse the RTL8211B's status register for speed and duplex
707 static uint mii_parse_RTL8211B_sr(uint mii_reg, struct tsec_private * priv)
711 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
712 if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
715 /* in case of timeout ->link is cleared */
717 puts("Waiting for PHY realtime link");
718 while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
719 /* Timeout reached ? */
720 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
721 puts(" TIMEOUT !\n");
726 if ((i++ % 1000) == 0) {
729 udelay(1000); /* 1 ms */
730 mii_reg = read_phy_reg(priv, MIIM_RTL8211B_PHY_STATUS);
733 udelay(500000); /* another 500 ms (results in faster booting) */
735 if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
741 if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
746 speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
749 case MIIM_RTL8211B_PHYSTAT_GBIT:
752 case MIIM_RTL8211B_PHYSTAT_100:
762 /* Parse the cis8201's status register for speed and duplex
765 static uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
769 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
774 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
776 case MIIM_CIS8201_AUXCONSTAT_GBIT:
779 case MIIM_CIS8201_AUXCONSTAT_100:
790 /* Parse the vsc8244's status register for speed and duplex
793 static uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
797 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
802 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
804 case MIIM_VSC8244_AUXCONSTAT_GBIT:
807 case MIIM_VSC8244_AUXCONSTAT_100:
818 /* Parse the DM9161's status register for speed and duplex
821 static uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
823 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
828 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
837 * Hack to write all 4 PHYs with the LED values
839 static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
842 volatile tsec_mdio_t *regbase = priv->phyregs;
843 int timeout = 1000000;
845 for (phyid = 0; phyid < 4; phyid++) {
846 regbase->miimadd = (phyid << 8) | mii_reg;
847 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
851 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
854 return MIIM_CIS8204_SLEDCON_INIT;
857 static uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
859 if (priv->flags & TSEC_REDUCED)
860 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
862 return MIIM_CIS8204_EPHYCON_INIT;
865 static uint mii_m88e1111s_setmode(uint mii_reg, struct tsec_private *priv)
867 uint mii_data = read_phy_reg(priv, mii_reg);
869 if (priv->flags & TSEC_REDUCED)
870 mii_data = (mii_data & 0xfff0) | 0x000b;
874 /* Initialized required registers to appropriate values, zeroing
875 * those we don't care about (unless zero is bad, in which case,
876 * choose a more appropriate value)
878 static void init_registers(volatile tsec_t * regs)
881 regs->ievent = IEVENT_INIT_CLEAR;
883 regs->imask = IMASK_INIT_CLEAR;
885 regs->hash.iaddr0 = 0;
886 regs->hash.iaddr1 = 0;
887 regs->hash.iaddr2 = 0;
888 regs->hash.iaddr3 = 0;
889 regs->hash.iaddr4 = 0;
890 regs->hash.iaddr5 = 0;
891 regs->hash.iaddr6 = 0;
892 regs->hash.iaddr7 = 0;
894 regs->hash.gaddr0 = 0;
895 regs->hash.gaddr1 = 0;
896 regs->hash.gaddr2 = 0;
897 regs->hash.gaddr3 = 0;
898 regs->hash.gaddr4 = 0;
899 regs->hash.gaddr5 = 0;
900 regs->hash.gaddr6 = 0;
901 regs->hash.gaddr7 = 0;
903 regs->rctrl = 0x00000000;
905 /* Init RMON mib registers */
906 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
908 regs->rmon.cam1 = 0xffffffff;
909 regs->rmon.cam2 = 0xffffffff;
911 regs->mrblr = MRBLR_INIT_SETTINGS;
913 regs->minflr = MINFLR_INIT_SETTINGS;
915 regs->attr = ATTR_INIT_SETTINGS;
916 regs->attreli = ATTRELI_INIT_SETTINGS;
920 /* Configure maccfg2 based on negotiated speed and duplex
921 * reported by PHY handling code
923 static void adjust_link(struct eth_device *dev)
925 struct tsec_private *priv = (struct tsec_private *)dev->priv;
926 volatile tsec_t *regs = priv->regs;
929 if (priv->duplexity != 0)
930 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
932 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
934 switch (priv->speed) {
936 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
941 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
944 /* Set R100 bit in all modes although
945 * it is only used in RGMII mode
947 if (priv->speed == 100)
948 regs->ecntrl |= ECNTRL_R100;
950 regs->ecntrl &= ~(ECNTRL_R100);
953 printf("%s: Speed was bad\n", dev->name);
957 printf("Speed: %d, %s duplex%s\n", priv->speed,
958 (priv->duplexity) ? "full" : "half",
959 (priv->flags & TSEC_FIBER) ? ", fiber mode" : "");
962 printf("%s: No link.\n", dev->name);
966 /* Set up the buffers and their descriptors, and bring up the
969 static void startup_tsec(struct eth_device *dev)
972 struct tsec_private *priv = (struct tsec_private *)dev->priv;
973 volatile tsec_t *regs = priv->regs;
975 /* Point to the buffer descriptors */
976 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
977 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
979 /* Initialize the Rx Buffer descriptors */
980 for (i = 0; i < PKTBUFSRX; i++) {
981 rtx.rxbd[i].status = RXBD_EMPTY;
982 rtx.rxbd[i].length = 0;
983 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
985 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
987 /* Initialize the TX Buffer Descriptors */
988 for (i = 0; i < TX_BUF_CNT; i++) {
989 rtx.txbd[i].status = 0;
990 rtx.txbd[i].length = 0;
991 rtx.txbd[i].bufPtr = 0;
993 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
995 /* Start up the PHY */
997 phy_run_commands(priv, priv->phyinfo->startup);
1001 /* Enable Transmit and Receive */
1002 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1004 /* Tell the DMA it is clear to go */
1005 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
1006 regs->tstat = TSTAT_CLEAR_THALT;
1007 regs->rstat = RSTAT_CLEAR_RHALT;
1008 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
1011 /* This returns the status bits of the device. The return value
1012 * is never checked, and this is what the 8260 driver did, so we
1013 * do the same. Presumably, this would be zero if there were no
1016 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
1020 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1021 volatile tsec_t *regs = priv->regs;
1023 /* Find an empty buffer descriptor */
1024 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
1025 if (i >= TOUT_LOOP) {
1026 debug("%s: tsec: tx buffers full\n", dev->name);
1031 rtx.txbd[txIdx].bufPtr = (uint) packet;
1032 rtx.txbd[txIdx].length = length;
1033 rtx.txbd[txIdx].status |=
1034 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
1036 /* Tell the DMA to go */
1037 regs->tstat = TSTAT_CLEAR_THALT;
1039 /* Wait for buffer to be transmitted */
1040 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
1041 if (i >= TOUT_LOOP) {
1042 debug("%s: tsec: tx error\n", dev->name);
1047 txIdx = (txIdx + 1) % TX_BUF_CNT;
1048 result = rtx.txbd[txIdx].status & TXBD_STATS;
1053 static int tsec_recv(struct eth_device *dev)
1056 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1057 volatile tsec_t *regs = priv->regs;
1059 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
1061 length = rtx.rxbd[rxIdx].length;
1063 /* Send the packet up if there were no errors */
1064 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
1065 NetReceive(NetRxPackets[rxIdx], length - 4);
1067 printf("Got error %x\n",
1068 (rtx.rxbd[rxIdx].status & RXBD_STATS));
1071 rtx.rxbd[rxIdx].length = 0;
1073 /* Set the wrap bit if this is the last element in the list */
1074 rtx.rxbd[rxIdx].status =
1075 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
1077 rxIdx = (rxIdx + 1) % PKTBUFSRX;
1080 if (regs->ievent & IEVENT_BSY) {
1081 regs->ievent = IEVENT_BSY;
1082 regs->rstat = RSTAT_CLEAR_RHALT;
1089 /* Stop the interface */
1090 static void tsec_halt(struct eth_device *dev)
1092 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1093 volatile tsec_t *regs = priv->regs;
1095 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
1096 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
1098 while ((regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))
1099 != (IEVENT_GRSC | IEVENT_GTSC)) ;
1101 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
1103 /* Shut down the PHY, as needed */
1105 phy_run_commands(priv, priv->phyinfo->shutdown);
1108 static struct phy_info phy_info_M88E1149S = {
1112 (struct phy_cmd[]) { /* config */
1113 /* Reset and configure the PHY */
1114 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1116 {0x1e, 0x200c, NULL},
1119 {0x1e, 0x100, NULL},
1120 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1121 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1122 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1123 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1126 (struct phy_cmd[]) { /* startup */
1127 /* Status is read once to clear old link state */
1128 {MIIM_STATUS, miim_read, NULL},
1129 /* Auto-negotiate */
1130 {MIIM_STATUS, miim_read, &mii_parse_sr},
1131 /* Read the status */
1132 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1135 (struct phy_cmd[]) { /* shutdown */
1140 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
1141 static struct phy_info phy_info_BCM5461S = {
1142 0x02060c1, /* 5461 ID */
1143 "Broadcom BCM5461S",
1144 0, /* not clear to me what minor revisions we can shift away */
1145 (struct phy_cmd[]) { /* config */
1146 /* Reset and configure the PHY */
1147 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1148 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1149 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1150 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1151 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1154 (struct phy_cmd[]) { /* startup */
1155 /* Status is read once to clear old link state */
1156 {MIIM_STATUS, miim_read, NULL},
1157 /* Auto-negotiate */
1158 {MIIM_STATUS, miim_read, &mii_parse_sr},
1159 /* Read the status */
1160 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1163 (struct phy_cmd[]) { /* shutdown */
1168 static struct phy_info phy_info_BCM5464S = {
1169 0x02060b1, /* 5464 ID */
1170 "Broadcom BCM5464S",
1171 0, /* not clear to me what minor revisions we can shift away */
1172 (struct phy_cmd[]) { /* config */
1173 /* Reset and configure the PHY */
1174 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1175 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1176 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1177 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1178 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1181 (struct phy_cmd[]) { /* startup */
1182 /* Status is read once to clear old link state */
1183 {MIIM_STATUS, miim_read, NULL},
1184 /* Auto-negotiate */
1185 {MIIM_STATUS, miim_read, &mii_parse_sr},
1186 /* Read the status */
1187 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
1190 (struct phy_cmd[]) { /* shutdown */
1195 static struct phy_info phy_info_BCM5482S = {
1197 "Broadcom BCM5482S",
1199 (struct phy_cmd[]) { /* config */
1200 /* Reset and configure the PHY */
1201 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1202 /* Setup read from auxilary control shadow register 7 */
1203 {MIIM_BCM54xx_AUXCNTL, MIIM_BCM54xx_AUXCNTL_ENCODE(7), NULL},
1204 /* Read Misc Control register and or in Ethernet@Wirespeed */
1205 {MIIM_BCM54xx_AUXCNTL, 0, &mii_BCM54xx_wirespeed},
1206 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1207 /* Initial config/enable of secondary SerDes interface */
1208 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf), NULL},
1209 /* Write intial value to secondary SerDes Contol */
1210 {MIIM_BCM54XX_EXP_SEL, MIIM_BCM54XX_EXP_SEL_SSD | 0, NULL},
1211 {MIIM_BCM54XX_EXP_DATA, MIIM_CONTROL_RESTART, NULL},
1212 /* Enable copper/fiber auto-detect */
1213 {MIIM_BCM54XX_SHD, MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)},
1216 (struct phy_cmd[]) { /* startup */
1217 /* Status is read once to clear old link state */
1218 {MIIM_STATUS, miim_read, NULL},
1219 /* Determine copper/fiber, auto-negotiate, and read the result */
1220 {MIIM_STATUS, miim_read, &mii_parse_BCM5482_sr},
1223 (struct phy_cmd[]) { /* shutdown */
1228 static struct phy_info phy_info_M88E1011S = {
1232 (struct phy_cmd[]) { /* config */
1233 /* Reset and configure the PHY */
1234 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1236 {0x1e, 0x200c, NULL},
1239 {0x1e, 0x100, NULL},
1240 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1241 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1242 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1243 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1246 (struct phy_cmd[]) { /* startup */
1247 /* Status is read once to clear old link state */
1248 {MIIM_STATUS, miim_read, NULL},
1249 /* Auto-negotiate */
1250 {MIIM_STATUS, miim_read, &mii_parse_sr},
1251 /* Read the status */
1252 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1255 (struct phy_cmd[]) { /* shutdown */
1260 static struct phy_info phy_info_M88E1111S = {
1264 (struct phy_cmd[]) { /* config */
1265 /* Reset and configure the PHY */
1266 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1267 {0x1b, 0x848f, &mii_m88e1111s_setmode},
1268 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1269 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1270 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1271 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1272 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1275 (struct phy_cmd[]) { /* startup */
1276 /* Status is read once to clear old link state */
1277 {MIIM_STATUS, miim_read, NULL},
1278 /* Auto-negotiate */
1279 {MIIM_STATUS, miim_read, &mii_parse_sr},
1280 /* Read the status */
1281 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1284 (struct phy_cmd[]) { /* shutdown */
1289 static struct phy_info phy_info_M88E1118 = {
1293 (struct phy_cmd[]) { /* config */
1294 /* Reset and configure the PHY */
1295 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1296 {0x16, 0x0002, NULL}, /* Change Page Number */
1297 {0x15, 0x1070, NULL}, /* Delay RGMII TX and RX */
1298 {0x16, 0x0003, NULL}, /* Change Page Number */
1299 {0x10, 0x021e, NULL}, /* Adjust LED control */
1300 {0x16, 0x0000, NULL}, /* Change Page Number */
1301 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1302 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1303 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1304 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1307 (struct phy_cmd[]) { /* startup */
1308 {0x16, 0x0000, NULL}, /* Change Page Number */
1309 /* Status is read once to clear old link state */
1310 {MIIM_STATUS, miim_read, NULL},
1311 /* Auto-negotiate */
1312 {MIIM_STATUS, miim_read, &mii_parse_sr},
1313 /* Read the status */
1314 {MIIM_88E1011_PHY_STATUS, miim_read,
1315 &mii_parse_88E1011_psr},
1318 (struct phy_cmd[]) { /* shutdown */
1324 * Since to access LED register we need do switch the page, we
1325 * do LED configuring in the miim_read-like function as follows
1327 static uint mii_88E1121_set_led (uint mii_reg, struct tsec_private *priv)
1331 /* Switch the page to access the led register */
1332 pg = read_phy_reg(priv, MIIM_88E1121_PHY_PAGE);
1333 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, MIIM_88E1121_PHY_LED_PAGE);
1335 /* Configure leds */
1336 write_phy_reg(priv, MIIM_88E1121_PHY_LED_CTRL,
1337 MIIM_88E1121_PHY_LED_DEF);
1339 /* Restore the page pointer */
1340 write_phy_reg(priv, MIIM_88E1121_PHY_PAGE, pg);
1344 static struct phy_info phy_info_M88E1121R = {
1348 (struct phy_cmd[]) { /* config */
1349 /* Reset and configure the PHY */
1350 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1351 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1352 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1353 /* Configure leds */
1354 {MIIM_88E1121_PHY_LED_CTRL, miim_read, &mii_88E1121_set_led},
1355 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1356 /* Disable IRQs and de-assert interrupt */
1357 {MIIM_88E1121_PHY_IRQ_EN, 0, NULL},
1358 {MIIM_88E1121_PHY_IRQ_STATUS, miim_read, NULL},
1361 (struct phy_cmd[]) { /* startup */
1362 /* Status is read once to clear old link state */
1363 {MIIM_STATUS, miim_read, NULL},
1364 {MIIM_STATUS, miim_read, &mii_parse_sr},
1365 {MIIM_STATUS, miim_read, &mii_parse_link},
1368 (struct phy_cmd[]) { /* shutdown */
1373 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1375 uint mii_data = read_phy_reg(priv, mii_reg);
1377 /* Setting MIIM_88E1145_PHY_EXT_CR */
1378 if (priv->flags & TSEC_REDUCED)
1380 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1385 static struct phy_info phy_info_M88E1145 = {
1389 (struct phy_cmd[]) { /* config */
1391 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1399 /* Configure the PHY */
1400 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1401 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1402 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
1403 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1404 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1405 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1408 (struct phy_cmd[]) { /* startup */
1409 /* Status is read once to clear old link state */
1410 {MIIM_STATUS, miim_read, NULL},
1411 /* Auto-negotiate */
1412 {MIIM_STATUS, miim_read, &mii_parse_sr},
1413 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
1414 /* Read the Status */
1415 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
1418 (struct phy_cmd[]) { /* shutdown */
1423 static struct phy_info phy_info_cis8204 = {
1427 (struct phy_cmd[]) { /* config */
1428 /* Override PHY config settings */
1429 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1430 /* Configure some basic stuff */
1431 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1432 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1433 &mii_cis8204_fixled},
1434 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1435 &mii_cis8204_setmode},
1438 (struct phy_cmd[]) { /* startup */
1439 /* Read the Status (2x to make sure link is right) */
1440 {MIIM_STATUS, miim_read, NULL},
1441 /* Auto-negotiate */
1442 {MIIM_STATUS, miim_read, &mii_parse_sr},
1443 /* Read the status */
1444 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1447 (struct phy_cmd[]) { /* shutdown */
1453 static struct phy_info phy_info_cis8201 = {
1457 (struct phy_cmd[]) { /* config */
1458 /* Override PHY config settings */
1459 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1460 /* Set up the interface mode */
1461 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1462 /* Configure some basic stuff */
1463 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1466 (struct phy_cmd[]) { /* startup */
1467 /* Read the Status (2x to make sure link is right) */
1468 {MIIM_STATUS, miim_read, NULL},
1469 /* Auto-negotiate */
1470 {MIIM_STATUS, miim_read, &mii_parse_sr},
1471 /* Read the status */
1472 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1475 (struct phy_cmd[]) { /* shutdown */
1480 static struct phy_info phy_info_VSC8211 = {
1484 (struct phy_cmd[]) { /* config */
1485 /* Override PHY config settings */
1486 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1487 /* Set up the interface mode */
1488 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
1489 /* Configure some basic stuff */
1490 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1493 (struct phy_cmd[]) { /* startup */
1494 /* Read the Status (2x to make sure link is right) */
1495 {MIIM_STATUS, miim_read, NULL},
1496 /* Auto-negotiate */
1497 {MIIM_STATUS, miim_read, &mii_parse_sr},
1498 /* Read the status */
1499 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
1502 (struct phy_cmd[]) { /* shutdown */
1507 static struct phy_info phy_info_VSC8244 = {
1511 (struct phy_cmd[]) { /* config */
1512 /* Override PHY config settings */
1513 /* Configure some basic stuff */
1514 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1517 (struct phy_cmd[]) { /* startup */
1518 /* Read the Status (2x to make sure link is right) */
1519 {MIIM_STATUS, miim_read, NULL},
1520 /* Auto-negotiate */
1521 {MIIM_STATUS, miim_read, &mii_parse_sr},
1522 /* Read the status */
1523 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1526 (struct phy_cmd[]) { /* shutdown */
1531 static struct phy_info phy_info_VSC8641 = {
1535 (struct phy_cmd[]) { /* config */
1536 /* Configure some basic stuff */
1537 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1540 (struct phy_cmd[]) { /* startup */
1541 /* Read the Status (2x to make sure link is right) */
1542 {MIIM_STATUS, miim_read, NULL},
1543 /* Auto-negotiate */
1544 {MIIM_STATUS, miim_read, &mii_parse_sr},
1545 /* Read the status */
1546 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1549 (struct phy_cmd[]) { /* shutdown */
1554 static struct phy_info phy_info_VSC8221 = {
1558 (struct phy_cmd[]) { /* config */
1559 /* Configure some basic stuff */
1560 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1563 (struct phy_cmd[]) { /* startup */
1564 /* Read the Status (2x to make sure link is right) */
1565 {MIIM_STATUS, miim_read, NULL},
1566 /* Auto-negotiate */
1567 {MIIM_STATUS, miim_read, &mii_parse_sr},
1568 /* Read the status */
1569 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1572 (struct phy_cmd[]) { /* shutdown */
1577 static struct phy_info phy_info_VSC8601 = {
1581 (struct phy_cmd[]) { /* config */
1582 /* Override PHY config settings */
1583 /* Configure some basic stuff */
1584 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1585 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
1586 {MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
1587 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
1588 {MIIM_EXT_PAGE_ACCESS,1,NULL},
1589 #define VSC8101_SKEW \
1590 (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12)
1591 {MIIM_VSC8601_SKEW_CTRL,VSC8101_SKEW,NULL},
1592 {MIIM_EXT_PAGE_ACCESS,0,NULL},
1595 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1596 {MIIM_CONTROL, MIIM_CONTROL_RESTART, &mii_cr_init},
1599 (struct phy_cmd[]) { /* startup */
1600 /* Read the Status (2x to make sure link is right) */
1601 {MIIM_STATUS, miim_read, NULL},
1602 /* Auto-negotiate */
1603 {MIIM_STATUS, miim_read, &mii_parse_sr},
1604 /* Read the status */
1605 {MIIM_VSC8244_AUX_CONSTAT, miim_read, &mii_parse_vsc8244},
1608 (struct phy_cmd[]) { /* shutdown */
1613 static struct phy_info phy_info_dm9161 = {
1617 (struct phy_cmd[]) { /* config */
1618 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1619 /* Do not bypass the scrambler/descrambler */
1620 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1621 /* Clear 10BTCSR to default */
1622 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
1623 /* Configure some basic stuff */
1624 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1625 /* Restart Auto Negotiation */
1626 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1629 (struct phy_cmd[]) { /* startup */
1630 /* Status is read once to clear old link state */
1631 {MIIM_STATUS, miim_read, NULL},
1632 /* Auto-negotiate */
1633 {MIIM_STATUS, miim_read, &mii_parse_sr},
1634 /* Read the status */
1635 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
1638 (struct phy_cmd[]) { /* shutdown */
1644 static struct phy_info phy_info_ksz804 = {
1646 "Micrel KSZ804 PHY",
1648 (struct phy_cmd[]) { /* config */
1649 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1650 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1653 (struct phy_cmd[]) { /* startup */
1654 {PHY_BMSR, miim_read, NULL},
1655 {PHY_BMSR, miim_read, &mii_parse_sr},
1656 {PHY_BMSR, miim_read, &mii_parse_link},
1659 (struct phy_cmd[]) { /* shutdown */
1664 /* a generic flavor. */
1665 static struct phy_info phy_info_generic = {
1667 "Unknown/Generic PHY",
1669 (struct phy_cmd[]) { /* config */
1670 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1671 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1674 (struct phy_cmd[]) { /* startup */
1675 {PHY_BMSR, miim_read, NULL},
1676 {PHY_BMSR, miim_read, &mii_parse_sr},
1677 {PHY_BMSR, miim_read, &mii_parse_link},
1680 (struct phy_cmd[]) { /* shutdown */
1685 static uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1689 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1692 case MIIM_LXT971_SR2_10HDX:
1694 priv->duplexity = 0;
1696 case MIIM_LXT971_SR2_10FDX:
1698 priv->duplexity = 1;
1700 case MIIM_LXT971_SR2_100HDX:
1702 priv->duplexity = 0;
1706 priv->duplexity = 1;
1710 priv->duplexity = 0;
1716 static struct phy_info phy_info_lxt971 = {
1720 (struct phy_cmd[]) { /* config */
1721 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1724 (struct phy_cmd[]) { /* startup - enable interrupts */
1725 /* { 0x12, 0x00f2, NULL }, */
1726 {MIIM_STATUS, miim_read, NULL},
1727 {MIIM_STATUS, miim_read, &mii_parse_sr},
1728 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1731 (struct phy_cmd[]) { /* shutdown - disable interrupts */
1736 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1739 static uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1741 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1743 case MIIM_DP83865_SPD_1000:
1747 case MIIM_DP83865_SPD_100:
1757 if (mii_reg & MIIM_DP83865_DPX_FULL)
1758 priv->duplexity = 1;
1760 priv->duplexity = 0;
1765 static struct phy_info phy_info_dp83865 = {
1769 (struct phy_cmd[]) { /* config */
1770 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1773 (struct phy_cmd[]) { /* startup */
1774 /* Status is read once to clear old link state */
1775 {MIIM_STATUS, miim_read, NULL},
1776 /* Auto-negotiate */
1777 {MIIM_STATUS, miim_read, &mii_parse_sr},
1778 /* Read the link and auto-neg status */
1779 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
1782 (struct phy_cmd[]) { /* shutdown */
1787 static struct phy_info phy_info_rtl8211b = {
1791 (struct phy_cmd[]) { /* config */
1792 /* Reset and configure the PHY */
1793 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1794 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1795 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1796 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1797 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1800 (struct phy_cmd[]) { /* startup */
1801 /* Status is read once to clear old link state */
1802 {MIIM_STATUS, miim_read, NULL},
1803 /* Auto-negotiate */
1804 {MIIM_STATUS, miim_read, &mii_parse_sr},
1805 /* Read the status */
1806 {MIIM_RTL8211B_PHY_STATUS, miim_read, &mii_parse_RTL8211B_sr},
1809 (struct phy_cmd[]) { /* shutdown */
1814 static struct phy_info *phy_info[] = {
1820 &phy_info_M88E1011S,
1821 &phy_info_M88E1111S,
1823 &phy_info_M88E1121R,
1825 &phy_info_M88E1149S,
1836 &phy_info_generic, /* must be last; has ID 0 and 32 bit mask */
1840 /* Grab the identifier of the device's PHY, and search through
1841 * all of the known PHYs to see if one matches. If so, return
1842 * it, if not, return NULL
1844 static struct phy_info *get_phy_info(struct eth_device *dev)
1846 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1847 uint phy_reg, phy_ID;
1849 struct phy_info *theInfo = NULL;
1851 /* Grab the bits from PHYIR1, and put them in the upper half */
1852 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1853 phy_ID = (phy_reg & 0xffff) << 16;
1855 /* Grab the bits from PHYIR2, and put them in the lower half */
1856 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1857 phy_ID |= (phy_reg & 0xffff);
1859 /* loop through all the known PHY types, and find one that */
1860 /* matches the ID we read from the PHY. */
1861 for (i = 0; phy_info[i]; i++) {
1862 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1863 theInfo = phy_info[i];
1868 if (theInfo == &phy_info_generic) {
1869 printf("%s: No support for PHY id %x; assuming generic\n",
1872 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1878 /* Execute the given series of commands on the given device's
1879 * PHY, running functions as necessary
1881 static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1885 volatile tsec_mdio_t *phyregs = priv->phyregs;
1887 phyregs->miimcfg = MIIMCFG_RESET;
1889 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1891 while (phyregs->miimind & MIIMIND_BUSY) ;
1893 for (i = 0; cmd->mii_reg != miim_end; i++) {
1894 if (cmd->mii_data == miim_read) {
1895 result = read_phy_reg(priv, cmd->mii_reg);
1897 if (cmd->funct != NULL)
1898 (*(cmd->funct)) (result, priv);
1901 if (cmd->funct != NULL)
1902 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1904 result = cmd->mii_data;
1906 write_phy_reg(priv, cmd->mii_reg, result);
1913 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1914 && !defined(BITBANGMII)
1917 * Read a MII PHY register.
1922 static int tsec_miiphy_read(const char *devname, unsigned char addr,
1923 unsigned char reg, unsigned short *value)
1926 struct tsec_private *priv = privlist[0];
1929 printf("Can't read PHY at address %d\n", addr);
1933 ret = (unsigned short)tsec_local_mdio_read(priv->phyregs, addr, reg);
1940 * Write a MII PHY register.
1945 static int tsec_miiphy_write(const char *devname, unsigned char addr,
1946 unsigned char reg, unsigned short value)
1948 struct tsec_private *priv = privlist[0];
1951 printf("Can't write PHY at address %d\n", addr);
1955 tsec_local_mdio_write(priv->phyregs, addr, reg, value);
1962 #ifdef CONFIG_MCAST_TFTP
1964 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
1966 /* Set the appropriate hash bit for the given addr */
1968 /* The algorithm works like so:
1969 * 1) Take the Destination Address (ie the multicast address), and
1970 * do a CRC on it (little endian), and reverse the bits of the
1972 * 2) Use the 8 most significant bits as a hash into a 256-entry
1973 * table. The table is controlled through 8 32-bit registers:
1974 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1975 * gaddr7. This means that the 3 most significant bits in the
1976 * hash index which gaddr register to use, and the 5 other bits
1977 * indicate which bit (assuming an IBM numbering scheme, which
1978 * for PowerPC (tm) is usually the case) in the tregister holds
1981 tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
1983 struct tsec_private *priv = privlist[1];
1984 volatile tsec_t *regs = priv->regs;
1985 volatile u32 *reg_array, value;
1986 u8 result, whichbit, whichreg;
1988 result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
1989 whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
1990 whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
1991 value = (1 << (31-whichbit));
1993 reg_array = &(regs->hash.gaddr0);
1996 reg_array[whichreg] |= value;
1998 reg_array[whichreg] &= ~value;
2002 #endif /* Multicast TFTP ? */