2 * Freescale Three Speed Ethernet Controller driver
4 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
5 * (C) Copyright 2003, Motorola, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
19 #include <linux/errno.h>
20 #include <asm/processor.h>
24 /* Default initializations for TSEC controllers. */
26 static struct tsec_info_struct tsec_info[] = {
28 STD_TSEC_INFO(1), /* TSEC1 */
31 STD_TSEC_INFO(2), /* TSEC2 */
33 #ifdef CONFIG_MPC85XX_FEC
35 .regs = TSEC_GET_REGS(2, 0x2000),
36 .devname = CONFIG_MPC85XX_FEC_NAME,
37 .phyaddr = FEC_PHY_ADDR,
39 .mii_devname = DEFAULT_MII_NAME
43 STD_TSEC_INFO(3), /* TSEC3 */
46 STD_TSEC_INFO(4), /* TSEC4 */
49 #endif /* CONFIG_DM_ETH */
51 #define TBIANA_SETTINGS ( \
52 TBIANA_ASYMMETRIC_PAUSE \
53 | TBIANA_SYMMETRIC_PAUSE \
54 | TBIANA_FULL_DUPLEX \
57 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
58 #ifndef CONFIG_TSEC_TBICR_SETTINGS
59 #define CONFIG_TSEC_TBICR_SETTINGS ( \
65 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
67 /* Configure the TBI for SGMII operation */
68 static void tsec_configure_serdes(struct tsec_private *priv)
71 * Access TBI PHY registers at given TSEC register offset as opposed
72 * to the register offset used for external PHY accesses
74 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
75 0, TBI_ANA, TBIANA_SETTINGS);
76 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
77 0, TBI_TBICON, TBICON_CLK_SELECT);
78 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
79 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
82 #ifdef CONFIG_MCAST_TFTP
84 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
86 /* Set the appropriate hash bit for the given addr */
89 * The algorithm works like so:
90 * 1) Take the Destination Address (ie the multicast address), and
91 * do a CRC on it (little endian), and reverse the bits of the
93 * 2) Use the 8 most significant bits as a hash into a 256-entry
94 * table. The table is controlled through 8 32-bit registers:
95 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
96 * 255. This means that the 3 most significant bits in the
97 * hash index which gaddr register to use, and the 5 other bits
98 * indicate which bit (assuming an IBM numbering scheme, which
99 * for PowerPC (tm) is usually the case) in the register holds
102 #ifndef CONFIG_DM_ETH
103 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
105 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
108 struct tsec_private *priv = (struct tsec_private *)dev->priv;
109 struct tsec __iomem *regs = priv->regs;
111 u8 whichbit, whichreg;
113 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
114 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
115 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
117 value = BIT(31 - whichbit);
120 setbits_be32(®s->hash.gaddr0 + whichreg, value);
122 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
126 #endif /* Multicast TFTP ? */
129 * Initialized required registers to appropriate values, zeroing
130 * those we don't care about (unless zero is bad, in which case,
131 * choose a more appropriate value)
133 static void init_registers(struct tsec __iomem *regs)
136 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
138 out_be32(®s->imask, IMASK_INIT_CLEAR);
140 out_be32(®s->hash.iaddr0, 0);
141 out_be32(®s->hash.iaddr1, 0);
142 out_be32(®s->hash.iaddr2, 0);
143 out_be32(®s->hash.iaddr3, 0);
144 out_be32(®s->hash.iaddr4, 0);
145 out_be32(®s->hash.iaddr5, 0);
146 out_be32(®s->hash.iaddr6, 0);
147 out_be32(®s->hash.iaddr7, 0);
149 out_be32(®s->hash.gaddr0, 0);
150 out_be32(®s->hash.gaddr1, 0);
151 out_be32(®s->hash.gaddr2, 0);
152 out_be32(®s->hash.gaddr3, 0);
153 out_be32(®s->hash.gaddr4, 0);
154 out_be32(®s->hash.gaddr5, 0);
155 out_be32(®s->hash.gaddr6, 0);
156 out_be32(®s->hash.gaddr7, 0);
158 out_be32(®s->rctrl, 0x00000000);
160 /* Init RMON mib registers */
161 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
163 out_be32(®s->rmon.cam1, 0xffffffff);
164 out_be32(®s->rmon.cam2, 0xffffffff);
166 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
168 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
170 out_be32(®s->attr, ATTR_INIT_SETTINGS);
171 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
175 * Configure maccfg2 based on negotiated speed and duplex
176 * reported by PHY handling code
178 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
180 struct tsec __iomem *regs = priv->regs;
184 printf("%s: No link.\n", phydev->dev->name);
188 /* clear all bits relative with interface mode */
189 ecntrl = in_be32(®s->ecntrl);
190 ecntrl &= ~ECNTRL_R100;
192 maccfg2 = in_be32(®s->maccfg2);
193 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
196 maccfg2 |= MACCFG2_FULL_DUPLEX;
198 switch (phydev->speed) {
200 maccfg2 |= MACCFG2_GMII;
204 maccfg2 |= MACCFG2_MII;
207 * Set R100 bit in all modes although
208 * it is only used in RGMII mode
210 if (phydev->speed == 100)
211 ecntrl |= ECNTRL_R100;
214 printf("%s: Speed was bad\n", phydev->dev->name);
218 out_be32(®s->ecntrl, ecntrl);
219 out_be32(®s->maccfg2, maccfg2);
221 printf("Speed: %d, %s duplex%s\n", phydev->speed,
222 (phydev->duplex) ? "full" : "half",
223 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
227 * This returns the status bits of the device. The return value
228 * is never checked, and this is what the 8260 driver did, so we
229 * do the same. Presumably, this would be zero if there were no
232 #ifndef CONFIG_DM_ETH
233 static int tsec_send(struct eth_device *dev, void *packet, int length)
235 static int tsec_send(struct udevice *dev, void *packet, int length)
238 struct tsec_private *priv = (struct tsec_private *)dev->priv;
239 struct tsec __iomem *regs = priv->regs;
244 /* Find an empty buffer descriptor */
246 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
248 if (i >= TOUT_LOOP) {
249 debug("%s: tsec: tx buffers full\n", dev->name);
254 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
255 out_be16(&priv->txbd[priv->tx_idx].length, length);
256 status = in_be16(&priv->txbd[priv->tx_idx].status);
257 out_be16(&priv->txbd[priv->tx_idx].status, status |
258 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
260 /* Tell the DMA to go */
261 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
263 /* Wait for buffer to be transmitted */
265 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
267 if (i >= TOUT_LOOP) {
268 debug("%s: tsec: tx error\n", dev->name);
273 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
274 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
279 #ifndef CONFIG_DM_ETH
280 static int tsec_recv(struct eth_device *dev)
282 struct tsec_private *priv = (struct tsec_private *)dev->priv;
283 struct tsec __iomem *regs = priv->regs;
285 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
286 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
287 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
288 uchar *packet = net_rx_packets[priv->rx_idx];
290 /* Send the packet up if there were no errors */
291 if (!(status & RXBD_STATS))
292 net_process_received_packet(packet, length - 4);
294 printf("Got error %x\n", (status & RXBD_STATS));
296 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
299 /* Set the wrap bit if this is the last element in the list */
300 if ((priv->rx_idx + 1) == PKTBUFSRX)
302 out_be16(&priv->rxbd[priv->rx_idx].status, status);
304 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
307 if (in_be32(®s->ievent) & IEVENT_BSY) {
308 out_be32(®s->ievent, IEVENT_BSY);
309 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
315 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
317 struct tsec_private *priv = (struct tsec_private *)dev->priv;
318 struct tsec __iomem *regs = priv->regs;
321 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
322 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
323 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
326 /* Send the packet up if there were no errors */
327 if (!(status & RXBD_STATS)) {
328 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
329 *packetp = (uchar *)buf;
332 printf("Got error %x\n", (status & RXBD_STATS));
336 if (in_be32(®s->ievent) & IEVENT_BSY) {
337 out_be32(®s->ievent, IEVENT_BSY);
338 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
344 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
346 struct tsec_private *priv = (struct tsec_private *)dev->priv;
349 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
352 /* Set the wrap bit if this is the last element in the list */
353 if ((priv->rx_idx + 1) == PKTBUFSRX)
355 out_be16(&priv->rxbd[priv->rx_idx].status, status);
357 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
363 /* Stop the interface */
364 #ifndef CONFIG_DM_ETH
365 static void tsec_halt(struct eth_device *dev)
367 static void tsec_halt(struct udevice *dev)
370 struct tsec_private *priv = (struct tsec_private *)dev->priv;
371 struct tsec __iomem *regs = priv->regs;
373 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
374 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
376 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
377 != (IEVENT_GRSC | IEVENT_GTSC))
380 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
382 /* Shut down the PHY, as needed */
383 phy_shutdown(priv->phydev);
386 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
388 * When MACCFG1[Rx_EN] is enabled during system boot as part
389 * of the eTSEC port initialization sequence,
390 * the eTSEC Rx logic may not be properly initialized.
392 void redundant_init(struct tsec_private *priv)
394 struct tsec __iomem *regs = priv->regs;
397 static const u8 pkt[] = {
398 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
399 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
400 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
401 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
402 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
403 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
404 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
405 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
406 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
407 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
408 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
409 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
410 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
413 /* Enable promiscuous mode */
414 setbits_be32(®s->rctrl, 0x8);
415 /* Enable loopback mode */
416 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
417 /* Enable transmit and receive */
418 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
420 /* Tell the DMA it is clear to go */
421 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
422 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
423 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
424 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
429 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
431 /* Wait for buffer to be received */
433 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
435 if (t >= 10 * TOUT_LOOP) {
436 printf("%s: tsec: rx error\n", priv->dev->name);
441 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
444 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
446 if ((priv->rx_idx + 1) == PKTBUFSRX)
448 out_be16(&priv->rxbd[priv->rx_idx].status, status);
449 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
451 if (in_be32(®s->ievent) & IEVENT_BSY) {
452 out_be32(®s->ievent, IEVENT_BSY);
453 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
456 printf("loopback recv packet error!\n");
457 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
459 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
461 } while ((count++ < 4) && (fail == 1));
464 panic("eTSEC init fail!\n");
465 /* Disable promiscuous mode */
466 clrbits_be32(®s->rctrl, 0x8);
467 /* Disable loopback mode */
468 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
473 * Set up the buffers and their descriptors, and bring up the
476 static void startup_tsec(struct tsec_private *priv)
478 struct tsec __iomem *regs = priv->regs;
482 /* reset the indices to zero */
485 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
489 /* Point to the buffer descriptors */
490 out_be32(®s->tbase, (u32)&priv->txbd[0]);
491 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
493 /* Initialize the Rx Buffer descriptors */
494 for (i = 0; i < PKTBUFSRX; i++) {
495 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
496 out_be16(&priv->rxbd[i].length, 0);
497 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
499 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
500 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
502 /* Initialize the TX Buffer Descriptors */
503 for (i = 0; i < TX_BUF_CNT; i++) {
504 out_be16(&priv->txbd[i].status, 0);
505 out_be16(&priv->txbd[i].length, 0);
506 out_be32(&priv->txbd[i].bufptr, 0);
508 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
509 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
511 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
513 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
514 redundant_init(priv);
516 /* Enable Transmit and Receive */
517 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
519 /* Tell the DMA it is clear to go */
520 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
521 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
522 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
523 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
527 * Initializes data structures and registers for the controller,
528 * and brings the interface up. Returns the link status, meaning
529 * that it returns success if the link is up, failure otherwise.
530 * This allows U-Boot to find the first active controller.
532 #ifndef CONFIG_DM_ETH
533 static int tsec_init(struct eth_device *dev, bd_t *bd)
535 static int tsec_init(struct udevice *dev)
538 struct tsec_private *priv = (struct tsec_private *)dev->priv;
540 struct eth_pdata *pdata = dev_get_platdata(dev);
542 struct tsec __iomem *regs = priv->regs;
546 /* Make sure the controller is stopped */
549 /* Init MACCFG2. Defaults to GMII */
550 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
553 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
556 * Copy the station address into the address registers.
557 * For a station address of 0x12345678ABCD in transmission
558 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
559 * MACnADDR2 is set to 0x34120000.
561 #ifndef CONFIG_DM_ETH
562 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
563 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
565 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
566 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
569 out_be32(®s->macstnaddr1, tempval);
571 #ifndef CONFIG_DM_ETH
572 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
574 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
577 out_be32(®s->macstnaddr2, tempval);
579 /* Clear out (for the most part) the other registers */
580 init_registers(regs);
582 /* Ready the device for tx/rx */
585 /* Start up the PHY */
586 ret = phy_startup(priv->phydev);
588 printf("Could not initialize PHY %s\n",
589 priv->phydev->dev->name);
593 adjust_link(priv, priv->phydev);
595 /* If there's no link, fail */
596 return priv->phydev->link ? 0 : -1;
599 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
601 struct tsec __iomem *regs = priv->regs;
604 ecntrl = in_be32(®s->ecntrl);
606 if (ecntrl & ECNTRL_SGMII_MODE)
607 return PHY_INTERFACE_MODE_SGMII;
609 if (ecntrl & ECNTRL_TBI_MODE) {
610 if (ecntrl & ECNTRL_REDUCED_MODE)
611 return PHY_INTERFACE_MODE_RTBI;
613 return PHY_INTERFACE_MODE_TBI;
616 if (ecntrl & ECNTRL_REDUCED_MODE) {
617 phy_interface_t interface;
619 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
620 return PHY_INTERFACE_MODE_RMII;
622 interface = priv->interface;
625 * This isn't autodetected, so it must
626 * be set by the platform code.
628 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
629 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
630 interface == PHY_INTERFACE_MODE_RGMII_RXID)
633 return PHY_INTERFACE_MODE_RGMII;
636 if (priv->flags & TSEC_GIGABIT)
637 return PHY_INTERFACE_MODE_GMII;
639 return PHY_INTERFACE_MODE_MII;
643 * Discover which PHY is attached to the device, and configure it
644 * properly. If the PHY is not recognized, then return 0
645 * (failure). Otherwise, return 1
647 static int init_phy(struct tsec_private *priv)
649 struct phy_device *phydev;
650 struct tsec __iomem *regs = priv->regs;
651 u32 supported = (SUPPORTED_10baseT_Half |
652 SUPPORTED_10baseT_Full |
653 SUPPORTED_100baseT_Half |
654 SUPPORTED_100baseT_Full);
656 if (priv->flags & TSEC_GIGABIT)
657 supported |= SUPPORTED_1000baseT_Full;
659 /* Assign a Physical address to the TBI */
660 out_be32(®s->tbipa, priv->tbiaddr);
662 priv->interface = tsec_get_interface(priv);
664 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
665 tsec_configure_serdes(priv);
667 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
672 phydev->supported &= supported;
673 phydev->advertising = phydev->supported;
675 priv->phydev = phydev;
682 #ifndef CONFIG_DM_ETH
684 * Initialize device structure. Returns success if PHY
685 * initialization succeeded (i.e. if it recognizes the PHY)
687 static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
689 struct eth_device *dev;
691 struct tsec_private *priv;
693 dev = (struct eth_device *)malloc(sizeof(*dev));
698 memset(dev, 0, sizeof(*dev));
700 priv = (struct tsec_private *)malloc(sizeof(*priv));
707 priv->regs = tsec_info->regs;
708 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
710 priv->phyaddr = tsec_info->phyaddr;
711 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
712 priv->flags = tsec_info->flags;
714 strcpy(dev->name, tsec_info->devname);
715 priv->interface = tsec_info->interface;
716 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
720 dev->init = tsec_init;
721 dev->halt = tsec_halt;
722 dev->send = tsec_send;
723 dev->recv = tsec_recv;
724 #ifdef CONFIG_MCAST_TFTP
725 dev->mcast = tsec_mcast_addr;
728 /* Tell U-Boot to get the addr from the env */
729 for (i = 0; i < 6; i++)
730 dev->enetaddr[i] = 0;
735 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
736 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
737 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
739 /* Try to initialize PHY here, and return */
740 return init_phy(priv);
744 * Initialize all the TSEC devices
746 * Returns the number of TSEC devices that were initialized
748 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
753 for (i = 0; i < num; i++) {
754 int ret = tsec_initialize(bis, &tsecs[i]);
763 int tsec_standard_init(bd_t *bis)
765 struct fsl_pq_mdio_info info;
767 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
768 info.name = DEFAULT_MII_NAME;
770 fsl_pq_mdio_init(bis, &info);
772 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
774 #else /* CONFIG_DM_ETH */
775 int tsec_probe(struct udevice *dev)
777 struct tsec_private *priv = dev_get_priv(dev);
778 struct eth_pdata *pdata = dev_get_platdata(dev);
779 struct fsl_pq_mdio_info mdio_info;
780 struct ofnode_phandle_args phandle_args;
782 const char *phy_mode;
785 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
786 priv->regs = (struct tsec *)pdata->iobase;
788 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
790 debug("phy-handle does not exist under tsec %s\n", dev->name);
793 int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
798 parent = ofnode_get_parent(phandle_args.node);
799 if (ofnode_valid(parent)) {
800 int reg = ofnode_read_u32_default(parent, "reg", 0);
801 priv->phyregs_sgmii = (struct tsec_mii_mng *)(reg + 0x520);
803 debug("No parent node for PHY?\n");
807 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
809 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
811 int reg = ofnode_read_u32_default(phandle_args.node, "reg",
812 CONFIG_SYS_TBIPA_VALUE);
816 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
818 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
819 if (pdata->phy_interface == -1) {
820 debug("Invalid PHY interface '%s'\n", phy_mode);
823 priv->interface = pdata->phy_interface;
825 /* Initialize flags */
826 priv->flags = TSEC_GIGABIT;
827 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
828 priv->flags |= TSEC_SGMII;
830 mdio_info.regs = priv->phyregs_sgmii;
831 mdio_info.name = (char *)dev->name;
832 ret = fsl_pq_mdio_init(NULL, &mdio_info);
837 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
838 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
839 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
842 priv->bus = miiphy_get_dev_by_name(dev->name);
844 /* Try to initialize PHY here, and return */
845 return !init_phy(priv);
848 int tsec_remove(struct udevice *dev)
850 struct tsec_private *priv = dev->priv;
853 mdio_unregister(priv->bus);
854 mdio_free(priv->bus);
859 static const struct eth_ops tsec_ops = {
863 .free_pkt = tsec_free_pkt,
865 #ifdef CONFIG_MCAST_TFTP
866 .mcast = tsec_mcast_addr,
870 static const struct udevice_id tsec_ids[] = {
871 { .compatible = "fsl,tsec" },
875 U_BOOT_DRIVER(eth_tsec) = {
878 .of_match = tsec_ids,
880 .remove = tsec_remove,
882 .priv_auto_alloc_size = sizeof(struct tsec_private),
883 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
884 .flags = DM_FLAG_ALLOC_PRIV_DMA,
886 #endif /* CONFIG_DM_ETH */