1 // SPDX-License-Identifier: GPL-2.0+
3 * Ethernet driver for TI K2HK EVM.
5 * (C) Copyright 2012-2014
6 * Texas Instruments Incorporated, <www.ti.com>
20 #include <asm/ti-common/keystone_nav.h>
21 #include <asm/ti-common/keystone_net.h>
22 #include <asm/ti-common/keystone_serdes.h>
23 #include <asm/arch/psc_defs.h>
25 #include "cpsw_mdio.h"
27 DECLARE_GLOBAL_DATA_PTR;
29 #ifdef KEYSTONE2_EMAC_GIG_ENABLE
30 #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
32 #define emac_gigabit_enable(x) /* no gigabit to enable */
35 #define RX_BUFF_NUMS 24
36 #define RX_BUFF_LEN 1520
37 #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
38 #define SGMII_ANEG_TIMEOUT 4000
40 static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
43 LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
44 LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
45 LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
46 LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
47 LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
48 LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
49 LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
50 LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
51 LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
52 LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
55 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
56 ((mac)[2] << 16) | ((mac)[3] << 24))
57 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
59 #ifdef CONFIG_KSNET_NETCP_V1_0
61 #define EMAC_EMACSW_BASE_OFS 0x90800
62 #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
64 /* CPSW Switch slave registers */
65 #define CPGMACSL_REG_SA_LO 0x10
66 #define CPGMACSL_REG_SA_HI 0x14
68 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
71 #elif defined(CONFIG_KSNET_NETCP_V1_5)
73 #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
75 /* CPSW Switch slave registers */
76 #define CPGMACSL_REG_SA_LO 0x308
77 #define CPGMACSL_REG_SA_HI 0x30c
79 #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
87 struct phy_device *phydev;
88 struct mii_dev *mdio_bus;
90 phy_interface_t phy_if;
94 struct rx_buff_desc net_rx_buffs;
95 struct pktdma_cfg *netcp_pktdma;
98 enum link_type link_type;
103 static void __attribute__((unused))
104 keystone2_eth_gigabit_enable(struct udevice *dev)
106 struct ks2_eth_priv *priv = dev_get_priv(dev);
109 * Check if link detected is giga-bit
110 * If Gigabit mode detected, enable gigbit in MAC
112 if (priv->has_mdio) {
113 if (priv->phydev->speed != 1000)
117 writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
119 EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
120 DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
123 #ifdef CONFIG_SOC_K2G
124 int keystone_rgmii_config(struct phy_device *phy_dev)
126 unsigned int i, status;
130 if (i > SGMII_ANEG_TIMEOUT) {
131 puts(" TIMEOUT !\n");
137 puts("user interrupt!\n");
142 if ((i++ % 500) == 0)
145 udelay(1000); /* 1 ms */
146 status = readl(RGMII_STATUS_REG);
147 } while (!(status & RGMII_REG_STATUS_LINK));
154 int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
156 unsigned int i, status, mask;
157 unsigned int mr_adv_ability, control;
160 case SGMII_LINK_MAC_MAC_AUTONEG:
161 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
162 SGMII_REG_MR_ADV_LINK |
163 SGMII_REG_MR_ADV_FULL_DUPLEX |
164 SGMII_REG_MR_ADV_GIG_MODE);
165 control = (SGMII_REG_CONTROL_MASTER |
166 SGMII_REG_CONTROL_AUTONEG);
169 case SGMII_LINK_MAC_PHY:
170 case SGMII_LINK_MAC_PHY_FORCED:
171 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
172 control = SGMII_REG_CONTROL_AUTONEG;
175 case SGMII_LINK_MAC_MAC_FORCED:
176 mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
177 SGMII_REG_MR_ADV_LINK |
178 SGMII_REG_MR_ADV_FULL_DUPLEX |
179 SGMII_REG_MR_ADV_GIG_MODE);
180 control = SGMII_REG_CONTROL_MASTER;
183 case SGMII_LINK_MAC_FIBER:
184 mr_adv_ability = 0x20;
185 control = SGMII_REG_CONTROL_AUTONEG;
189 mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
190 control = SGMII_REG_CONTROL_AUTONEG;
193 __raw_writel(0, SGMII_CTL_REG(port));
196 * Wait for the SerDes pll to lock,
197 * but don't trap if lock is never read
199 for (i = 0; i < 1000; i++) {
201 status = __raw_readl(SGMII_STATUS_REG(port));
202 if ((status & SGMII_REG_STATUS_LOCK) != 0)
206 __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
207 __raw_writel(control, SGMII_CTL_REG(port));
210 mask = SGMII_REG_STATUS_LINK;
212 if (control & SGMII_REG_CONTROL_AUTONEG)
213 mask |= SGMII_REG_STATUS_AUTONEG;
215 status = __raw_readl(SGMII_STATUS_REG(port));
216 if ((status & mask) == mask)
219 printf("\n%s Waiting for SGMII auto negotiation to complete",
221 while ((status & mask) != mask) {
225 if (i > SGMII_ANEG_TIMEOUT) {
226 puts(" TIMEOUT !\n");
232 puts("user interrupt!\n");
237 if ((i++ % 500) == 0)
240 udelay(1000); /* 1 ms */
241 status = __raw_readl(SGMII_STATUS_REG(port));
249 int mac_sl_reset(u32 port)
253 if (port >= DEVICE_N_GMACSL_PORTS)
254 return GMACSL_RET_INVALID_PORT;
256 /* Set the soft reset bit */
257 writel(CPGMAC_REG_RESET_VAL_RESET,
258 DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
260 /* Wait for the bit to clear */
261 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
262 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
263 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
264 CPGMAC_REG_RESET_VAL_RESET)
265 return GMACSL_RET_OK;
268 /* Timeout on the reset */
269 return GMACSL_RET_WARN_RESET_INCOMPLETE;
272 int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
275 int ret = GMACSL_RET_OK;
277 if (port >= DEVICE_N_GMACSL_PORTS)
278 return GMACSL_RET_INVALID_PORT;
280 if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
281 cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
282 ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
285 /* Must wait if the device is undergoing reset */
286 for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
287 v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
288 if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
289 CPGMAC_REG_RESET_VAL_RESET)
293 if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
294 return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
296 writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
297 writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
299 #ifndef CONFIG_SOC_K2HK
300 /* Map RX packet flow priority to 0 */
301 writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
307 int ethss_config(u32 ctl, u32 max_pkt_size)
311 /* Max length register */
312 writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
314 /* Control register */
315 writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
317 /* All statistics enabled by default */
318 writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
319 DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
321 /* Reset and enable the ALE */
322 writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
323 CPSW_REG_VAL_ALE_CTL_BYPASS,
324 DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
326 /* All ports put into forward mode */
327 for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
328 writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
329 DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
334 int ethss_start(void)
337 struct mac_sl_cfg cfg;
339 cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
340 cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
342 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
344 mac_sl_config(i, &cfg);
354 for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
360 struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
361 .clk = SERDES_CLOCK_156P25M,
362 .rate = SERDES_RATE_5G,
363 .rate_mode = SERDES_QUARTER_RATE,
364 .intf = SERDES_PHY_SGMII,
368 #ifndef CONFIG_SOC_K2G
369 static void keystone2_net_serdes_setup(void)
371 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
372 &ks2_serdes_sgmii_156p25mhz,
373 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
375 #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
376 ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
377 &ks2_serdes_sgmii_156p25mhz,
378 CONFIG_KSNET_SERDES_LANES_PER_SGMII);
381 /* wait till setup */
386 static int ks2_eth_start(struct udevice *dev)
388 struct ks2_eth_priv *priv = dev_get_priv(dev);
390 #ifdef CONFIG_SOC_K2G
391 keystone_rgmii_config(priv->phydev);
393 keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
394 priv->sgmii_link_type);
399 /* On chip switch configuration */
400 ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
404 if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
405 pr_err("ksnav_init failed\n");
410 * Streaming switch configuration. If not present this
411 * statement is defined to void in target.h.
412 * If present this is usually defined to a series of register writes
414 hw_config_streaming_switch();
416 if (priv->has_mdio) {
417 phy_startup(priv->phydev);
418 if (priv->phydev->link == 0) {
419 pr_err("phy startup failed\n");
424 emac_gigabit_enable(dev);
428 priv->emac_open = true;
433 ksnav_close(priv->netcp_pktdma);
440 static int ks2_eth_send(struct udevice *dev, void *packet, int length)
442 struct ks2_eth_priv *priv = dev_get_priv(dev);
444 genphy_update_link(priv->phydev);
445 if (priv->phydev->link == 0)
448 if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
449 length = EMAC_MIN_ETHERNET_PKT_SIZE;
451 return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
452 length, (priv->slave_port) << 16);
455 static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
457 struct ks2_eth_priv *priv = dev_get_priv(dev);
461 priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
462 if (priv->hd == NULL)
465 *packetp = (uchar *)pkt;
470 static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
473 struct ks2_eth_priv *priv = dev_get_priv(dev);
475 ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
480 static void ks2_eth_stop(struct udevice *dev)
482 struct ks2_eth_priv *priv = dev_get_priv(dev);
484 if (!priv->emac_open)
488 ksnav_close(priv->netcp_pktdma);
490 phy_shutdown(priv->phydev);
491 priv->emac_open = false;
494 int ks2_eth_read_rom_hwaddr(struct udevice *dev)
496 struct ks2_eth_priv *priv = dev_get_priv(dev);
497 struct eth_pdata *pdata = dev_get_platdata(dev);
501 /* Read the e-fuse mac address */
502 if (priv->slave_port == 1) {
503 maca = __raw_readl(MAC_ID_BASE_ADDR);
504 macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
507 pdata->enetaddr[0] = (macb >> 8) & 0xff;
508 pdata->enetaddr[1] = (macb >> 0) & 0xff;
509 pdata->enetaddr[2] = (maca >> 24) & 0xff;
510 pdata->enetaddr[3] = (maca >> 16) & 0xff;
511 pdata->enetaddr[4] = (maca >> 8) & 0xff;
512 pdata->enetaddr[5] = (maca >> 0) & 0xff;
517 int ks2_eth_write_hwaddr(struct udevice *dev)
519 struct ks2_eth_priv *priv = dev_get_priv(dev);
520 struct eth_pdata *pdata = dev_get_platdata(dev);
522 writel(mac_hi(pdata->enetaddr),
523 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
525 writel(mac_lo(pdata->enetaddr),
526 DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
532 static int ks2_eth_probe(struct udevice *dev)
534 struct ks2_eth_priv *priv = dev_get_priv(dev);
535 struct mii_dev *mdio_bus;
538 priv->emac_open = false;
540 /* These clock enables has to be moved to common location */
542 writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
544 /* By default, select PA PLL clock as PA clock source */
545 #ifndef CONFIG_SOC_K2G
546 if (psc_enable_module(KS2_LPSC_PA))
549 if (psc_enable_module(KS2_LPSC_CPGMAC))
551 if (psc_enable_module(KS2_LPSC_CRYPTO))
554 if (cpu_is_k2e() || cpu_is_k2l())
557 priv->net_rx_buffs.buff_ptr = rx_buffs;
558 priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
559 priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
561 if (priv->slave_port == 1) {
562 #ifndef CONFIG_SOC_K2G
563 keystone2_net_serdes_setup();
566 * Register MDIO bus for slave 0 only, other slave have
569 mdio_bus = cpsw_mdio_init("ethernet-mdio",
570 (u32)priv->mdio_base,
571 EMAC_MDIO_CLOCK_FREQ,
574 pr_err("MDIO alloc failed\n");
577 priv->mdio_bus = mdio_bus;
579 /* Get the MDIO bus from slave 0 device */
580 struct ks2_eth_priv *parent_priv;
582 parent_priv = dev_get_priv(dev->parent);
583 priv->mdio_bus = parent_priv->mdio_bus;
584 priv->mdio_base = parent_priv->mdio_base;
587 priv->netcp_pktdma = &netcp_pktdma;
589 if (priv->has_mdio) {
590 priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
593 if (priv->phy_of_handle)
594 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
596 phy_config(priv->phydev);
602 int ks2_eth_remove(struct udevice *dev)
604 struct ks2_eth_priv *priv = dev_get_priv(dev);
606 cpsw_mdio_free(priv->mdio_bus);
611 static const struct eth_ops ks2_eth_ops = {
612 .start = ks2_eth_start,
613 .send = ks2_eth_send,
614 .recv = ks2_eth_recv,
615 .free_pkt = ks2_eth_free_pkt,
616 .stop = ks2_eth_stop,
617 .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
618 .write_hwaddr = ks2_eth_write_hwaddr,
621 static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
623 const void *fdt = gd->fdt_blob;
624 struct udevice *sl_dev;
631 interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
632 fdt_for_each_subnode(slave, fdt, interfaces) {
635 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
636 if (slave_no == -ENOENT)
640 /* This is the current eth device */
643 /* Slave devices to be registered */
644 slave_name = malloc(20);
645 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
646 ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
647 slave_name, offset_to_ofnode(slave),
650 pr_err("ks2_net - not able to bind slave interfaces\n");
656 sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
657 fdt_for_each_subnode(slave, fdt, sec_slave) {
660 slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
661 if (slave_no == -ENOENT)
664 /* Slave devices to be registered */
665 slave_name = malloc(20);
666 snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
667 ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
668 offset_to_ofnode(slave), &sl_dev);
670 pr_err("ks2_net - not able to bind slave interfaces\n");
678 static int ks2_eth_parse_slave_interface(int netcp, int slave,
679 struct ks2_eth_priv *priv,
680 struct eth_pdata *pdata)
682 const void *fdt = gd->fdt_blob;
687 const char *phy_mode;
689 priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
690 priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
692 /* U-Boot slave port number starts with 1 instead of 0 */
693 priv->slave_port += 1;
695 dma_count = fdtdec_get_int_array_count(fdt, netcp,
699 if (dma_count > (2 * priv->slave_port)) {
702 dma_idx = priv->slave_port * 2 - 1;
703 priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
706 priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
708 phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
711 priv->phy_of_handle = phy;
712 priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
714 mdio = fdt_parent_offset(fdt, phy);
716 pr_err("mdio dt not found\n");
719 priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
722 if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
723 priv->phy_if = PHY_INTERFACE_MODE_SGMII;
724 pdata->phy_interface = priv->phy_if;
725 priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
726 priv->has_mdio = true;
727 } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
728 phy_mode = fdt_getprop(fdt, slave, "phy-mode", NULL);
730 priv->phy_if = phy_get_interface_by_name(phy_mode);
731 if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
732 priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
733 priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
734 priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
735 pr_err("invalid phy-mode\n");
739 priv->phy_if = PHY_INTERFACE_MODE_RGMII;
741 pdata->phy_interface = priv->phy_if;
742 priv->has_mdio = true;
748 static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
750 struct ks2_eth_priv *priv = dev_get_priv(dev);
751 struct eth_pdata *pdata = dev_get_platdata(dev);
752 const void *fdt = gd->fdt_blob;
753 int slave = dev_of_offset(dev);
759 interfaces = fdt_parent_offset(fdt, slave);
760 gbe = fdt_parent_offset(fdt, interfaces);
761 netcp_devices = fdt_parent_offset(fdt, gbe);
762 netcp = fdt_parent_offset(fdt, netcp_devices);
764 ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
766 pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
771 static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
773 struct ks2_eth_priv *priv = dev_get_priv(dev);
774 struct eth_pdata *pdata = dev_get_platdata(dev);
775 const void *fdt = gd->fdt_blob;
780 netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
782 gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
784 ks2_eth_bind_slaves(dev, gbe, &gbe_0);
786 ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
788 pdata->iobase = devfdt_get_addr(dev);
793 static const struct udevice_id ks2_eth_ids[] = {
794 { .compatible = "ti,netcp-1.0" },
798 U_BOOT_DRIVER(eth_ks2_slave) = {
799 .name = "eth_ks2_sl",
801 .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
802 .probe = ks2_eth_probe,
803 .remove = ks2_eth_remove,
805 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
806 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
807 .flags = DM_FLAG_ALLOC_PRIV_DMA,
810 U_BOOT_DRIVER(eth_ks2) = {
813 .of_match = ks2_eth_ids,
814 .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
815 .probe = ks2_eth_probe,
816 .remove = ks2_eth_remove,
818 .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
819 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
820 .flags = DM_FLAG_ALLOC_PRIV_DMA,