drivers/net/ti/cpsw.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * CPSW Ethernet Switch Driver
   4  *
   5  * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <net.h>
  11 #include <miiphy.h>
  12 #include <malloc.h>
  13 #include <net.h>
  14 #include <netdev.h>
  15 #include <cpsw.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/io.h>
  19 #include <phy.h>
  20 #include <asm/arch/cpu.h>
  21 #include <dm.h>
  22 #include <fdt_support.h>
  23
  24 #include "cpsw_mdio.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #define BITMASK(bits)           (BIT(bits) - 1)
  29 #define NUM_DESCS               (PKTBUFSRX * 2)
  30 #define PKT_MIN                 60
  31 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  32 #define CLEAR_BIT               1
  33 #define GIGABITEN               BIT(7)
  34 #define FULLDUPLEXEN            BIT(0)
  35 #define MIIEN                   BIT(15)
  36 /* DMA Registers */
  37 #define CPDMA_TXCONTROL         0x004
  38 #define CPDMA_RXCONTROL         0x014
  39 #define CPDMA_SOFTRESET         0x01c
  40 #define CPDMA_RXFREE            0x0e0
  41 #define CPDMA_TXHDP_VER1        0x100
  42 #define CPDMA_TXHDP_VER2        0x200
  43 #define CPDMA_RXHDP_VER1        0x120
  44 #define CPDMA_RXHDP_VER2        0x220
  45 #define CPDMA_TXCP_VER1         0x140
  46 #define CPDMA_TXCP_VER2         0x240
  47 #define CPDMA_RXCP_VER1         0x160
  48 #define CPDMA_RXCP_VER2         0x260
  49
  50 /* Descriptor mode bits */
  51 #define CPDMA_DESC_SOP          BIT(31)
  52 #define CPDMA_DESC_EOP          BIT(30)
  53 #define CPDMA_DESC_OWNER        BIT(29)
  54 #define CPDMA_DESC_EOQ          BIT(28)
  55
  56 /*
  57  * This timeout definition is a worst-case ultra defensive measure against
  58  * unexpected controller lock ups.  Ideally, we should never ever hit this
  59  * scenario in practice.
  60  */
  61 #define CPDMA_TIMEOUT           100 /* msecs */
  62
  63 struct cpsw_regs {
  64         u32     id_ver;
  65         u32     control;
  66         u32     soft_reset;
  67         u32     stat_port_en;
  68         u32     ptype;
  69 };
  70
  71 struct cpsw_slave_regs {
  72         u32     max_blks;
  73         u32     blk_cnt;
  74         u32     flow_thresh;
  75         u32     port_vlan;
  76         u32     tx_pri_map;
  77 #ifdef CONFIG_AM33XX
  78         u32     gap_thresh;
  79 #elif defined(CONFIG_TI814X)
  80         u32     ts_ctl;
  81         u32     ts_seq_ltype;
  82         u32     ts_vlan;
  83 #endif
  84         u32     sa_lo;
  85         u32     sa_hi;
  86 };
  87
  88 struct cpsw_host_regs {
  89         u32     max_blks;
  90         u32     blk_cnt;
  91         u32     flow_thresh;
  92         u32     port_vlan;
  93         u32     tx_pri_map;
  94         u32     cpdma_tx_pri_map;
  95         u32     cpdma_rx_chan_map;
  96 };
  97
  98 struct cpsw_sliver_regs {
  99         u32     id_ver;
 100         u32     mac_control;
 101         u32     mac_status;
 102         u32     soft_reset;
 103         u32     rx_maxlen;
 104         u32     __reserved_0;
 105         u32     rx_pause;
 106         u32     tx_pause;
 107         u32     __reserved_1;
 108         u32     rx_pri_map;
 109 };
 110
 111 #define ALE_ENTRY_BITS          68
 112 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 113
 114 /* ALE Registers */
 115 #define ALE_CONTROL             0x08
 116 #define ALE_UNKNOWNVLAN         0x18
 117 #define ALE_TABLE_CONTROL       0x20
 118 #define ALE_TABLE               0x34
 119 #define ALE_PORTCTL             0x40
 120
 121 #define ALE_TABLE_WRITE         BIT(31)
 122
 123 #define ALE_TYPE_FREE                   0
 124 #define ALE_TYPE_ADDR                   1
 125 #define ALE_TYPE_VLAN                   2
 126 #define ALE_TYPE_VLAN_ADDR              3
 127
 128 #define ALE_UCAST_PERSISTANT            0
 129 #define ALE_UCAST_UNTOUCHED             1
 130 #define ALE_UCAST_OUI                   2
 131 #define ALE_UCAST_TOUCHED               3
 132
 133 #define ALE_MCAST_FWD                   0
 134 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 135 #define ALE_MCAST_FWD_LEARN             2
 136 #define ALE_MCAST_FWD_2                 3
 137
 138 enum cpsw_ale_port_state {
 139         ALE_PORT_STATE_DISABLE  = 0x00,
 140         ALE_PORT_STATE_BLOCK    = 0x01,
 141         ALE_PORT_STATE_LEARN    = 0x02,
 142         ALE_PORT_STATE_FORWARD  = 0x03,
 143 };
 144
 145 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 146 #define ALE_SECURE      1
 147 #define ALE_BLOCKED     2
 148
 149 struct cpsw_slave {
 150         struct cpsw_slave_regs          *regs;
 151         struct cpsw_sliver_regs         *sliver;
 152         int                             slave_num;
 153         u32                             mac_control;
 154         struct cpsw_slave_data          *data;
 155 };
 156
 157 struct cpdma_desc {
 158         /* hardware fields */
 159         u32                     hw_next;
 160         u32                     hw_buffer;
 161         u32                     hw_len;
 162         u32                     hw_mode;
 163         /* software fields */
 164         u32                     sw_buffer;
 165         u32                     sw_len;
 166 };
 167
 168 struct cpdma_chan {
 169         struct cpdma_desc       *head, *tail;
 170         void                    *hdp, *cp, *rxfree;
 171 };
 172
 173 /* AM33xx SoC specific definitions for the CONTROL port */
 174 #define AM33XX_GMII_SEL_MODE_MII        0
 175 #define AM33XX_GMII_SEL_MODE_RMII       1
 176 #define AM33XX_GMII_SEL_MODE_RGMII      2
 177
 178 #define AM33XX_GMII_SEL_RGMII1_IDMODE   BIT(4)
 179 #define AM33XX_GMII_SEL_RGMII2_IDMODE   BIT(5)
 180 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
 181 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
 182
 183 #define GMII_SEL_MODE_MASK              0x3
 184
 185 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->fld)
 186 #define desc_read(desc, fld)            __raw_readl(&(desc)->fld)
 187 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->fld))
 188
 189 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 190 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 191 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 192
 193 #define for_active_slave(slave, priv) \
 194         slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
 195 #define for_each_slave(slave, priv) \
 196         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 197                                 ((priv)->data)->slaves; slave++)
 198
 199 struct cpsw_priv {
 200 #ifdef CONFIG_DM_ETH
 201         struct udevice                  *dev;
 202 #else
 203         struct eth_device               *dev;
 204 #endif
 205         struct cpsw_platform_data       *data;
 206         int                             host_port;
 207
 208         struct cpsw_regs                *regs;
 209         void                            *dma_regs;
 210         struct cpsw_host_regs           *host_port_regs;
 211         void                            *ale_regs;
 212
 213         struct cpdma_desc               *descs;
 214         struct cpdma_desc               *desc_free;
 215         struct cpdma_chan               rx_chan, tx_chan;
 216
 217         struct cpsw_slave               *slaves;
 218         struct phy_device               *phydev;
 219         struct mii_dev                  *bus;
 220
 221         u32                             phy_mask;
 222 };
 223
 224 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 225 {
 226         int idx;
 227
 228         idx    = start / 32;
 229         start -= idx * 32;
 230         idx    = 2 - idx; /* flip */
 231         return (ale_entry[idx] >> start) & BITMASK(bits);
 232 }
 233
 234 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 235                                       u32 value)
 236 {
 237         int idx;
 238
 239         value &= BITMASK(bits);
 240         idx    = start / 32;
 241         start -= idx * 32;
 242         idx    = 2 - idx; /* flip */
 243         ale_entry[idx] &= ~(BITMASK(bits) << start);
 244         ale_entry[idx] |=  (value << start);
 245 }
 246
 247 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 248 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 249 {                                                                       \
 250         return cpsw_ale_get_field(ale_entry, start, bits);              \
 251 }                                                                       \
 252 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 253 {                                                                       \
 254         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 255 }
 256
 257 DEFINE_ALE_FIELD(entry_type,            60,     2)
 258 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 259 DEFINE_ALE_FIELD(port_mask,             66,     3)
 260 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 261 DEFINE_ALE_FIELD(port_num,              66,     2)
 262 DEFINE_ALE_FIELD(blocked,               65,     1)
 263 DEFINE_ALE_FIELD(secure,                64,     1)
 264 DEFINE_ALE_FIELD(mcast,                 40,     1)
 265
 266 /* The MAC address field in the ALE entry cannot be macroized as above */
 267 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 268 {
 269         int i;
 270
 271         for (i = 0; i < 6; i++)
 272                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 273 }
 274
 275 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 276 {
 277         int i;
 278
 279         for (i = 0; i < 6; i++)
 280                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 281 }
 282
 283 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 284 {
 285         int i;
 286
 287         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 288
 289         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 290                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 291
 292         return idx;
 293 }
 294
 295 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 296 {
 297         int i;
 298
 299         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 300                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 301
 302         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 303
 304         return idx;
 305 }
 306
 307 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
 308 {
 309         u32 ale_entry[ALE_ENTRY_WORDS];
 310         int type, idx;
 311
 312         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 313                 u8 entry_addr[6];
 314
 315                 cpsw_ale_read(priv, idx, ale_entry);
 316                 type = cpsw_ale_get_entry_type(ale_entry);
 317                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 318                         continue;
 319                 cpsw_ale_get_addr(ale_entry, entry_addr);
 320                 if (memcmp(entry_addr, addr, 6) == 0)
 321                         return idx;
 322         }
 323         return -ENOENT;
 324 }
 325
 326 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 327 {
 328         u32 ale_entry[ALE_ENTRY_WORDS];
 329         int type, idx;
 330
 331         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 332                 cpsw_ale_read(priv, idx, ale_entry);
 333                 type = cpsw_ale_get_entry_type(ale_entry);
 334                 if (type == ALE_TYPE_FREE)
 335                         return idx;
 336         }
 337         return -ENOENT;
 338 }
 339
 340 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 341 {
 342         u32 ale_entry[ALE_ENTRY_WORDS];
 343         int type, idx;
 344
 345         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 346                 cpsw_ale_read(priv, idx, ale_entry);
 347                 type = cpsw_ale_get_entry_type(ale_entry);
 348                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 349                         continue;
 350                 if (cpsw_ale_get_mcast(ale_entry))
 351                         continue;
 352                 type = cpsw_ale_get_ucast_type(ale_entry);
 353                 if (type != ALE_UCAST_PERSISTANT &&
 354                     type != ALE_UCAST_OUI)
 355                         return idx;
 356         }
 357         return -ENOENT;
 358 }
 359
 360 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
 361                               int port, int flags)
 362 {
 363         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 364         int idx;
 365
 366         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 367         cpsw_ale_set_addr(ale_entry, addr);
 368         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 369         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 370         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 371         cpsw_ale_set_port_num(ale_entry, port);
 372
 373         idx = cpsw_ale_match_addr(priv, addr);
 374         if (idx < 0)
 375                 idx = cpsw_ale_match_free(priv);
 376         if (idx < 0)
 377                 idx = cpsw_ale_find_ageable(priv);
 378         if (idx < 0)
 379                 return -ENOMEM;
 380
 381         cpsw_ale_write(priv, idx, ale_entry);
 382         return 0;
 383 }
 384
 385 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
 386                               int port_mask)
 387 {
 388         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 389         int idx, mask;
 390
 391         idx = cpsw_ale_match_addr(priv, addr);
 392         if (idx >= 0)
 393                 cpsw_ale_read(priv, idx, ale_entry);
 394
 395         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 396         cpsw_ale_set_addr(ale_entry, addr);
 397         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 398
 399         mask = cpsw_ale_get_port_mask(ale_entry);
 400         port_mask |= mask;
 401         cpsw_ale_set_port_mask(ale_entry, port_mask);
 402
 403         if (idx < 0)
 404                 idx = cpsw_ale_match_free(priv);
 405         if (idx < 0)
 406                 idx = cpsw_ale_find_ageable(priv);
 407         if (idx < 0)
 408                 return -ENOMEM;
 409
 410         cpsw_ale_write(priv, idx, ale_entry);
 411         return 0;
 412 }
 413
 414 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 415 {
 416         u32 tmp, mask = BIT(bit);
 417
 418         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 419         tmp &= ~mask;
 420         tmp |= val ? mask : 0;
 421         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 422 }
 423
 424 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 425 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 426 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 427
 428 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 429                                        int val)
 430 {
 431         int offset = ALE_PORTCTL + 4 * port;
 432         u32 tmp, mask = 0x3;
 433
 434         tmp  = __raw_readl(priv->ale_regs + offset);
 435         tmp &= ~mask;
 436         tmp |= val & mask;
 437         __raw_writel(tmp, priv->ale_regs + offset);
 438 }
 439
 440 /* Set a self-clearing bit in a register, and wait for it to clear */
 441 static inline void setbit_and_wait_for_clear32(void *addr)
 442 {
 443         __raw_writel(CLEAR_BIT, addr);
 444         while (__raw_readl(addr) & CLEAR_BIT)
 445                 ;
 446 }
 447
 448 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 449                          ((mac)[2] << 16) | ((mac)[3] << 24))
 450 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 451
 452 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 453                                struct cpsw_priv *priv)
 454 {
 455 #ifdef CONFIG_DM_ETH
 456         struct eth_pdata *pdata = dev_get_platdata(priv->dev);
 457
 458         writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
 459         writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
 460 #else
 461         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 462         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 463 #endif
 464 }
 465
 466 static int cpsw_slave_update_link(struct cpsw_slave *slave,
 467                                    struct cpsw_priv *priv, int *link)
 468 {
 469         struct phy_device *phy;
 470         u32 mac_control = 0;
 471         int ret = -ENODEV;
 472
 473         phy = priv->phydev;
 474         if (!phy)
 475                 goto out;
 476
 477         ret = phy_startup(phy);
 478         if (ret)
 479                 goto out;
 480
 481         if (link)
 482                 *link = phy->link;
 483
 484         if (phy->link) { /* link up */
 485                 mac_control = priv->data->mac_control;
 486                 if (phy->speed == 1000)
 487                         mac_control |= GIGABITEN;
 488                 if (phy->duplex == DUPLEX_FULL)
 489                         mac_control |= FULLDUPLEXEN;
 490                 if (phy->speed == 100)
 491                         mac_control |= MIIEN;
 492         }
 493
 494         if (mac_control == slave->mac_control)
 495                 goto out;
 496
 497         if (mac_control) {
 498                 printf("link up on port %d, speed %d, %s duplex\n",
 499                                 slave->slave_num, phy->speed,
 500                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 501         } else {
 502                 printf("link down on port %d\n", slave->slave_num);
 503         }
 504
 505         __raw_writel(mac_control, &slave->sliver->mac_control);
 506         slave->mac_control = mac_control;
 507
 508 out:
 509         return ret;
 510 }
 511
 512 static int cpsw_update_link(struct cpsw_priv *priv)
 513 {
 514         int ret = -ENODEV;
 515         struct cpsw_slave *slave;
 516
 517         for_active_slave(slave, priv)
 518                 ret = cpsw_slave_update_link(slave, priv, NULL);
 519
 520         return ret;
 521 }
 522
 523 static inline u32  cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 524 {
 525         if (priv->host_port == 0)
 526                 return slave_num + 1;
 527         else
 528                 return slave_num;
 529 }
 530
 531 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 532 {
 533         u32     slave_port;
 534
 535         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 536
 537         /* setup priority mapping */
 538         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 539         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 540
 541         /* setup max packet size, and mac address */
 542         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 543         cpsw_set_slave_mac(slave, priv);
 544
 545         slave->mac_control = 0; /* no link yet */
 546
 547         /* enable forwarding */
 548         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 549         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 550
 551         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
 552
 553         priv->phy_mask |= 1 << slave->data->phy_addr;
 554 }
 555
 556 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 557 {
 558         struct cpdma_desc *desc = priv->desc_free;
 559
 560         if (desc)
 561                 priv->desc_free = desc_read_ptr(desc, hw_next);
 562         return desc;
 563 }
 564
 565 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
 566 {
 567         if (desc) {
 568                 desc_write(desc, hw_next, priv->desc_free);
 569                 priv->desc_free = desc;
 570         }
 571 }
 572
 573 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 574                         void *buffer, int len)
 575 {
 576         struct cpdma_desc *desc, *prev;
 577         u32 mode;
 578
 579         desc = cpdma_desc_alloc(priv);
 580         if (!desc)
 581                 return -ENOMEM;
 582
 583         if (len < PKT_MIN)
 584                 len = PKT_MIN;
 585
 586         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 587
 588         desc_write(desc, hw_next,   0);
 589         desc_write(desc, hw_buffer, buffer);
 590         desc_write(desc, hw_len,    len);
 591         desc_write(desc, hw_mode,   mode | len);
 592         desc_write(desc, sw_buffer, buffer);
 593         desc_write(desc, sw_len,    len);
 594
 595         if (!chan->head) {
 596                 /* simple case - first packet enqueued */
 597                 chan->head = desc;
 598                 chan->tail = desc;
 599                 chan_write(chan, hdp, desc);
 600                 goto done;
 601         }
 602
 603         /* not the first packet - enqueue at the tail */
 604         prev = chan->tail;
 605         desc_write(prev, hw_next, desc);
 606         chan->tail = desc;
 607
 608         /* next check if EOQ has been triggered already */
 609         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 610                 chan_write(chan, hdp, desc);
 611
 612 done:
 613         if (chan->rxfree)
 614                 chan_write(chan, rxfree, 1);
 615         return 0;
 616 }
 617
 618 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 619                          void **buffer, int *len)
 620 {
 621         struct cpdma_desc *desc = chan->head;
 622         u32 status;
 623
 624         if (!desc)
 625                 return -ENOENT;
 626
 627         status = desc_read(desc, hw_mode);
 628
 629         if (len)
 630                 *len = status & 0x7ff;
 631
 632         if (buffer)
 633                 *buffer = desc_read_ptr(desc, sw_buffer);
 634
 635         if (status & CPDMA_DESC_OWNER) {
 636                 if (chan_read(chan, hdp) == 0) {
 637                         if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
 638                                 chan_write(chan, hdp, desc);
 639                 }
 640
 641                 return -EBUSY;
 642         }
 643
 644         chan->head = desc_read_ptr(desc, hw_next);
 645         chan_write(chan, cp, desc);
 646
 647         cpdma_desc_free(priv, desc);
 648         return 0;
 649 }
 650
 651 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
 652 {
 653         struct cpsw_slave       *slave;
 654         int i, ret;
 655
 656         /* soft reset the controller and initialize priv */
 657         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 658
 659         /* initialize and reset the address lookup engine */
 660         cpsw_ale_enable(priv, 1);
 661         cpsw_ale_clear(priv, 1);
 662         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 663
 664         /* setup host port priority mapping */
 665         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 666         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 667
 668         /* disable priority elevation and enable statistics on all ports */
 669         __raw_writel(0, &priv->regs->ptype);
 670
 671         /* enable statistics collection only on the host port */
 672         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 673         __raw_writel(0x7, &priv->regs->stat_port_en);
 674
 675         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 676
 677         cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
 678         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 679
 680         for_active_slave(slave, priv)
 681                 cpsw_slave_init(slave, priv);
 682
 683         ret = cpsw_update_link(priv);
 684         if (ret)
 685                 goto out;
 686
 687         /* init descriptor pool */
 688         for (i = 0; i < NUM_DESCS; i++) {
 689                 desc_write(&priv->descs[i], hw_next,
 690                            (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
 691         }
 692         priv->desc_free = &priv->descs[0];
 693
 694         /* initialize channels */
 695         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 696                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 697                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 698                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 699                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 700
 701                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 702                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 703                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 704         } else {
 705                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 706                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 707                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 708                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 709
 710                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 711                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 712                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 713         }
 714
 715         /* clear dma state */
 716         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 717
 718         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 719                 for (i = 0; i < priv->data->channels; i++) {
 720                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
 721                                         * i);
 722                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 723                                         * i);
 724                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
 725                                         * i);
 726                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
 727                                         * i);
 728                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
 729                                         * i);
 730                 }
 731         } else {
 732                 for (i = 0; i < priv->data->channels; i++) {
 733                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
 734                                         * i);
 735                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
 736                                         * i);
 737                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
 738                                         * i);
 739                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
 740                                         * i);
 741                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
 742                                         * i);
 743
 744                 }
 745         }
 746
 747         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 748         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 749
 750         /* submit rx descs */
 751         for (i = 0; i < PKTBUFSRX; i++) {
 752                 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
 753                                    PKTSIZE);
 754                 if (ret < 0) {
 755                         printf("error %d submitting rx desc\n", ret);
 756                         break;
 757                 }
 758         }
 759
 760 out:
 761         return ret;
 762 }
 763
 764 static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
 765 {
 766         int timeout = CPDMA_TIMEOUT;
 767
 768         /* reap completed packets */
 769         while (timeout-- &&
 770                (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
 771                 ;
 772
 773         return timeout;
 774 }
 775
 776 static void _cpsw_halt(struct cpsw_priv *priv)
 777 {
 778         cpsw_reap_completed_packets(priv);
 779
 780         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 781         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 782
 783         /* soft reset the controller and initialize priv */
 784         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 785
 786         /* clear dma state */
 787         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 788
 789 }
 790
 791 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
 792 {
 793         int timeout;
 794
 795         flush_dcache_range((unsigned long)packet,
 796                            (unsigned long)packet + ALIGN(length, PKTALIGN));
 797
 798         timeout = cpsw_reap_completed_packets(priv);
 799         if (timeout == -1) {
 800                 printf("cpdma_process timeout\n");
 801                 return -ETIMEDOUT;
 802         }
 803
 804         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 805 }
 806
 807 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
 808 {
 809         void *buffer;
 810         int len;
 811         int ret;
 812
 813         ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
 814         if (ret < 0)
 815                 return ret;
 816
 817         invalidate_dcache_range((unsigned long)buffer,
 818                                 (unsigned long)buffer + PKTSIZE_ALIGN);
 819         *pkt = buffer;
 820
 821         return len;
 822 }
 823
 824 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 825                             struct cpsw_priv *priv)
 826 {
 827         void                    *regs = priv->regs;
 828         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 829         slave->slave_num = slave_num;
 830         slave->data     = data;
 831         slave->regs     = regs + data->slave_reg_ofs;
 832         slave->sliver   = regs + data->sliver_reg_ofs;
 833 }
 834
 835 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 836 {
 837         struct phy_device *phydev;
 838         u32 supported = PHY_GBIT_FEATURES;
 839
 840         phydev = phy_connect(priv->bus,
 841                         slave->data->phy_addr,
 842                         priv->dev,
 843                         slave->data->phy_if);
 844
 845         if (!phydev)
 846                 return -1;
 847
 848         phydev->supported &= supported;
 849         phydev->advertising = phydev->supported;
 850
 851 #ifdef CONFIG_DM_ETH
 852         if (slave->data->phy_of_handle)
 853                 phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
 854 #endif
 855
 856         priv->phydev = phydev;
 857         phy_config(phydev);
 858
 859         return 1;
 860 }
 861
 862 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
 863 {
 864         struct cpsw_platform_data *data = priv->data;
 865         u16 alive = cpsw_mdio_get_alive(priv->bus);
 866         int active = data->active_slave;
 867         int new_addr = ffs(alive) - 1;
 868
 869         /*
 870          * If there is only one phy alive and its address does not match
 871          * that of active slave, then phy address can safely be updated.
 872          */
 873         if (hweight16(alive) == 1 &&
 874             data->slave_data[active].phy_addr != new_addr) {
 875                 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
 876                        active, data->slave_data[active].phy_addr, new_addr);
 877                 data->slave_data[active].phy_addr = new_addr;
 878         }
 879 }
 880
 881 int _cpsw_register(struct cpsw_priv *priv)
 882 {
 883         struct cpsw_slave       *slave;
 884         struct cpsw_platform_data *data = priv->data;
 885         void                    *regs = (void *)data->cpsw_base;
 886
 887         priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
 888         if (!priv->slaves) {
 889                 return -ENOMEM;
 890         }
 891
 892         priv->host_port         = data->host_port_num;
 893         priv->regs              = regs;
 894         priv->host_port_regs    = regs + data->host_port_reg_ofs;
 895         priv->dma_regs          = regs + data->cpdma_reg_ofs;
 896         priv->ale_regs          = regs + data->ale_reg_ofs;
 897         priv->descs             = (void *)regs + data->bd_ram_ofs;
 898
 899         int idx = 0;
 900
 901         for_each_slave(slave, priv) {
 902                 cpsw_slave_setup(slave, idx, priv);
 903                 idx = idx + 1;
 904         }
 905
 906         priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
 907         if (!priv->bus)
 908                 return -EFAULT;
 909
 910         cpsw_phy_addr_update(priv);
 911
 912         for_active_slave(slave, priv)
 913                 cpsw_phy_init(priv, slave);
 914
 915         return 0;
 916 }
 917
 918 #ifndef CONFIG_DM_ETH
 919 static int cpsw_init(struct eth_device *dev, bd_t *bis)
 920 {
 921         struct cpsw_priv        *priv = dev->priv;
 922
 923         return _cpsw_init(priv, dev->enetaddr);
 924 }
 925
 926 static void cpsw_halt(struct eth_device *dev)
 927 {
 928         struct cpsw_priv *priv = dev->priv;
 929
 930         return _cpsw_halt(priv);
 931 }
 932
 933 static int cpsw_send(struct eth_device *dev, void *packet, int length)
 934 {
 935         struct cpsw_priv        *priv = dev->priv;
 936
 937         return _cpsw_send(priv, packet, length);
 938 }
 939
 940 static int cpsw_recv(struct eth_device *dev)
 941 {
 942         struct cpsw_priv *priv = dev->priv;
 943         uchar *pkt = NULL;
 944         int len;
 945
 946         len = _cpsw_recv(priv, &pkt);
 947
 948         if (len > 0) {
 949                 net_process_received_packet(pkt, len);
 950                 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
 951         }
 952
 953         return len;
 954 }
 955
 956 int cpsw_register(struct cpsw_platform_data *data)
 957 {
 958         struct cpsw_priv        *priv;
 959         struct eth_device       *dev;
 960         int ret;
 961
 962         dev = calloc(sizeof(*dev), 1);
 963         if (!dev)
 964                 return -ENOMEM;
 965
 966         priv = calloc(sizeof(*priv), 1);
 967         if (!priv) {
 968                 free(dev);
 969                 return -ENOMEM;
 970         }
 971
 972         priv->dev = dev;
 973         priv->data = data;
 974
 975         strcpy(dev->name, "cpsw");
 976         dev->iobase     = 0;
 977         dev->init       = cpsw_init;
 978         dev->halt       = cpsw_halt;
 979         dev->send       = cpsw_send;
 980         dev->recv       = cpsw_recv;
 981         dev->priv       = priv;
 982
 983         eth_register(dev);
 984
 985         ret = _cpsw_register(priv);
 986         if (ret < 0) {
 987                 eth_unregister(dev);
 988                 free(dev);
 989                 free(priv);
 990                 return ret;
 991         }
 992
 993         return 1;
 994 }
 995 #else
 996 static int cpsw_eth_start(struct udevice *dev)
 997 {
 998         struct eth_pdata *pdata = dev_get_platdata(dev);
 999         struct cpsw_priv *priv = dev_get_priv(dev);
1000
1001         return _cpsw_init(priv, pdata->enetaddr);
1002 }
1003
1004 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1005 {
1006         struct cpsw_priv *priv = dev_get_priv(dev);
1007
1008         return _cpsw_send(priv, packet, length);
1009 }
1010
1011 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1012 {
1013         struct cpsw_priv *priv = dev_get_priv(dev);
1014
1015         return _cpsw_recv(priv, packetp);
1016 }
1017
1018 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1019                                    int length)
1020 {
1021         struct cpsw_priv *priv = dev_get_priv(dev);
1022
1023         return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1024 }
1025
1026 static void cpsw_eth_stop(struct udevice *dev)
1027 {
1028         struct cpsw_priv *priv = dev_get_priv(dev);
1029
1030         return _cpsw_halt(priv);
1031 }
1032
1033 static const struct eth_ops cpsw_eth_ops = {
1034         .start          = cpsw_eth_start,
1035         .send           = cpsw_eth_send,
1036         .recv           = cpsw_eth_recv,
1037         .free_pkt       = cpsw_eth_free_pkt,
1038         .stop           = cpsw_eth_stop,
1039 };
1040
1041 static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
1042 {
1043         return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL,
1044                                                   false);
1045 }
1046
1047 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
1048                                  phy_interface_t phy_mode)
1049 {
1050         u32 reg;
1051         u32 mask;
1052         u32 mode = 0;
1053         bool rgmii_id = false;
1054         int slave = priv->data->active_slave;
1055
1056         reg = readl(priv->data->gmii_sel);
1057
1058         switch (phy_mode) {
1059         case PHY_INTERFACE_MODE_RMII:
1060                 mode = AM33XX_GMII_SEL_MODE_RMII;
1061                 break;
1062
1063         case PHY_INTERFACE_MODE_RGMII:
1064                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1065                 break;
1066         case PHY_INTERFACE_MODE_RGMII_ID:
1067         case PHY_INTERFACE_MODE_RGMII_RXID:
1068         case PHY_INTERFACE_MODE_RGMII_TXID:
1069                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1070                 rgmii_id = true;
1071                 break;
1072
1073         case PHY_INTERFACE_MODE_MII:
1074         default:
1075                 mode = AM33XX_GMII_SEL_MODE_MII;
1076                 break;
1077         };
1078
1079         mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
1080         mode <<= slave * 2;
1081
1082         if (priv->data->rmii_clock_external) {
1083                 if (slave == 0)
1084                         mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1085                 else
1086                         mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1087         }
1088
1089         if (rgmii_id) {
1090                 if (slave == 0)
1091                         mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1092                 else
1093                         mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1094         }
1095
1096         reg &= ~mask;
1097         reg |= mode;
1098
1099         writel(reg, priv->data->gmii_sel);
1100 }
1101
1102 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1103                                  phy_interface_t phy_mode)
1104 {
1105         u32 reg;
1106         u32 mask;
1107         u32 mode = 0;
1108         int slave = priv->data->active_slave;
1109
1110         reg = readl(priv->data->gmii_sel);
1111
1112         switch (phy_mode) {
1113         case PHY_INTERFACE_MODE_RMII:
1114                 mode = AM33XX_GMII_SEL_MODE_RMII;
1115                 break;
1116
1117         case PHY_INTERFACE_MODE_RGMII:
1118         case PHY_INTERFACE_MODE_RGMII_ID:
1119         case PHY_INTERFACE_MODE_RGMII_RXID:
1120         case PHY_INTERFACE_MODE_RGMII_TXID:
1121                 mode = AM33XX_GMII_SEL_MODE_RGMII;
1122                 break;
1123
1124         case PHY_INTERFACE_MODE_MII:
1125         default:
1126                 mode = AM33XX_GMII_SEL_MODE_MII;
1127                 break;
1128         };
1129
1130         switch (slave) {
1131         case 0:
1132                 mask = GMII_SEL_MODE_MASK;
1133                 break;
1134         case 1:
1135                 mask = GMII_SEL_MODE_MASK << 4;
1136                 mode <<= 4;
1137                 break;
1138         default:
1139                 dev_err(priv->dev, "invalid slave number...\n");
1140                 return;
1141         }
1142
1143         if (priv->data->rmii_clock_external)
1144                 dev_err(priv->dev, "RMII External clock is not supported\n");
1145
1146         reg &= ~mask;
1147         reg |= mode;
1148
1149         writel(reg, priv->data->gmii_sel);
1150 }
1151
1152 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1153                          phy_interface_t phy_mode)
1154 {
1155         if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1156                 cpsw_gmii_sel_am3352(priv, phy_mode);
1157         if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1158                 cpsw_gmii_sel_am3352(priv, phy_mode);
1159         else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1160                 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1161 }
1162
1163 static int cpsw_eth_probe(struct udevice *dev)
1164 {
1165         struct cpsw_priv *priv = dev_get_priv(dev);
1166         struct eth_pdata *pdata = dev_get_platdata(dev);
1167
1168         priv->dev = dev;
1169         priv->data = pdata->priv_pdata;
1170         ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
1171         /* Select phy interface in control module */
1172         cpsw_phy_sel(priv, priv->data->phy_sel_compat,
1173                      pdata->phy_interface);
1174
1175         return _cpsw_register(priv);
1176 }
1177
1178 #if CONFIG_IS_ENABLED(OF_CONTROL)
1179 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1180 {
1181         struct eth_pdata *pdata = dev_get_platdata(dev);
1182         struct cpsw_platform_data *data;
1183         struct gpio_desc *mode_gpios;
1184         const char *phy_mode;
1185         const void *fdt = gd->fdt_blob;
1186         int node = dev_of_offset(dev);
1187         int subnode;
1188         int slave_index = 0;
1189         int active_slave;
1190         int num_mode_gpios;
1191         int ret;
1192
1193         data = calloc(1, sizeof(struct cpsw_platform_data));
1194         pdata->priv_pdata = data;
1195         pdata->iobase = devfdt_get_addr(dev);
1196         data->version = CPSW_CTRL_VERSION_2;
1197         data->bd_ram_ofs = CPSW_BD_OFFSET;
1198         data->ale_reg_ofs = CPSW_ALE_OFFSET;
1199         data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1200         data->mdio_div = CPSW_MDIO_DIV;
1201         data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1202
1203         pdata->phy_interface = -1;
1204
1205         data->cpsw_base = pdata->iobase;
1206         data->channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1);
1207         if (data->channels <= 0) {
1208                 printf("error: cpdma_channels not found in dt\n");
1209                 return -ENOENT;
1210         }
1211
1212         data->slaves = fdtdec_get_int(fdt, node, "slaves", -1);
1213         if (data->slaves <= 0) {
1214                 printf("error: slaves not found in dt\n");
1215                 return -ENOENT;
1216         }
1217         data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
1218                                        data->slaves);
1219
1220         data->ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1);
1221         if (data->ale_entries <= 0) {
1222                 printf("error: ale_entries not found in dt\n");
1223                 return -ENOENT;
1224         }
1225
1226         data->bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1);
1227         if (data->bd_ram_ofs <= 0) {
1228                 printf("error: bd_ram_size not found in dt\n");
1229                 return -ENOENT;
1230         }
1231
1232         data->mac_control = fdtdec_get_int(fdt, node, "mac_control", -1);
1233         if (data->mac_control <= 0) {
1234                 printf("error: ale_entries not found in dt\n");
1235                 return -ENOENT;
1236         }
1237
1238         num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1239         if (num_mode_gpios > 0) {
1240                 mode_gpios = malloc(sizeof(struct gpio_desc) *
1241                                     num_mode_gpios);
1242                 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1243                                           num_mode_gpios, GPIOD_IS_OUT);
1244                 free(mode_gpios);
1245         }
1246
1247         active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
1248         data->active_slave = active_slave;
1249
1250         fdt_for_each_subnode(subnode, fdt, node) {
1251                 int len;
1252                 const char *name;
1253
1254                 name = fdt_get_name(fdt, subnode, &len);
1255                 if (!strncmp(name, "mdio", 4)) {
1256                         u32 mdio_base;
1257
1258                         mdio_base = cpsw_get_addr_by_node(fdt, subnode);
1259                         if (mdio_base == FDT_ADDR_T_NONE) {
1260                                 pr_err("Not able to get MDIO address space\n");
1261                                 return -ENOENT;
1262                         }
1263                         data->mdio_base = mdio_base;
1264                 }
1265
1266                 if (!strncmp(name, "slave", 5)) {
1267                         u32 phy_id[2];
1268
1269                         if (slave_index >= data->slaves)
1270                                 continue;
1271                         phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
1272                         if (phy_mode)
1273                                 data->slave_data[slave_index].phy_if =
1274                                         phy_get_interface_by_name(phy_mode);
1275
1276                         data->slave_data[slave_index].phy_of_handle =
1277                                 fdtdec_lookup_phandle(fdt, subnode,
1278                                                       "phy-handle");
1279
1280                         if (data->slave_data[slave_index].phy_of_handle >= 0) {
1281                                 data->slave_data[slave_index].phy_addr =
1282                                                 fdtdec_get_int(gd->fdt_blob,
1283                                                 data->slave_data[slave_index].phy_of_handle,
1284                                                                "reg", -1);
1285                         } else {
1286                                 fdtdec_get_int_array(fdt, subnode, "phy_id",
1287                                                      phy_id, 2);
1288                                 data->slave_data[slave_index].phy_addr =
1289                                                 phy_id[1];
1290                         }
1291                         slave_index++;
1292                 }
1293
1294                 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1295                         data->gmii_sel = cpsw_get_addr_by_node(fdt, subnode);
1296
1297                         if (data->gmii_sel == FDT_ADDR_T_NONE) {
1298                                 pr_err("Not able to get gmii_sel reg address\n");
1299                                 return -ENOENT;
1300                         }
1301
1302                         if (fdt_get_property(fdt, subnode, "rmii-clock-ext",
1303                                              NULL))
1304                                 data->rmii_clock_external = true;
1305
1306                         data->phy_sel_compat = fdt_getprop(fdt, subnode,
1307                                                            "compatible", NULL);
1308                         if (!data->phy_sel_compat) {
1309                                 pr_err("Not able to get gmii_sel compatible\n");
1310                                 return -ENOENT;
1311                         }
1312                 }
1313         }
1314
1315         data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1316         data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1317
1318         if (data->slaves == 2) {
1319                 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1320                 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1321         }
1322
1323         ret = ti_cm_get_macid_addr(dev, active_slave, data);
1324         if (ret < 0) {
1325                 pr_err("cpsw read efuse mac failed\n");
1326                 return ret;
1327         }
1328
1329         pdata->phy_interface = data->slave_data[active_slave].phy_if;
1330         if (pdata->phy_interface == -1) {
1331                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1332                 return -EINVAL;
1333         }
1334
1335         return 0;
1336 }
1337
1338 static const struct udevice_id cpsw_eth_ids[] = {
1339         { .compatible = "ti,cpsw" },
1340         { .compatible = "ti,am335x-cpsw" },
1341         { }
1342 };
1343 #endif
1344
1345 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
1346 {
1347         struct cpsw_priv *priv = dev_get_priv(dev);
1348         struct cpsw_platform_data *data = priv->data;
1349
1350         return data->slave_data[slave].phy_addr;
1351 }
1352
1353 U_BOOT_DRIVER(eth_cpsw) = {
1354         .name   = "eth_cpsw",
1355         .id     = UCLASS_ETH,
1356 #if CONFIG_IS_ENABLED(OF_CONTROL)
1357         .of_match = cpsw_eth_ids,
1358         .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1359         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1360 #endif
1361         .probe  = cpsw_eth_probe,
1362         .ops    = &cpsw_eth_ops,
1363         .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1364         .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
1365 };
1366 #endif /* CONFIG_DM_ETH */