1 // SPDX-License-Identifier: GPL-2.0+
3 * CPSW Ethernet Switch Driver
5 * Copyright (C) 2010-2018 Texas Instruments Incorporated - http://www.ti.com/
16 #include <linux/errno.h>
20 #include <asm/arch/cpu.h>
22 #include <fdt_support.h>
24 #include "cpsw_mdio.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 #define BITMASK(bits) (BIT(bits) - 1)
29 #define NUM_DESCS (PKTBUFSRX * 2)
31 #define PKT_MAX (1500 + 14 + 4 + 4)
33 #define GIGABITEN BIT(7)
34 #define FULLDUPLEXEN BIT(0)
37 #define CPDMA_TXCONTROL 0x004
38 #define CPDMA_RXCONTROL 0x014
39 #define CPDMA_SOFTRESET 0x01c
40 #define CPDMA_RXFREE 0x0e0
41 #define CPDMA_TXHDP_VER1 0x100
42 #define CPDMA_TXHDP_VER2 0x200
43 #define CPDMA_RXHDP_VER1 0x120
44 #define CPDMA_RXHDP_VER2 0x220
45 #define CPDMA_TXCP_VER1 0x140
46 #define CPDMA_TXCP_VER2 0x240
47 #define CPDMA_RXCP_VER1 0x160
48 #define CPDMA_RXCP_VER2 0x260
50 /* Descriptor mode bits */
51 #define CPDMA_DESC_SOP BIT(31)
52 #define CPDMA_DESC_EOP BIT(30)
53 #define CPDMA_DESC_OWNER BIT(29)
54 #define CPDMA_DESC_EOQ BIT(28)
57 * This timeout definition is a worst-case ultra defensive measure against
58 * unexpected controller lock ups. Ideally, we should never ever hit this
59 * scenario in practice.
61 #define CPDMA_TIMEOUT 100 /* msecs */
71 struct cpsw_slave_regs {
79 #elif defined(CONFIG_TI814X)
88 struct cpsw_host_regs {
95 u32 cpdma_rx_chan_map;
98 struct cpsw_sliver_regs {
111 #define ALE_ENTRY_BITS 68
112 #define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
115 #define ALE_CONTROL 0x08
116 #define ALE_UNKNOWNVLAN 0x18
117 #define ALE_TABLE_CONTROL 0x20
118 #define ALE_TABLE 0x34
119 #define ALE_PORTCTL 0x40
121 #define ALE_TABLE_WRITE BIT(31)
123 #define ALE_TYPE_FREE 0
124 #define ALE_TYPE_ADDR 1
125 #define ALE_TYPE_VLAN 2
126 #define ALE_TYPE_VLAN_ADDR 3
128 #define ALE_UCAST_PERSISTANT 0
129 #define ALE_UCAST_UNTOUCHED 1
130 #define ALE_UCAST_OUI 2
131 #define ALE_UCAST_TOUCHED 3
133 #define ALE_MCAST_FWD 0
134 #define ALE_MCAST_BLOCK_LEARN_FWD 1
135 #define ALE_MCAST_FWD_LEARN 2
136 #define ALE_MCAST_FWD_2 3
138 enum cpsw_ale_port_state {
139 ALE_PORT_STATE_DISABLE = 0x00,
140 ALE_PORT_STATE_BLOCK = 0x01,
141 ALE_PORT_STATE_LEARN = 0x02,
142 ALE_PORT_STATE_FORWARD = 0x03,
145 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
147 #define ALE_BLOCKED 2
150 struct cpsw_slave_regs *regs;
151 struct cpsw_sliver_regs *sliver;
154 struct cpsw_slave_data *data;
158 /* hardware fields */
163 /* software fields */
169 struct cpdma_desc *head, *tail;
170 void *hdp, *cp, *rxfree;
173 /* AM33xx SoC specific definitions for the CONTROL port */
174 #define AM33XX_GMII_SEL_MODE_MII 0
175 #define AM33XX_GMII_SEL_MODE_RMII 1
176 #define AM33XX_GMII_SEL_MODE_RGMII 2
178 #define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4)
179 #define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5)
180 #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
181 #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
183 #define GMII_SEL_MODE_MASK 0x3
185 #define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld)
186 #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
187 #define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld))
189 #define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld)
190 #define chan_read(chan, fld) __raw_readl((chan)->fld)
191 #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld))
193 #define for_active_slave(slave, priv) \
194 slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave)
195 #define for_each_slave(slave, priv) \
196 for (slave = (priv)->slaves; slave != (priv)->slaves + \
197 ((priv)->data)->slaves; slave++)
203 struct eth_device *dev;
205 struct cpsw_platform_data *data;
208 struct cpsw_regs *regs;
210 struct cpsw_host_regs *host_port_regs;
213 struct cpdma_desc *descs;
214 struct cpdma_desc *desc_free;
215 struct cpdma_chan rx_chan, tx_chan;
217 struct cpsw_slave *slaves;
218 struct phy_device *phydev;
224 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
230 idx = 2 - idx; /* flip */
231 return (ale_entry[idx] >> start) & BITMASK(bits);
234 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
239 value &= BITMASK(bits);
242 idx = 2 - idx; /* flip */
243 ale_entry[idx] &= ~(BITMASK(bits) << start);
244 ale_entry[idx] |= (value << start);
247 #define DEFINE_ALE_FIELD(name, start, bits) \
248 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
250 return cpsw_ale_get_field(ale_entry, start, bits); \
252 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
254 cpsw_ale_set_field(ale_entry, start, bits, value); \
257 DEFINE_ALE_FIELD(entry_type, 60, 2)
258 DEFINE_ALE_FIELD(mcast_state, 62, 2)
259 DEFINE_ALE_FIELD(port_mask, 66, 3)
260 DEFINE_ALE_FIELD(ucast_type, 62, 2)
261 DEFINE_ALE_FIELD(port_num, 66, 2)
262 DEFINE_ALE_FIELD(blocked, 65, 1)
263 DEFINE_ALE_FIELD(secure, 64, 1)
264 DEFINE_ALE_FIELD(mcast, 40, 1)
266 /* The MAC address field in the ALE entry cannot be macroized as above */
267 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
271 for (i = 0; i < 6; i++)
272 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
275 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
279 for (i = 0; i < 6; i++)
280 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
283 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
287 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
289 for (i = 0; i < ALE_ENTRY_WORDS; i++)
290 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
295 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
299 for (i = 0; i < ALE_ENTRY_WORDS; i++)
300 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
302 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
307 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
309 u32 ale_entry[ALE_ENTRY_WORDS];
312 for (idx = 0; idx < priv->data->ale_entries; idx++) {
315 cpsw_ale_read(priv, idx, ale_entry);
316 type = cpsw_ale_get_entry_type(ale_entry);
317 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
319 cpsw_ale_get_addr(ale_entry, entry_addr);
320 if (memcmp(entry_addr, addr, 6) == 0)
326 static int cpsw_ale_match_free(struct cpsw_priv *priv)
328 u32 ale_entry[ALE_ENTRY_WORDS];
331 for (idx = 0; idx < priv->data->ale_entries; idx++) {
332 cpsw_ale_read(priv, idx, ale_entry);
333 type = cpsw_ale_get_entry_type(ale_entry);
334 if (type == ALE_TYPE_FREE)
340 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
342 u32 ale_entry[ALE_ENTRY_WORDS];
345 for (idx = 0; idx < priv->data->ale_entries; idx++) {
346 cpsw_ale_read(priv, idx, ale_entry);
347 type = cpsw_ale_get_entry_type(ale_entry);
348 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
350 if (cpsw_ale_get_mcast(ale_entry))
352 type = cpsw_ale_get_ucast_type(ale_entry);
353 if (type != ALE_UCAST_PERSISTANT &&
354 type != ALE_UCAST_OUI)
360 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
363 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
366 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
367 cpsw_ale_set_addr(ale_entry, addr);
368 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
369 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
370 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
371 cpsw_ale_set_port_num(ale_entry, port);
373 idx = cpsw_ale_match_addr(priv, addr);
375 idx = cpsw_ale_match_free(priv);
377 idx = cpsw_ale_find_ageable(priv);
381 cpsw_ale_write(priv, idx, ale_entry);
385 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
388 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
391 idx = cpsw_ale_match_addr(priv, addr);
393 cpsw_ale_read(priv, idx, ale_entry);
395 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
396 cpsw_ale_set_addr(ale_entry, addr);
397 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
399 mask = cpsw_ale_get_port_mask(ale_entry);
401 cpsw_ale_set_port_mask(ale_entry, port_mask);
404 idx = cpsw_ale_match_free(priv);
406 idx = cpsw_ale_find_ageable(priv);
410 cpsw_ale_write(priv, idx, ale_entry);
414 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
416 u32 tmp, mask = BIT(bit);
418 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL);
420 tmp |= val ? mask : 0;
421 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
424 #define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
425 #define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
426 #define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
428 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
431 int offset = ALE_PORTCTL + 4 * port;
434 tmp = __raw_readl(priv->ale_regs + offset);
437 __raw_writel(tmp, priv->ale_regs + offset);
440 /* Set a self-clearing bit in a register, and wait for it to clear */
441 static inline void setbit_and_wait_for_clear32(void *addr)
443 __raw_writel(CLEAR_BIT, addr);
444 while (__raw_readl(addr) & CLEAR_BIT)
448 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
449 ((mac)[2] << 16) | ((mac)[3] << 24))
450 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
452 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
453 struct cpsw_priv *priv)
456 struct eth_pdata *pdata = dev_get_platdata(priv->dev);
458 writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
459 writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
461 __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
462 __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
466 static int cpsw_slave_update_link(struct cpsw_slave *slave,
467 struct cpsw_priv *priv, int *link)
469 struct phy_device *phy;
477 ret = phy_startup(phy);
484 if (phy->link) { /* link up */
485 mac_control = priv->data->mac_control;
486 if (phy->speed == 1000)
487 mac_control |= GIGABITEN;
488 if (phy->duplex == DUPLEX_FULL)
489 mac_control |= FULLDUPLEXEN;
490 if (phy->speed == 100)
491 mac_control |= MIIEN;
494 if (mac_control == slave->mac_control)
498 printf("link up on port %d, speed %d, %s duplex\n",
499 slave->slave_num, phy->speed,
500 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
502 printf("link down on port %d\n", slave->slave_num);
505 __raw_writel(mac_control, &slave->sliver->mac_control);
506 slave->mac_control = mac_control;
512 static int cpsw_update_link(struct cpsw_priv *priv)
515 struct cpsw_slave *slave;
517 for_active_slave(slave, priv)
518 ret = cpsw_slave_update_link(slave, priv, NULL);
523 static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
525 if (priv->host_port == 0)
526 return slave_num + 1;
531 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
535 setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
537 /* setup priority mapping */
538 __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
539 __raw_writel(0x33221100, &slave->regs->tx_pri_map);
541 /* setup max packet size, and mac address */
542 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
543 cpsw_set_slave_mac(slave, priv);
545 slave->mac_control = 0; /* no link yet */
547 /* enable forwarding */
548 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
549 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
551 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
553 priv->phy_mask |= 1 << slave->data->phy_addr;
556 static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
558 struct cpdma_desc *desc = priv->desc_free;
561 priv->desc_free = desc_read_ptr(desc, hw_next);
565 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
568 desc_write(desc, hw_next, priv->desc_free);
569 priv->desc_free = desc;
573 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
574 void *buffer, int len)
576 struct cpdma_desc *desc, *prev;
579 desc = cpdma_desc_alloc(priv);
586 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
588 desc_write(desc, hw_next, 0);
589 desc_write(desc, hw_buffer, buffer);
590 desc_write(desc, hw_len, len);
591 desc_write(desc, hw_mode, mode | len);
592 desc_write(desc, sw_buffer, buffer);
593 desc_write(desc, sw_len, len);
596 /* simple case - first packet enqueued */
599 chan_write(chan, hdp, desc);
603 /* not the first packet - enqueue at the tail */
605 desc_write(prev, hw_next, desc);
608 /* next check if EOQ has been triggered already */
609 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
610 chan_write(chan, hdp, desc);
614 chan_write(chan, rxfree, 1);
618 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
619 void **buffer, int *len)
621 struct cpdma_desc *desc = chan->head;
627 status = desc_read(desc, hw_mode);
630 *len = status & 0x7ff;
633 *buffer = desc_read_ptr(desc, sw_buffer);
635 if (status & CPDMA_DESC_OWNER) {
636 if (chan_read(chan, hdp) == 0) {
637 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER)
638 chan_write(chan, hdp, desc);
644 chan->head = desc_read_ptr(desc, hw_next);
645 chan_write(chan, cp, desc);
647 cpdma_desc_free(priv, desc);
651 static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr)
653 struct cpsw_slave *slave;
656 /* soft reset the controller and initialize priv */
657 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
659 /* initialize and reset the address lookup engine */
660 cpsw_ale_enable(priv, 1);
661 cpsw_ale_clear(priv, 1);
662 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
664 /* setup host port priority mapping */
665 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
666 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
668 /* disable priority elevation and enable statistics on all ports */
669 __raw_writel(0, &priv->regs->ptype);
671 /* enable statistics collection only on the host port */
672 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
673 __raw_writel(0x7, &priv->regs->stat_port_en);
675 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
677 cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE);
678 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
680 for_active_slave(slave, priv)
681 cpsw_slave_init(slave, priv);
683 ret = cpsw_update_link(priv);
687 /* init descriptor pool */
688 for (i = 0; i < NUM_DESCS; i++) {
689 desc_write(&priv->descs[i], hw_next,
690 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]);
692 priv->desc_free = &priv->descs[0];
694 /* initialize channels */
695 if (priv->data->version == CPSW_CTRL_VERSION_2) {
696 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
697 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2;
698 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2;
699 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
701 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
702 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2;
703 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2;
705 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
706 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1;
707 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1;
708 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
710 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
711 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1;
712 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1;
715 /* clear dma state */
716 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
718 if (priv->data->version == CPSW_CTRL_VERSION_2) {
719 for (i = 0; i < priv->data->channels; i++) {
720 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4
722 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
724 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4
726 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4
728 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4
732 for (i = 0; i < priv->data->channels; i++) {
733 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4
735 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4
737 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4
739 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4
741 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4
747 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
748 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
750 /* submit rx descs */
751 for (i = 0; i < PKTBUFSRX; i++) {
752 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
755 printf("error %d submitting rx desc\n", ret);
764 static int cpsw_reap_completed_packets(struct cpsw_priv *priv)
766 int timeout = CPDMA_TIMEOUT;
768 /* reap completed packets */
770 (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0))
776 static void _cpsw_halt(struct cpsw_priv *priv)
778 cpsw_reap_completed_packets(priv);
780 writel(0, priv->dma_regs + CPDMA_TXCONTROL);
781 writel(0, priv->dma_regs + CPDMA_RXCONTROL);
783 /* soft reset the controller and initialize priv */
784 setbit_and_wait_for_clear32(&priv->regs->soft_reset);
786 /* clear dma state */
787 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
791 static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length)
795 flush_dcache_range((unsigned long)packet,
796 (unsigned long)packet + ALIGN(length, PKTALIGN));
798 timeout = cpsw_reap_completed_packets(priv);
800 printf("cpdma_process timeout\n");
804 return cpdma_submit(priv, &priv->tx_chan, packet, length);
807 static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt)
813 ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len);
817 invalidate_dcache_range((unsigned long)buffer,
818 (unsigned long)buffer + PKTSIZE_ALIGN);
824 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
825 struct cpsw_priv *priv)
827 void *regs = priv->regs;
828 struct cpsw_slave_data *data = priv->data->slave_data + slave_num;
829 slave->slave_num = slave_num;
831 slave->regs = regs + data->slave_reg_ofs;
832 slave->sliver = regs + data->sliver_reg_ofs;
835 static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
837 struct phy_device *phydev;
838 u32 supported = PHY_GBIT_FEATURES;
840 phydev = phy_connect(priv->bus,
841 slave->data->phy_addr,
843 slave->data->phy_if);
848 phydev->supported &= supported;
849 phydev->advertising = phydev->supported;
852 if (slave->data->phy_of_handle)
853 phydev->node = offset_to_ofnode(slave->data->phy_of_handle);
856 priv->phydev = phydev;
862 static void cpsw_phy_addr_update(struct cpsw_priv *priv)
864 struct cpsw_platform_data *data = priv->data;
865 u16 alive = cpsw_mdio_get_alive(priv->bus);
866 int active = data->active_slave;
867 int new_addr = ffs(alive) - 1;
870 * If there is only one phy alive and its address does not match
871 * that of active slave, then phy address can safely be updated.
873 if (hweight16(alive) == 1 &&
874 data->slave_data[active].phy_addr != new_addr) {
875 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n",
876 active, data->slave_data[active].phy_addr, new_addr);
877 data->slave_data[active].phy_addr = new_addr;
881 int _cpsw_register(struct cpsw_priv *priv)
883 struct cpsw_slave *slave;
884 struct cpsw_platform_data *data = priv->data;
885 void *regs = (void *)data->cpsw_base;
887 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves);
892 priv->host_port = data->host_port_num;
894 priv->host_port_regs = regs + data->host_port_reg_ofs;
895 priv->dma_regs = regs + data->cpdma_reg_ofs;
896 priv->ale_regs = regs + data->ale_reg_ofs;
897 priv->descs = (void *)regs + data->bd_ram_ofs;
901 for_each_slave(slave, priv) {
902 cpsw_slave_setup(slave, idx, priv);
906 priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0);
910 cpsw_phy_addr_update(priv);
912 for_active_slave(slave, priv)
913 cpsw_phy_init(priv, slave);
918 #ifndef CONFIG_DM_ETH
919 static int cpsw_init(struct eth_device *dev, bd_t *bis)
921 struct cpsw_priv *priv = dev->priv;
923 return _cpsw_init(priv, dev->enetaddr);
926 static void cpsw_halt(struct eth_device *dev)
928 struct cpsw_priv *priv = dev->priv;
930 return _cpsw_halt(priv);
933 static int cpsw_send(struct eth_device *dev, void *packet, int length)
935 struct cpsw_priv *priv = dev->priv;
937 return _cpsw_send(priv, packet, length);
940 static int cpsw_recv(struct eth_device *dev)
942 struct cpsw_priv *priv = dev->priv;
946 len = _cpsw_recv(priv, &pkt);
949 net_process_received_packet(pkt, len);
950 cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
956 int cpsw_register(struct cpsw_platform_data *data)
958 struct cpsw_priv *priv;
959 struct eth_device *dev;
962 dev = calloc(sizeof(*dev), 1);
966 priv = calloc(sizeof(*priv), 1);
975 strcpy(dev->name, "cpsw");
977 dev->init = cpsw_init;
978 dev->halt = cpsw_halt;
979 dev->send = cpsw_send;
980 dev->recv = cpsw_recv;
985 ret = _cpsw_register(priv);
996 static int cpsw_eth_start(struct udevice *dev)
998 struct eth_pdata *pdata = dev_get_platdata(dev);
999 struct cpsw_priv *priv = dev_get_priv(dev);
1001 return _cpsw_init(priv, pdata->enetaddr);
1004 static int cpsw_eth_send(struct udevice *dev, void *packet, int length)
1006 struct cpsw_priv *priv = dev_get_priv(dev);
1008 return _cpsw_send(priv, packet, length);
1011 static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp)
1013 struct cpsw_priv *priv = dev_get_priv(dev);
1015 return _cpsw_recv(priv, packetp);
1018 static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet,
1021 struct cpsw_priv *priv = dev_get_priv(dev);
1023 return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE);
1026 static void cpsw_eth_stop(struct udevice *dev)
1028 struct cpsw_priv *priv = dev_get_priv(dev);
1030 return _cpsw_halt(priv);
1033 static const struct eth_ops cpsw_eth_ops = {
1034 .start = cpsw_eth_start,
1035 .send = cpsw_eth_send,
1036 .recv = cpsw_eth_recv,
1037 .free_pkt = cpsw_eth_free_pkt,
1038 .stop = cpsw_eth_stop,
1041 static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
1043 return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL,
1047 static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv,
1048 phy_interface_t phy_mode)
1053 bool rgmii_id = false;
1054 int slave = priv->data->active_slave;
1056 reg = readl(priv->data->gmii_sel);
1059 case PHY_INTERFACE_MODE_RMII:
1060 mode = AM33XX_GMII_SEL_MODE_RMII;
1063 case PHY_INTERFACE_MODE_RGMII:
1064 mode = AM33XX_GMII_SEL_MODE_RGMII;
1066 case PHY_INTERFACE_MODE_RGMII_ID:
1067 case PHY_INTERFACE_MODE_RGMII_RXID:
1068 case PHY_INTERFACE_MODE_RGMII_TXID:
1069 mode = AM33XX_GMII_SEL_MODE_RGMII;
1073 case PHY_INTERFACE_MODE_MII:
1075 mode = AM33XX_GMII_SEL_MODE_MII;
1079 mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
1082 if (priv->data->rmii_clock_external) {
1084 mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
1086 mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
1091 mode |= AM33XX_GMII_SEL_RGMII1_IDMODE;
1093 mode |= AM33XX_GMII_SEL_RGMII2_IDMODE;
1099 writel(reg, priv->data->gmii_sel);
1102 static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv,
1103 phy_interface_t phy_mode)
1108 int slave = priv->data->active_slave;
1110 reg = readl(priv->data->gmii_sel);
1113 case PHY_INTERFACE_MODE_RMII:
1114 mode = AM33XX_GMII_SEL_MODE_RMII;
1117 case PHY_INTERFACE_MODE_RGMII:
1118 case PHY_INTERFACE_MODE_RGMII_ID:
1119 case PHY_INTERFACE_MODE_RGMII_RXID:
1120 case PHY_INTERFACE_MODE_RGMII_TXID:
1121 mode = AM33XX_GMII_SEL_MODE_RGMII;
1124 case PHY_INTERFACE_MODE_MII:
1126 mode = AM33XX_GMII_SEL_MODE_MII;
1132 mask = GMII_SEL_MODE_MASK;
1135 mask = GMII_SEL_MODE_MASK << 4;
1139 dev_err(priv->dev, "invalid slave number...\n");
1143 if (priv->data->rmii_clock_external)
1144 dev_err(priv->dev, "RMII External clock is not supported\n");
1149 writel(reg, priv->data->gmii_sel);
1152 static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat,
1153 phy_interface_t phy_mode)
1155 if (!strcmp(compat, "ti,am3352-cpsw-phy-sel"))
1156 cpsw_gmii_sel_am3352(priv, phy_mode);
1157 if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel"))
1158 cpsw_gmii_sel_am3352(priv, phy_mode);
1159 else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel"))
1160 cpsw_gmii_sel_dra7xx(priv, phy_mode);
1163 static int cpsw_eth_probe(struct udevice *dev)
1165 struct cpsw_priv *priv = dev_get_priv(dev);
1166 struct eth_pdata *pdata = dev_get_platdata(dev);
1169 priv->data = pdata->priv_pdata;
1170 ti_cm_get_macid(dev, priv->data, pdata->enetaddr);
1171 /* Select phy interface in control module */
1172 cpsw_phy_sel(priv, priv->data->phy_sel_compat,
1173 pdata->phy_interface);
1175 return _cpsw_register(priv);
1178 #if CONFIG_IS_ENABLED(OF_CONTROL)
1179 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
1181 struct eth_pdata *pdata = dev_get_platdata(dev);
1182 struct cpsw_platform_data *data;
1183 struct gpio_desc *mode_gpios;
1184 const char *phy_mode;
1185 const void *fdt = gd->fdt_blob;
1186 int node = dev_of_offset(dev);
1188 int slave_index = 0;
1193 data = calloc(1, sizeof(struct cpsw_platform_data));
1194 pdata->priv_pdata = data;
1195 pdata->iobase = devfdt_get_addr(dev);
1196 data->version = CPSW_CTRL_VERSION_2;
1197 data->bd_ram_ofs = CPSW_BD_OFFSET;
1198 data->ale_reg_ofs = CPSW_ALE_OFFSET;
1199 data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET;
1200 data->mdio_div = CPSW_MDIO_DIV;
1201 data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
1203 pdata->phy_interface = -1;
1205 data->cpsw_base = pdata->iobase;
1206 data->channels = fdtdec_get_int(fdt, node, "cpdma_channels", -1);
1207 if (data->channels <= 0) {
1208 printf("error: cpdma_channels not found in dt\n");
1212 data->slaves = fdtdec_get_int(fdt, node, "slaves", -1);
1213 if (data->slaves <= 0) {
1214 printf("error: slaves not found in dt\n");
1217 data->slave_data = malloc(sizeof(struct cpsw_slave_data) *
1220 data->ale_entries = fdtdec_get_int(fdt, node, "ale_entries", -1);
1221 if (data->ale_entries <= 0) {
1222 printf("error: ale_entries not found in dt\n");
1226 data->bd_ram_ofs = fdtdec_get_int(fdt, node, "bd_ram_size", -1);
1227 if (data->bd_ram_ofs <= 0) {
1228 printf("error: bd_ram_size not found in dt\n");
1232 data->mac_control = fdtdec_get_int(fdt, node, "mac_control", -1);
1233 if (data->mac_control <= 0) {
1234 printf("error: ale_entries not found in dt\n");
1238 num_mode_gpios = gpio_get_list_count(dev, "mode-gpios");
1239 if (num_mode_gpios > 0) {
1240 mode_gpios = malloc(sizeof(struct gpio_desc) *
1242 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios,
1243 num_mode_gpios, GPIOD_IS_OUT);
1247 active_slave = fdtdec_get_int(fdt, node, "active_slave", 0);
1248 data->active_slave = active_slave;
1250 fdt_for_each_subnode(subnode, fdt, node) {
1254 name = fdt_get_name(fdt, subnode, &len);
1255 if (!strncmp(name, "mdio", 4)) {
1258 mdio_base = cpsw_get_addr_by_node(fdt, subnode);
1259 if (mdio_base == FDT_ADDR_T_NONE) {
1260 pr_err("Not able to get MDIO address space\n");
1263 data->mdio_base = mdio_base;
1266 if (!strncmp(name, "slave", 5)) {
1269 if (slave_index >= data->slaves)
1271 phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
1273 data->slave_data[slave_index].phy_if =
1274 phy_get_interface_by_name(phy_mode);
1276 data->slave_data[slave_index].phy_of_handle =
1277 fdtdec_lookup_phandle(fdt, subnode,
1280 if (data->slave_data[slave_index].phy_of_handle >= 0) {
1281 data->slave_data[slave_index].phy_addr =
1282 fdtdec_get_int(gd->fdt_blob,
1283 data->slave_data[slave_index].phy_of_handle,
1286 fdtdec_get_int_array(fdt, subnode, "phy_id",
1288 data->slave_data[slave_index].phy_addr =
1294 if (!strncmp(name, "cpsw-phy-sel", 12)) {
1295 data->gmii_sel = cpsw_get_addr_by_node(fdt, subnode);
1297 if (data->gmii_sel == FDT_ADDR_T_NONE) {
1298 pr_err("Not able to get gmii_sel reg address\n");
1302 if (fdt_get_property(fdt, subnode, "rmii-clock-ext",
1304 data->rmii_clock_external = true;
1306 data->phy_sel_compat = fdt_getprop(fdt, subnode,
1307 "compatible", NULL);
1308 if (!data->phy_sel_compat) {
1309 pr_err("Not able to get gmii_sel compatible\n");
1315 data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET;
1316 data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET;
1318 if (data->slaves == 2) {
1319 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET;
1320 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
1323 ret = ti_cm_get_macid_addr(dev, active_slave, data);
1325 pr_err("cpsw read efuse mac failed\n");
1329 pdata->phy_interface = data->slave_data[active_slave].phy_if;
1330 if (pdata->phy_interface == -1) {
1331 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1338 static const struct udevice_id cpsw_eth_ids[] = {
1339 { .compatible = "ti,cpsw" },
1340 { .compatible = "ti,am335x-cpsw" },
1345 int cpsw_get_slave_phy_addr(struct udevice *dev, int slave)
1347 struct cpsw_priv *priv = dev_get_priv(dev);
1348 struct cpsw_platform_data *data = priv->data;
1350 return data->slave_data[slave].phy_addr;
1353 U_BOOT_DRIVER(eth_cpsw) = {
1356 #if CONFIG_IS_ENABLED(OF_CONTROL)
1357 .of_match = cpsw_eth_ids,
1358 .ofdata_to_platdata = cpsw_eth_ofdata_to_platdata,
1359 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1361 .probe = cpsw_eth_probe,
1362 .ops = &cpsw_eth_ops,
1363 .priv_auto_alloc_size = sizeof(struct cpsw_priv),
1364 .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
1366 #endif /* CONFIG_DM_ETH */