1 // SPDX-License-Identifier: GPL-2.0+
3 * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
5 * Copyright (C) 2019, Texas Instruments, Incorporated
11 #include <asm/processor.h>
15 #include <dma-uclass.h>
16 #include <dm/of_access.h>
20 #include <power-domain.h>
21 #include <linux/soc/ti/ti-udma.h>
23 #include "cpsw_mdio.h"
25 #define AM65_CPSW_CPSWNU_MAX_PORTS 2
27 #define AM65_CPSW_SS_BASE 0x0
28 #define AM65_CPSW_SGMII_BASE 0x100
29 #define AM65_CPSW_MDIO_BASE 0xf00
30 #define AM65_CPSW_XGMII_BASE 0x2100
31 #define AM65_CPSW_CPSW_NU_BASE 0x20000
32 #define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000
34 #define AM65_CPSW_CPSW_NU_PORTS_OFFSET 0x1000
35 #define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET 0x330
37 #define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000
39 #define AM65_CPSW_CTL_REG 0x4
40 #define AM65_CPSW_STAT_PORT_EN_REG 0x14
41 #define AM65_CPSW_PTYPE_REG 0x18
43 #define AM65_CPSW_CTL_REG_P0_ENABLE BIT(2)
44 #define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE BIT(13)
45 #define AM65_CPSW_CTL_REG_P0_RX_PAD BIT(14)
47 #define AM65_CPSW_P0_FLOW_ID_REG 0x8
48 #define AM65_CPSW_PN_RX_MAXLEN_REG 0x24
49 #define AM65_CPSW_PN_REG_SA_L 0x308
50 #define AM65_CPSW_PN_REG_SA_H 0x30c
52 #define AM65_CPSW_ALE_CTL_REG 0x8
53 #define AM65_CPSW_ALE_CTL_REG_ENABLE BIT(31)
54 #define AM65_CPSW_ALE_CTL_REG_RESET_TBL BIT(30)
55 #define AM65_CPSW_ALE_CTL_REG_BYPASS BIT(4)
56 #define AM65_CPSW_ALE_PN_CTL_REG(x) (0x40 + (x) * 4)
57 #define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3
58 #define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11)
60 #define AM65_CPSW_MACSL_CTL_REG 0x0
61 #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15)
62 #define AM65_CPSW_MACSL_CTL_REG_GIG BIT(7)
63 #define AM65_CPSW_MACSL_CTL_REG_GMII_EN BIT(5)
64 #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK BIT(1)
65 #define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX BIT(0)
66 #define AM65_CPSW_MACSL_RESET_REG 0x8
67 #define AM65_CPSW_MACSL_RESET_REG_RESET BIT(0)
68 #define AM65_CPSW_MACSL_STATUS_REG 0x4
69 #define AM65_CPSW_MACSL_RESET_REG_PN_IDLE BIT(31)
70 #define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE BIT(30)
71 #define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE BIT(29)
72 #define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE BIT(28)
73 #define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \
74 (AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \
75 AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \
76 AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \
77 AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE)
79 #define AM65_CPSW_CPPI_PKT_TYPE 0x7
81 struct am65_cpsw_port {
83 fdt_addr_t macsl_base;
88 struct am65_cpsw_common {
98 struct power_domain pwrdmn;
101 struct am65_cpsw_port ports[AM65_CPSW_CPSWNU_MAX_PORTS];
114 struct am65_cpsw_priv {
116 struct am65_cpsw_common *cpsw_common;
119 struct phy_device *phydev;
126 #define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
128 #define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
132 #define UDMA_RX_DESC_NUM PKTBUFSRX
134 #define UDMA_RX_DESC_NUM 4
137 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
138 ((mac)[2] << 16) | ((mac)[3] << 24))
139 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
141 static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave,
145 slave->port_base + AM65_CPSW_PN_REG_SA_H);
147 slave->port_base + AM65_CPSW_PN_REG_SA_L);
150 int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave)
154 /* Set the soft reset bit */
155 writel(AM65_CPSW_MACSL_RESET_REG_RESET,
156 slave->macsl_base + AM65_CPSW_MACSL_RESET_REG);
158 while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) &
159 AM65_CPSW_MACSL_RESET_REG_RESET) && i--)
162 /* Timeout on the reset */
166 static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave)
170 while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) &
171 AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--)
177 static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
179 struct am65_cpsw_common *common = priv->cpsw_common;
180 struct am65_cpsw_port *port = &common->ports[priv->port_id];
181 struct phy_device *phy = priv->phydev;
184 if (phy->link) { /* link up */
185 mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/
186 AM65_CPSW_MACSL_CTL_REG_GMII_EN;
187 if (phy->speed == 1000)
188 mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
189 if (phy->duplex == DUPLEX_FULL)
190 mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
191 if (phy->speed == 100)
192 mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
195 if (mac_control == port->mac_control)
199 printf("link up on port %d, speed %d, %s duplex\n",
200 priv->port_id, phy->speed,
201 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
203 printf("link down on port %d\n", priv->port_id);
206 writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
207 port->mac_control = mac_control;
213 #define AM65_GMII_SEL_MODE_MII 0
214 #define AM65_GMII_SEL_MODE_RMII 1
215 #define AM65_GMII_SEL_MODE_RGMII 2
217 #define AM65_GMII_SEL_RGMII_IDMODE BIT(4)
219 static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
220 phy_interface_t phy_mode, int slave)
222 struct am65_cpsw_common *common = priv->cpsw_common;
225 bool rgmii_id = false;
227 reg = readl(common->gmii_sel);
229 dev_dbg(common->dev, "old gmii_sel: %08x\n", reg);
232 case PHY_INTERFACE_MODE_RMII:
233 mode = AM65_GMII_SEL_MODE_RMII;
236 case PHY_INTERFACE_MODE_RGMII:
237 case PHY_INTERFACE_MODE_RGMII_RXID:
238 mode = AM65_GMII_SEL_MODE_RGMII;
241 case PHY_INTERFACE_MODE_RGMII_ID:
242 case PHY_INTERFACE_MODE_RGMII_TXID:
243 mode = AM65_GMII_SEL_MODE_RGMII;
248 dev_warn(common->dev,
249 "Unsupported PHY mode: %u. Defaulting to MII.\n",
252 case PHY_INTERFACE_MODE_MII:
253 mode = AM65_GMII_SEL_MODE_MII;
258 mode |= AM65_GMII_SEL_RGMII_IDMODE;
261 dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
263 writel(reg, common->gmii_sel);
265 reg = readl(common->gmii_sel);
268 "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
272 static int am65_cpsw_start(struct udevice *dev)
274 struct eth_pdata *pdata = dev_get_platdata(dev);
275 struct am65_cpsw_priv *priv = dev_get_priv(dev);
276 struct am65_cpsw_common *common = priv->cpsw_common;
277 struct am65_cpsw_port *port = &common->ports[priv->port_id];
278 struct am65_cpsw_port *port0 = &common->ports[0];
281 ret = power_domain_on(&common->pwrdmn);
283 dev_err(dev, "power_domain_on() failed %d\n", ret);
287 ret = clk_enable(&common->fclk);
289 dev_err(dev, "clk enabled failed %d\n", ret);
295 ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx);
297 dev_err(dev, "TX dma get failed %d\n", ret);
300 ret = dma_get_by_name(common->dev, "rx", &common->dma_rx);
302 dev_err(dev, "RX dma get failed %d\n", ret);
306 for (i = 0; i < UDMA_RX_DESC_NUM; i++) {
307 ret = dma_prepare_rcv_buf(&common->dma_rx,
311 dev_err(dev, "RX dma add buf failed %d\n", ret);
316 ret = dma_enable(&common->dma_tx);
318 dev_err(dev, "TX dma_enable failed %d\n", ret);
321 ret = dma_enable(&common->dma_rx);
323 dev_err(dev, "RX dma_enable failed %d\n", ret);
327 /* Control register */
328 writel(AM65_CPSW_CTL_REG_P0_ENABLE |
329 AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE |
330 AM65_CPSW_CTL_REG_P0_RX_PAD,
331 common->cpsw_base + AM65_CPSW_CTL_REG);
333 /* disable priority elevation */
334 writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG);
336 /* enable statistics */
337 writel(BIT(0) | BIT(priv->port_id),
338 common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG);
340 /* Port 0 length register */
341 writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
343 /* set base flow_id */
344 writel(common->rflow_id_base,
345 port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);
347 /* Reset and enable the ALE */
348 writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL |
349 AM65_CPSW_ALE_CTL_REG_BYPASS,
350 common->ale_base + AM65_CPSW_ALE_CTL_REG);
352 /* port 0 put into forward mode */
353 writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
354 common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
356 /* PORT x configuration */
358 /* Port x Max length register */
359 writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
362 am65_cpsw_set_sl_mac(port, pdata->enetaddr);
364 /* Port x ALE: mac_only, Forwarding */
365 writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY |
366 AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
367 common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
369 port->mac_control = 0;
370 if (!am65_cpsw_macsl_reset(port)) {
371 dev_err(dev, "mac_sl reset failed\n");
376 ret = phy_startup(priv->phydev);
378 dev_err(dev, "phy_startup failed\n");
382 ret = am65_cpsw_update_link(priv);
385 goto err_phy_shutdown;
388 common->started = true;
393 phy_shutdown(priv->phydev);
396 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
397 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
398 if (!am65_cpsw_macsl_wait_for_idle(port))
399 dev_err(dev, "mac_sl idle timeout\n");
400 writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
401 writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
402 writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
404 dma_disable(&common->dma_rx);
406 dma_disable(&common->dma_tx);
408 dma_free(&common->dma_rx);
410 dma_free(&common->dma_tx);
412 clk_disable(&common->fclk);
414 power_domain_off(&common->pwrdmn);
416 dev_err(dev, "%s end error\n", __func__);
421 static int am65_cpsw_send(struct udevice *dev, void *packet, int length)
423 struct am65_cpsw_priv *priv = dev_get_priv(dev);
424 struct am65_cpsw_common *common = priv->cpsw_common;
425 struct ti_udma_drv_packet_data packet_data;
428 packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE;
429 packet_data.dest_tag = priv->port_id;
430 ret = dma_send(&common->dma_tx, packet, length, &packet_data);
432 dev_err(dev, "TX dma_send failed %d\n", ret);
439 static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp)
441 struct am65_cpsw_priv *priv = dev_get_priv(dev);
442 struct am65_cpsw_common *common = priv->cpsw_common;
444 /* try to receive a new packet */
445 return dma_receive(&common->dma_rx, (void **)packetp, NULL);
448 static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length)
450 struct am65_cpsw_priv *priv = dev_get_priv(dev);
451 struct am65_cpsw_common *common = priv->cpsw_common;
455 u32 pkt = common->rx_next % UDMA_RX_DESC_NUM;
457 ret = dma_prepare_rcv_buf(&common->dma_rx,
461 dev_err(dev, "RX dma free_pkt failed %d\n", ret);
468 static void am65_cpsw_stop(struct udevice *dev)
470 struct am65_cpsw_priv *priv = dev_get_priv(dev);
471 struct am65_cpsw_common *common = priv->cpsw_common;
472 struct am65_cpsw_port *port = &common->ports[priv->port_id];
474 if (!common->started)
477 phy_shutdown(priv->phydev);
479 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
480 writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
481 if (!am65_cpsw_macsl_wait_for_idle(port))
482 dev_err(dev, "mac_sl idle timeout\n");
483 writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
484 writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
485 writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
487 dma_disable(&common->dma_tx);
488 dma_free(&common->dma_tx);
490 dma_disable(&common->dma_rx);
491 dma_free(&common->dma_rx);
493 common->started = false;
496 static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
498 struct am65_cpsw_priv *priv = dev_get_priv(dev);
499 struct am65_cpsw_common *common = priv->cpsw_common;
500 struct eth_pdata *pdata = dev_get_platdata(dev);
503 if (common->mac_efuse == FDT_ADDR_T_NONE)
506 mac_lo = readl(common->mac_efuse);
507 mac_hi = readl(common->mac_efuse + 4);
508 pdata->enetaddr[0] = (mac_hi >> 8) & 0xff;
509 pdata->enetaddr[1] = mac_hi & 0xff;
510 pdata->enetaddr[2] = (mac_lo >> 24) & 0xff;
511 pdata->enetaddr[3] = (mac_lo >> 16) & 0xff;
512 pdata->enetaddr[4] = (mac_lo >> 8) & 0xff;
513 pdata->enetaddr[5] = mac_lo & 0xff;
518 static const struct eth_ops am65_cpsw_ops = {
519 .start = am65_cpsw_start,
520 .send = am65_cpsw_send,
521 .recv = am65_cpsw_recv,
522 .free_pkt = am65_cpsw_free_pkt,
523 .stop = am65_cpsw_stop,
524 .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
527 static int am65_cpsw_mdio_init(struct udevice *dev)
529 struct am65_cpsw_priv *priv = dev_get_priv(dev);
530 struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
532 if (!priv->has_phy || cpsw_common->bus)
535 cpsw_common->bus = cpsw_mdio_init(dev->name,
536 cpsw_common->mdio_base,
537 cpsw_common->bus_freq,
538 clk_get_rate(&cpsw_common->fclk));
539 if (!cpsw_common->bus)
545 static int am65_cpsw_phy_init(struct udevice *dev)
547 struct am65_cpsw_priv *priv = dev_get_priv(dev);
548 struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
549 struct eth_pdata *pdata = dev_get_platdata(dev);
550 struct phy_device *phydev;
551 u32 supported = PHY_GBIT_FEATURES;
554 phydev = phy_connect(cpsw_common->bus,
557 pdata->phy_interface);
560 dev_err(dev, "phy_connect() failed\n");
564 phydev->supported &= supported;
565 if (pdata->max_speed) {
566 ret = phy_set_supported(phydev, pdata->max_speed);
570 phydev->advertising = phydev->supported;
572 if (ofnode_valid(priv->phy_node))
573 phydev->node = priv->phy_node;
575 priv->phydev = phydev;
576 ret = phy_config(phydev);
578 pr_err("phy_config() failed: %d", ret);
583 static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np)
585 struct eth_pdata *pdata = dev_get_platdata(dev);
586 struct am65_cpsw_priv *priv = dev_get_priv(dev);
587 struct ofnode_phandle_args out_args;
588 const char *phy_mode;
591 phy_mode = ofnode_read_string(port_np, "phy-mode");
593 pdata->phy_interface =
594 phy_get_interface_by_name(phy_mode);
595 if (pdata->phy_interface == -1) {
596 dev_err(dev, "Invalid PHY mode '%s', port %u\n",
597 phy_mode, priv->port_id);
603 ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed);
604 if (pdata->max_speed)
605 dev_err(dev, "Port %u speed froced to %uMbit\n",
606 priv->port_id, pdata->max_speed);
608 priv->has_phy = true;
609 ret = ofnode_parse_phandle_with_args(port_np, "phy-handle",
610 NULL, 0, 0, &out_args);
612 dev_err(dev, "can't parse phy-handle port %u (%d)\n",
614 priv->has_phy = false;
618 priv->phy_node = out_args.node;
620 ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
622 dev_err(dev, "failed to get phy_addr port %u (%d)\n",
632 static int am65_cpsw_probe_cpsw(struct udevice *dev)
634 struct am65_cpsw_priv *priv = dev_get_priv(dev);
635 struct eth_pdata *pdata = dev_get_platdata(dev);
636 struct am65_cpsw_common *cpsw_common;
637 ofnode ports_np, node;
642 cpsw_common = calloc(1, sizeof(*priv->cpsw_common));
645 priv->cpsw_common = cpsw_common;
647 cpsw_common->dev = dev;
648 cpsw_common->ss_base = dev_read_addr(dev);
649 if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
651 cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse");
652 /* no err check - optional */
654 ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
656 dev_err(dev, "failed to get pwrdmn: %d\n", ret);
660 ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
662 power_domain_free(&cpsw_common->pwrdmn);
663 dev_err(dev, "failed to get clock %d\n", ret);
667 cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
668 cpsw_common->ale_base = cpsw_common->cpsw_base +
669 AM65_CPSW_CPSW_NU_ALE_BASE;
670 cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
672 cpsw_common->rflow_id_base = 0;
673 cpsw_common->rflow_id_base =
674 dev_read_u32_default(dev, "ti,rx-flow-id-base",
675 cpsw_common->rflow_id_base);
677 ports_np = dev_read_subnode(dev, "ports");
678 if (!ofnode_valid(ports_np)) {
683 ofnode_for_each_subnode(node, ports_np) {
684 const char *node_name;
688 node_name = ofnode_get_name(node);
690 disabled = !ofnode_is_available(node);
692 ret = ofnode_read_u32(node, "reg", &port_id);
694 dev_err(dev, "%s: failed to get port_id (%d)\n",
699 if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
700 dev_err(dev, "%s: invalid port_id (%d)\n",
705 cpsw_common->port_num++;
710 priv->port_id = port_id;
711 cpsw_common->ports[port_id].disabled = disabled;
715 ret = am65_cpsw_ofdata_parse_phy(dev, node);
720 for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
721 struct am65_cpsw_port *port = &cpsw_common->ports[i];
723 port->port_base = cpsw_common->cpsw_base +
724 AM65_CPSW_CPSW_NU_PORTS_OFFSET +
725 (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
726 port->macsl_base = port->port_base +
727 AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
730 node = dev_read_subnode(dev, "cpsw-phy-sel");
731 if (!ofnode_valid(node)) {
732 dev_err(dev, "can't find cpsw-phy-sel\n");
737 cpsw_common->gmii_sel = ofnode_get_addr(node);
738 if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) {
739 dev_err(dev, "failed to get gmii_sel base\n");
743 node = dev_read_subnode(dev, "mdio");
744 if (!ofnode_valid(node)) {
745 dev_err(dev, "can't find mdio\n");
750 cpsw_common->bus_freq =
751 dev_read_u32_default(dev, "bus_freq",
752 AM65_CPSW_MDIO_BUS_FREQ_DEF);
754 am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);
756 ret = am65_cpsw_mdio_init(dev);
760 ret = am65_cpsw_phy_init(dev);
764 dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u rflow_id_base:%u mdio_freq:%u\n",
765 readl(cpsw_common->ss_base),
766 readl(cpsw_common->cpsw_base),
767 readl(cpsw_common->ale_base),
768 cpsw_common->port_num,
769 cpsw_common->rflow_id_base,
770 cpsw_common->bus_freq);
773 clk_free(&cpsw_common->fclk);
774 power_domain_free(&cpsw_common->pwrdmn);
778 static const struct udevice_id am65_cpsw_nuss_ids[] = {
779 { .compatible = "ti,am654-cpsw-nuss" },
783 U_BOOT_DRIVER(am65_cpsw_nuss_slave) = {
784 .name = "am65_cpsw_nuss_slave",
786 .of_match = am65_cpsw_nuss_ids,
787 .probe = am65_cpsw_probe_cpsw,
788 .ops = &am65_cpsw_ops,
789 .priv_auto_alloc_size = sizeof(struct am65_cpsw_priv),
790 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
791 .flags = DM_FLAG_ALLOC_PRIV_DMA,