drivers/net/ti/am65-cpsw-nuss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver
   4  *
   5  * Copyright (C) 2019, Texas Instruments, Incorporated
   6  *
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #include <clk.h>
  13 #include <dm.h>
  14 #include <dm/lists.h>
  15 #include <dma-uclass.h>
  16 #include <dm/of_access.h>
  17 #include <miiphy.h>
  18 #include <net.h>
  19 #include <phy.h>
  20 #include <power-domain.h>
  21 #include <linux/soc/ti/ti-udma.h>
  22
  23 #include "cpsw_mdio.h"
  24
  25 #define AM65_CPSW_CPSWNU_MAX_PORTS 2
  26
  27 #define AM65_CPSW_SS_BASE               0x0
  28 #define AM65_CPSW_SGMII_BASE    0x100
  29 #define AM65_CPSW_MDIO_BASE     0xf00
  30 #define AM65_CPSW_XGMII_BASE    0x2100
  31 #define AM65_CPSW_CPSW_NU_BASE  0x20000
  32 #define AM65_CPSW_CPSW_NU_ALE_BASE 0x1e000
  33
  34 #define AM65_CPSW_CPSW_NU_PORTS_OFFSET  0x1000
  35 #define AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET     0x330
  36
  37 #define AM65_CPSW_MDIO_BUS_FREQ_DEF 1000000
  38
  39 #define AM65_CPSW_CTL_REG                       0x4
  40 #define AM65_CPSW_STAT_PORT_EN_REG      0x14
  41 #define AM65_CPSW_PTYPE_REG             0x18
  42
  43 #define AM65_CPSW_CTL_REG_P0_ENABLE                     BIT(2)
  44 #define AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE              BIT(13)
  45 #define AM65_CPSW_CTL_REG_P0_RX_PAD                     BIT(14)
  46
  47 #define AM65_CPSW_P0_FLOW_ID_REG                        0x8
  48 #define AM65_CPSW_PN_RX_MAXLEN_REG              0x24
  49 #define AM65_CPSW_PN_REG_SA_L                   0x308
  50 #define AM65_CPSW_PN_REG_SA_H                   0x30c
  51
  52 #define AM65_CPSW_ALE_CTL_REG                   0x8
  53 #define AM65_CPSW_ALE_CTL_REG_ENABLE            BIT(31)
  54 #define AM65_CPSW_ALE_CTL_REG_RESET_TBL         BIT(30)
  55 #define AM65_CPSW_ALE_CTL_REG_BYPASS            BIT(4)
  56 #define AM65_CPSW_ALE_PN_CTL_REG(x)             (0x40 + (x) * 4)
  57 #define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD   0x3
  58 #define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY       BIT(11)
  59
  60 #define AM65_CPSW_MACSL_CTL_REG                 0x0
  61 #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A         BIT(15)
  62 #define AM65_CPSW_MACSL_CTL_REG_GIG             BIT(7)
  63 #define AM65_CPSW_MACSL_CTL_REG_GMII_EN         BIT(5)
  64 #define AM65_CPSW_MACSL_CTL_REG_LOOPBACK        BIT(1)
  65 #define AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX     BIT(0)
  66 #define AM65_CPSW_MACSL_RESET_REG               0x8
  67 #define AM65_CPSW_MACSL_RESET_REG_RESET         BIT(0)
  68 #define AM65_CPSW_MACSL_STATUS_REG              0x4
  69 #define AM65_CPSW_MACSL_RESET_REG_PN_IDLE       BIT(31)
  70 #define AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE     BIT(30)
  71 #define AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE     BIT(29)
  72 #define AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE    BIT(28)
  73 #define AM65_CPSW_MACSL_RESET_REG_IDLE_MASK \
  74         (AM65_CPSW_MACSL_RESET_REG_PN_IDLE | \
  75          AM65_CPSW_MACSL_RESET_REG_PN_E_IDLE | \
  76          AM65_CPSW_MACSL_RESET_REG_PN_P_IDLE | \
  77          AM65_CPSW_MACSL_RESET_REG_PN_TX_IDLE)
  78
  79 #define AM65_CPSW_CPPI_PKT_TYPE                 0x7
  80
  81 struct am65_cpsw_port {
  82         fdt_addr_t      port_base;
  83         fdt_addr_t      macsl_base;
  84         bool            disabled;
  85         u32             mac_control;
  86 };
  87
  88 struct am65_cpsw_common {
  89         struct udevice          *dev;
  90         fdt_addr_t              ss_base;
  91         fdt_addr_t              cpsw_base;
  92         fdt_addr_t              mdio_base;
  93         fdt_addr_t              ale_base;
  94         fdt_addr_t              gmii_sel;
  95         fdt_addr_t              mac_efuse;
  96
  97         struct clk              fclk;
  98         struct power_domain     pwrdmn;
  99
 100         u32                     port_num;
 101         struct am65_cpsw_port   ports[AM65_CPSW_CPSWNU_MAX_PORTS];
 102         u32                     rflow_id_base;
 103
 104         struct mii_dev          *bus;
 105         u32                     bus_freq;
 106
 107         struct dma              dma_tx;
 108         struct dma              dma_rx;
 109         u32                     rx_next;
 110         u32                     rx_pend;
 111         bool                    started;
 112 };
 113
 114 struct am65_cpsw_priv {
 115         struct udevice          *dev;
 116         struct am65_cpsw_common *cpsw_common;
 117         u32                     port_id;
 118
 119         struct phy_device       *phydev;
 120         bool                    has_phy;
 121         ofnode                  phy_node;
 122         u32                     phy_addr;
 123 };
 124
 125 #ifdef PKTSIZE_ALIGN
 126 #define UDMA_RX_BUF_SIZE PKTSIZE_ALIGN
 127 #else
 128 #define UDMA_RX_BUF_SIZE ALIGN(1522, ARCH_DMA_MINALIGN)
 129 #endif
 130
 131 #ifdef PKTBUFSRX
 132 #define UDMA_RX_DESC_NUM PKTBUFSRX
 133 #else
 134 #define UDMA_RX_DESC_NUM 4
 135 #endif
 136
 137 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 138                          ((mac)[2] << 16) | ((mac)[3] << 24))
 139 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 140
 141 static void am65_cpsw_set_sl_mac(struct am65_cpsw_port *slave,
 142                                  unsigned char *addr)
 143 {
 144         writel(mac_hi(addr),
 145                slave->port_base + AM65_CPSW_PN_REG_SA_H);
 146         writel(mac_lo(addr),
 147                slave->port_base + AM65_CPSW_PN_REG_SA_L);
 148 }
 149
 150 int am65_cpsw_macsl_reset(struct am65_cpsw_port *slave)
 151 {
 152         u32 i = 100;
 153
 154         /* Set the soft reset bit */
 155         writel(AM65_CPSW_MACSL_RESET_REG_RESET,
 156                slave->macsl_base + AM65_CPSW_MACSL_RESET_REG);
 157
 158         while ((readl(slave->macsl_base + AM65_CPSW_MACSL_RESET_REG) &
 159                 AM65_CPSW_MACSL_RESET_REG_RESET) && i--)
 160                 cpu_relax();
 161
 162         /* Timeout on the reset */
 163         return i;
 164 }
 165
 166 static int am65_cpsw_macsl_wait_for_idle(struct am65_cpsw_port *slave)
 167 {
 168         u32 i = 100;
 169
 170         while ((readl(slave->macsl_base + AM65_CPSW_MACSL_STATUS_REG) &
 171                 AM65_CPSW_MACSL_RESET_REG_IDLE_MASK) && i--)
 172                 cpu_relax();
 173
 174         return i;
 175 }
 176
 177 static int am65_cpsw_update_link(struct am65_cpsw_priv *priv)
 178 {
 179         struct am65_cpsw_common *common = priv->cpsw_common;
 180         struct am65_cpsw_port *port = &common->ports[priv->port_id];
 181         struct phy_device *phy = priv->phydev;
 182         u32 mac_control = 0;
 183
 184         if (phy->link) { /* link up */
 185                 mac_control = /*AM65_CPSW_MACSL_CTL_REG_LOOPBACK |*/
 186                               AM65_CPSW_MACSL_CTL_REG_GMII_EN;
 187                 if (phy->speed == 1000)
 188                         mac_control |= AM65_CPSW_MACSL_CTL_REG_GIG;
 189                 if (phy->duplex == DUPLEX_FULL)
 190                         mac_control |= AM65_CPSW_MACSL_CTL_REG_FULL_DUPLEX;
 191                 if (phy->speed == 100)
 192                         mac_control |= AM65_CPSW_MACSL_CTL_REG_IFCTL_A;
 193         }
 194
 195         if (mac_control == port->mac_control)
 196                 goto out;
 197
 198         if (mac_control) {
 199                 printf("link up on port %d, speed %d, %s duplex\n",
 200                        priv->port_id, phy->speed,
 201                        (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 202         } else {
 203                 printf("link down on port %d\n", priv->port_id);
 204         }
 205
 206         writel(mac_control, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
 207         port->mac_control = mac_control;
 208
 209 out:
 210         return phy->link;
 211 }
 212
 213 #define AM65_GMII_SEL_MODE_MII          0
 214 #define AM65_GMII_SEL_MODE_RMII         1
 215 #define AM65_GMII_SEL_MODE_RGMII        2
 216
 217 #define AM65_GMII_SEL_RGMII_IDMODE      BIT(4)
 218
 219 static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
 220                                   phy_interface_t phy_mode, int slave)
 221 {
 222         struct am65_cpsw_common *common = priv->cpsw_common;
 223         u32 reg;
 224         u32 mode = 0;
 225         bool rgmii_id = false;
 226
 227         reg = readl(common->gmii_sel);
 228
 229         dev_dbg(common->dev, "old gmii_sel: %08x\n", reg);
 230
 231         switch (phy_mode) {
 232         case PHY_INTERFACE_MODE_RMII:
 233                 mode = AM65_GMII_SEL_MODE_RMII;
 234                 break;
 235
 236         case PHY_INTERFACE_MODE_RGMII:
 237                 mode = AM65_GMII_SEL_MODE_RGMII;
 238                 break;
 239
 240         case PHY_INTERFACE_MODE_RGMII_ID:
 241         case PHY_INTERFACE_MODE_RGMII_RXID:
 242         case PHY_INTERFACE_MODE_RGMII_TXID:
 243                 mode = AM65_GMII_SEL_MODE_RGMII;
 244                 rgmii_id = true;
 245                 break;
 246
 247         default:
 248                 dev_warn(common->dev,
 249                          "Unsupported PHY mode: %u. Defaulting to MII.\n",
 250                          phy_mode);
 251                 /* fallthrough */
 252         case PHY_INTERFACE_MODE_MII:
 253                 mode = AM65_GMII_SEL_MODE_MII;
 254                 break;
 255         };
 256
 257         if (rgmii_id)
 258                 mode |= AM65_GMII_SEL_RGMII_IDMODE;
 259
 260         reg = mode;
 261         dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
 262                 phy_mode, reg);
 263         writel(reg, common->gmii_sel);
 264
 265         reg = readl(common->gmii_sel);
 266         if (reg != mode)
 267                 dev_err(common->dev,
 268                         "gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",
 269                         mode, reg);
 270 }
 271
 272 static int am65_cpsw_start(struct udevice *dev)
 273 {
 274         struct eth_pdata *pdata = dev_get_platdata(dev);
 275         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 276         struct am65_cpsw_common *common = priv->cpsw_common;
 277         struct am65_cpsw_port *port = &common->ports[priv->port_id];
 278         struct am65_cpsw_port *port0 = &common->ports[0];
 279         int ret, i;
 280
 281         ret = power_domain_on(&common->pwrdmn);
 282         if (ret) {
 283                 dev_err(dev, "power_domain_on() failed %d\n", ret);
 284                 goto out;
 285         }
 286
 287         ret = clk_enable(&common->fclk);
 288         if (ret) {
 289                 dev_err(dev, "clk enabled failed %d\n", ret);
 290                 goto err_off_pwrdm;
 291         }
 292
 293         common->rx_next = 0;
 294         common->rx_pend = 0;
 295         ret = dma_get_by_name(common->dev, "tx0", &common->dma_tx);
 296         if (ret) {
 297                 dev_err(dev, "TX dma get failed %d\n", ret);
 298                 goto err_off_clk;
 299         }
 300         ret = dma_get_by_name(common->dev, "rx", &common->dma_rx);
 301         if (ret) {
 302                 dev_err(dev, "RX dma get failed %d\n", ret);
 303                 goto err_free_tx;
 304         }
 305
 306         for (i = 0; i < UDMA_RX_DESC_NUM; i++) {
 307                 ret = dma_prepare_rcv_buf(&common->dma_rx,
 308                                           net_rx_packets[i],
 309                                           UDMA_RX_BUF_SIZE);
 310                 if (ret) {
 311                         dev_err(dev, "RX dma add buf failed %d\n", ret);
 312                         goto err_free_tx;
 313                 }
 314         }
 315
 316         ret = dma_enable(&common->dma_tx);
 317         if (ret) {
 318                 dev_err(dev, "TX dma_enable failed %d\n", ret);
 319                 goto err_free_rx;
 320         }
 321         ret = dma_enable(&common->dma_rx);
 322         if (ret) {
 323                 dev_err(dev, "RX dma_enable failed %d\n", ret);
 324                 goto err_dis_tx;
 325         }
 326
 327         /* Control register */
 328         writel(AM65_CPSW_CTL_REG_P0_ENABLE |
 329                AM65_CPSW_CTL_REG_P0_TX_CRC_REMOVE |
 330                AM65_CPSW_CTL_REG_P0_RX_PAD,
 331                common->cpsw_base + AM65_CPSW_CTL_REG);
 332
 333         /* disable priority elevation */
 334         writel(0, common->cpsw_base + AM65_CPSW_PTYPE_REG);
 335
 336         /* enable statistics */
 337         writel(BIT(0) | BIT(priv->port_id),
 338                common->cpsw_base + AM65_CPSW_STAT_PORT_EN_REG);
 339
 340         /* Port 0  length register */
 341         writel(PKTSIZE_ALIGN, port0->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
 342
 343         /* set base flow_id */
 344         writel(common->rflow_id_base,
 345                port0->port_base + AM65_CPSW_P0_FLOW_ID_REG);
 346
 347         /* Reset and enable the ALE */
 348         writel(AM65_CPSW_ALE_CTL_REG_ENABLE | AM65_CPSW_ALE_CTL_REG_RESET_TBL |
 349                AM65_CPSW_ALE_CTL_REG_BYPASS,
 350                common->ale_base + AM65_CPSW_ALE_CTL_REG);
 351
 352         /* port 0 put into forward mode */
 353         writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
 354                common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
 355
 356         /* PORT x configuration */
 357
 358         /* Port x Max length register */
 359         writel(PKTSIZE_ALIGN, port->port_base + AM65_CPSW_PN_RX_MAXLEN_REG);
 360
 361         /* Port x set mac */
 362         am65_cpsw_set_sl_mac(port, pdata->enetaddr);
 363
 364         /* Port x ALE: mac_only, Forwarding */
 365         writel(AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY |
 366                AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD,
 367                common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
 368
 369         port->mac_control = 0;
 370         if (!am65_cpsw_macsl_reset(port)) {
 371                 dev_err(dev, "mac_sl reset failed\n");
 372                 ret = -EFAULT;
 373                 goto err_dis_rx;
 374         }
 375
 376         ret = phy_startup(priv->phydev);
 377         if (ret) {
 378                 dev_err(dev, "phy_startup failed\n");
 379                 goto err_dis_rx;
 380         }
 381
 382         ret = am65_cpsw_update_link(priv);
 383         if (!ret) {
 384                 ret = -ENODEV;
 385                 goto err_phy_shutdown;
 386         }
 387
 388         common->started = true;
 389
 390         return 0;
 391
 392 err_phy_shutdown:
 393         phy_shutdown(priv->phydev);
 394 err_dis_rx:
 395         /* disable ports */
 396         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
 397         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
 398         if (!am65_cpsw_macsl_wait_for_idle(port))
 399                 dev_err(dev, "mac_sl idle timeout\n");
 400         writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
 401         writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
 402         writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
 403
 404         dma_disable(&common->dma_rx);
 405 err_dis_tx:
 406         dma_disable(&common->dma_tx);
 407 err_free_rx:
 408         dma_free(&common->dma_rx);
 409 err_free_tx:
 410         dma_free(&common->dma_tx);
 411 err_off_clk:
 412         clk_disable(&common->fclk);
 413 err_off_pwrdm:
 414         power_domain_off(&common->pwrdmn);
 415 out:
 416         dev_err(dev, "%s end error\n", __func__);
 417
 418         return ret;
 419 }
 420
 421 static int am65_cpsw_send(struct udevice *dev, void *packet, int length)
 422 {
 423         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 424         struct am65_cpsw_common *common = priv->cpsw_common;
 425         struct ti_udma_drv_packet_data packet_data;
 426         int ret;
 427
 428         packet_data.pkt_type = AM65_CPSW_CPPI_PKT_TYPE;
 429         packet_data.dest_tag = priv->port_id;
 430         ret = dma_send(&common->dma_tx, packet, length, &packet_data);
 431         if (ret) {
 432                 dev_err(dev, "TX dma_send failed %d\n", ret);
 433                 return ret;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static int am65_cpsw_recv(struct udevice *dev, int flags, uchar **packetp)
 440 {
 441         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 442         struct am65_cpsw_common *common = priv->cpsw_common;
 443
 444         /* try to receive a new packet */
 445         return dma_receive(&common->dma_rx, (void **)packetp, NULL);
 446 }
 447
 448 static int am65_cpsw_free_pkt(struct udevice *dev, uchar *packet, int length)
 449 {
 450         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 451         struct am65_cpsw_common *common = priv->cpsw_common;
 452         int ret;
 453
 454         if (length > 0) {
 455                 u32 pkt = common->rx_next % UDMA_RX_DESC_NUM;
 456
 457                 ret = dma_prepare_rcv_buf(&common->dma_rx,
 458                                           net_rx_packets[pkt],
 459                                           UDMA_RX_BUF_SIZE);
 460                 if (ret)
 461                         dev_err(dev, "RX dma free_pkt failed %d\n", ret);
 462                 common->rx_next++;
 463         }
 464
 465         return 0;
 466 }
 467
 468 static void am65_cpsw_stop(struct udevice *dev)
 469 {
 470         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 471         struct am65_cpsw_common *common = priv->cpsw_common;
 472         struct am65_cpsw_port *port = &common->ports[priv->port_id];
 473
 474         if (!common->started)
 475                 return;
 476
 477         phy_shutdown(priv->phydev);
 478
 479         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(priv->port_id));
 480         writel(0, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0));
 481         if (!am65_cpsw_macsl_wait_for_idle(port))
 482                 dev_err(dev, "mac_sl idle timeout\n");
 483         writel(0, port->macsl_base + AM65_CPSW_MACSL_CTL_REG);
 484         writel(0, common->ale_base + AM65_CPSW_ALE_CTL_REG);
 485         writel(0, common->cpsw_base + AM65_CPSW_CTL_REG);
 486
 487         dma_disable(&common->dma_tx);
 488         dma_free(&common->dma_tx);
 489
 490         dma_disable(&common->dma_rx);
 491         dma_free(&common->dma_rx);
 492
 493         common->started = false;
 494 }
 495
 496 static int am65_cpsw_read_rom_hwaddr(struct udevice *dev)
 497 {
 498         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 499         struct am65_cpsw_common *common = priv->cpsw_common;
 500         struct eth_pdata *pdata = dev_get_platdata(dev);
 501         u32 mac_hi, mac_lo;
 502
 503         if (common->mac_efuse == FDT_ADDR_T_NONE)
 504                 return -1;
 505
 506         mac_lo = readl(common->mac_efuse);
 507         mac_hi = readl(common->mac_efuse + 4);
 508         pdata->enetaddr[0] = (mac_hi >> 8) & 0xff;
 509         pdata->enetaddr[1] = mac_hi & 0xff;
 510         pdata->enetaddr[2] = (mac_lo >> 24) & 0xff;
 511         pdata->enetaddr[3] = (mac_lo >> 16) & 0xff;
 512         pdata->enetaddr[4] = (mac_lo >> 8) & 0xff;
 513         pdata->enetaddr[5] = mac_lo & 0xff;
 514
 515         return 0;
 516 }
 517
 518 static const struct eth_ops am65_cpsw_ops = {
 519         .start          = am65_cpsw_start,
 520         .send           = am65_cpsw_send,
 521         .recv           = am65_cpsw_recv,
 522         .free_pkt       = am65_cpsw_free_pkt,
 523         .stop           = am65_cpsw_stop,
 524         .read_rom_hwaddr = am65_cpsw_read_rom_hwaddr,
 525 };
 526
 527 static int am65_cpsw_mdio_init(struct udevice *dev)
 528 {
 529         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 530         struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
 531
 532         if (!priv->has_phy || cpsw_common->bus)
 533                 return 0;
 534
 535         cpsw_common->bus = cpsw_mdio_init(dev->name,
 536                                           cpsw_common->mdio_base,
 537                                           cpsw_common->bus_freq,
 538                                           clk_get_rate(&cpsw_common->fclk));
 539         if (!cpsw_common->bus)
 540                 return -EFAULT;
 541
 542         return 0;
 543 }
 544
 545 static int am65_cpsw_phy_init(struct udevice *dev)
 546 {
 547         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 548         struct am65_cpsw_common *cpsw_common = priv->cpsw_common;
 549         struct eth_pdata *pdata = dev_get_platdata(dev);
 550         struct phy_device *phydev;
 551         u32 supported = PHY_GBIT_FEATURES;
 552         int ret;
 553
 554         phydev = phy_connect(cpsw_common->bus,
 555                              priv->phy_addr,
 556                              priv->dev,
 557                              pdata->phy_interface);
 558
 559         if (!phydev) {
 560                 dev_err(dev, "phy_connect() failed\n");
 561                 return -ENODEV;
 562         }
 563
 564         phydev->supported &= supported;
 565         if (pdata->max_speed) {
 566                 ret = phy_set_supported(phydev, pdata->max_speed);
 567                 if (ret)
 568                         return ret;
 569         }
 570         phydev->advertising = phydev->supported;
 571
 572         if (ofnode_valid(priv->phy_node))
 573                 phydev->node = priv->phy_node;
 574
 575         priv->phydev = phydev;
 576         ret = phy_config(phydev);
 577         if (ret < 0)
 578                 pr_err("phy_config() failed: %d", ret);
 579
 580         return ret;
 581 }
 582
 583 static int am65_cpsw_ofdata_parse_phy(struct udevice *dev, ofnode port_np)
 584 {
 585         struct eth_pdata *pdata = dev_get_platdata(dev);
 586         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 587         struct ofnode_phandle_args out_args;
 588         const char *phy_mode;
 589         int ret = 0;
 590
 591         phy_mode = ofnode_read_string(port_np, "phy-mode");
 592         if (phy_mode) {
 593                 pdata->phy_interface =
 594                                 phy_get_interface_by_name(phy_mode);
 595                 if (pdata->phy_interface == -1) {
 596                         dev_err(dev, "Invalid PHY mode '%s', port %u\n",
 597                                 phy_mode, priv->port_id);
 598                         ret = -EINVAL;
 599                         goto out;
 600                 }
 601         }
 602
 603         ofnode_read_u32(port_np, "max-speed", (u32 *)&pdata->max_speed);
 604         if (pdata->max_speed)
 605                 dev_err(dev, "Port %u speed froced to %uMbit\n",
 606                         priv->port_id, pdata->max_speed);
 607
 608         priv->has_phy  = true;
 609         ret = ofnode_parse_phandle_with_args(port_np, "phy-handle",
 610                                              NULL, 0, 0, &out_args);
 611         if (ret) {
 612                 dev_err(dev, "can't parse phy-handle port %u (%d)\n",
 613                         priv->port_id, ret);
 614                 priv->has_phy  = false;
 615                 ret = 0;
 616         }
 617
 618         priv->phy_node = out_args.node;
 619         if (priv->has_phy) {
 620                 ret = ofnode_read_u32(priv->phy_node, "reg", &priv->phy_addr);
 621                 if (ret) {
 622                         dev_err(dev, "failed to get phy_addr port %u (%d)\n",
 623                                 priv->port_id, ret);
 624                         goto out;
 625                 }
 626         }
 627
 628 out:
 629         return ret;
 630 }
 631
 632 static int am65_cpsw_probe_cpsw(struct udevice *dev)
 633 {
 634         struct am65_cpsw_priv *priv = dev_get_priv(dev);
 635         struct eth_pdata *pdata = dev_get_platdata(dev);
 636         struct am65_cpsw_common *cpsw_common;
 637         ofnode ports_np, node;
 638         int ret, i;
 639
 640         priv->dev = dev;
 641
 642         cpsw_common = calloc(1, sizeof(*priv->cpsw_common));
 643         if (!cpsw_common)
 644                 return -ENOMEM;
 645         priv->cpsw_common = cpsw_common;
 646
 647         cpsw_common->dev = dev;
 648         cpsw_common->ss_base = dev_read_addr(dev);
 649         if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
 650                 return -EINVAL;
 651         cpsw_common->mac_efuse = devfdt_get_addr_name(dev, "mac_efuse");
 652         /* no err check - optional */
 653
 654         ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
 655         if (ret) {
 656                 dev_err(dev, "failed to get pwrdmn: %d\n", ret);
 657                 return ret;
 658         }
 659
 660         ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
 661         if (ret) {
 662                 power_domain_free(&cpsw_common->pwrdmn);
 663                 dev_err(dev, "failed to get clock %d\n", ret);
 664                 return ret;
 665         }
 666
 667         cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
 668         cpsw_common->ale_base = cpsw_common->cpsw_base +
 669                                 AM65_CPSW_CPSW_NU_ALE_BASE;
 670         cpsw_common->mdio_base = cpsw_common->ss_base + AM65_CPSW_MDIO_BASE;
 671
 672         cpsw_common->rflow_id_base = 0;
 673         cpsw_common->rflow_id_base =
 674                         dev_read_u32_default(dev, "ti,rx-flow-id-base",
 675                                              cpsw_common->rflow_id_base);
 676
 677         ports_np = dev_read_subnode(dev, "ports");
 678         if (!ofnode_valid(ports_np)) {
 679                 ret = -ENOENT;
 680                 goto out;
 681         }
 682
 683         ofnode_for_each_subnode(node, ports_np) {
 684                 const char *node_name;
 685                 u32 port_id;
 686                 bool disabled;
 687
 688                 node_name = ofnode_get_name(node);
 689
 690                 disabled = !ofnode_is_available(node);
 691
 692                 ret = ofnode_read_u32(node, "reg", &port_id);
 693                 if (ret) {
 694                         dev_err(dev, "%s: failed to get port_id (%d)\n",
 695                                 node_name, ret);
 696                         goto out;
 697                 }
 698
 699                 if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
 700                         dev_err(dev, "%s: invalid port_id (%d)\n",
 701                                 node_name, port_id);
 702                         ret = -EINVAL;
 703                         goto out;
 704                 }
 705                 cpsw_common->port_num++;
 706
 707                 if (!port_id)
 708                         continue;
 709
 710                 priv->port_id = port_id;
 711                 cpsw_common->ports[port_id].disabled = disabled;
 712                 if (disabled)
 713                         continue;
 714
 715                 ret = am65_cpsw_ofdata_parse_phy(dev, node);
 716                 if (ret)
 717                         goto out;
 718         }
 719
 720         for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
 721                 struct am65_cpsw_port *port = &cpsw_common->ports[i];
 722
 723                 port->port_base = cpsw_common->cpsw_base +
 724                                   AM65_CPSW_CPSW_NU_PORTS_OFFSET +
 725                                   (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
 726                 port->macsl_base = port->port_base +
 727                                    AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
 728         }
 729
 730         node = dev_read_subnode(dev, "cpsw-phy-sel");
 731         if (!ofnode_valid(node)) {
 732                 dev_err(dev, "can't find cpsw-phy-sel\n");
 733                 ret = -ENOENT;
 734                 goto out;
 735         }
 736
 737         cpsw_common->gmii_sel = ofnode_get_addr(node);
 738         if (cpsw_common->gmii_sel == FDT_ADDR_T_NONE) {
 739                 dev_err(dev, "failed to get gmii_sel base\n");
 740                 goto out;
 741         }
 742
 743         node = dev_read_subnode(dev, "mdio");
 744         if (!ofnode_valid(node)) {
 745                 dev_err(dev, "can't find mdio\n");
 746                 ret = -ENOENT;
 747                 goto out;
 748         }
 749
 750         cpsw_common->bus_freq =
 751                         dev_read_u32_default(dev, "bus_freq",
 752                                              AM65_CPSW_MDIO_BUS_FREQ_DEF);
 753
 754         am65_cpsw_gmii_sel_k3(priv, pdata->phy_interface, priv->port_id);
 755
 756         ret = am65_cpsw_mdio_init(dev);
 757         if (ret)
 758                 goto out;
 759
 760         ret = am65_cpsw_phy_init(dev);
 761         if (ret)
 762                 goto out;
 763
 764         dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u rflow_id_base:%u mdio_freq:%u\n",
 765                  readl(cpsw_common->ss_base),
 766                  readl(cpsw_common->cpsw_base),
 767                  readl(cpsw_common->ale_base),
 768                  cpsw_common->port_num,
 769                  cpsw_common->rflow_id_base,
 770                  cpsw_common->bus_freq);
 771
 772 out:
 773         clk_free(&cpsw_common->fclk);
 774         power_domain_free(&cpsw_common->pwrdmn);
 775         return ret;
 776 }
 777
 778 static const struct udevice_id am65_cpsw_nuss_ids[] = {
 779         { .compatible = "ti,am654-cpsw-nuss" },
 780         { }
 781 };
 782
 783 U_BOOT_DRIVER(am65_cpsw_nuss_slave) = {
 784         .name   = "am65_cpsw_nuss_slave",
 785         .id     = UCLASS_ETH,
 786         .of_match = am65_cpsw_nuss_ids,
 787         .probe  = am65_cpsw_probe_cpsw,
 788         .ops    = &am65_cpsw_ops,
 789         .priv_auto_alloc_size = sizeof(struct am65_cpsw_priv),
 790         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 791         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 792 };