1 // SPDX-License-Identifier: GPL-2.0+
3 * sunxi_emac.c -- Allwinner A10 ethernet driver
5 * (C) Copyright 2012, Stefan Roese <sr@denx.de>
11 #include <dm/device_compat.h>
12 #include <linux/err.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/gpio.h>
23 u32 tx_mode; /* 0x04 */
24 u32 tx_flow; /* 0x08 */
25 u32 tx_ctl0; /* 0x0c */
26 u32 tx_ctl1; /* 0x10 */
27 u32 tx_ins; /* 0x14 */
28 u32 tx_pl0; /* 0x18 */
29 u32 tx_pl1; /* 0x1c */
30 u32 tx_sta; /* 0x20 */
31 u32 tx_io_data; /* 0x24 */
32 u32 tx_io_data1;/* 0x28 */
33 u32 tx_tsvl0; /* 0x2c */
34 u32 tx_tsvh0; /* 0x30 */
35 u32 tx_tsvl1; /* 0x34 */
36 u32 tx_tsvh1; /* 0x38 */
37 u32 rx_ctl; /* 0x3c */
38 u32 rx_hash0; /* 0x40 */
39 u32 rx_hash1; /* 0x44 */
40 u32 rx_sta; /* 0x48 */
41 u32 rx_io_data; /* 0x4c */
42 u32 rx_fbc; /* 0x50 */
43 u32 int_ctl; /* 0x54 */
44 u32 int_sta; /* 0x58 */
45 u32 mac_ctl0; /* 0x5c */
46 u32 mac_ctl1; /* 0x60 */
47 u32 mac_ipgt; /* 0x64 */
48 u32 mac_ipgr; /* 0x68 */
49 u32 mac_clrt; /* 0x6c */
50 u32 mac_maxf; /* 0x70 */
51 u32 mac_supp; /* 0x74 */
52 u32 mac_test; /* 0x78 */
53 u32 mac_mcfg; /* 0x7c */
54 u32 mac_mcmd; /* 0x80 */
55 u32 mac_madr; /* 0x84 */
56 u32 mac_mwtd; /* 0x88 */
57 u32 mac_mrdd; /* 0x8c */
58 u32 mac_mind; /* 0x90 */
59 u32 mac_ssrr; /* 0x94 */
60 u32 mac_a0; /* 0x98 */
61 u32 mac_a1; /* 0x9c */
65 struct sunxi_sramc_regs {
70 /* 0: Disable 1: Aborted frame enable(default) */
71 #define EMAC_TX_AB_M (0x1 << 0)
72 /* 0: CPU 1: DMA(default) */
73 #define EMAC_TX_TM (0x1 << 1)
75 #define EMAC_TX_SETUP (0)
77 /* 0: DRQ asserted 1: DRQ automatically(default) */
78 #define EMAC_RX_DRQ_MODE (0x1 << 1)
79 /* 0: CPU 1: DMA(default) */
80 #define EMAC_RX_TM (0x1 << 2)
81 /* 0: Normal(default) 1: Pass all Frames */
82 #define EMAC_RX_PA (0x1 << 4)
83 /* 0: Normal(default) 1: Pass Control Frames */
84 #define EMAC_RX_PCF (0x1 << 5)
85 /* 0: Normal(default) 1: Pass Frames with CRC Error */
86 #define EMAC_RX_PCRCE (0x1 << 6)
87 /* 0: Normal(default) 1: Pass Frames with Length Error */
88 #define EMAC_RX_PLE (0x1 << 7)
89 /* 0: Normal 1: Pass Frames length out of range(default) */
90 #define EMAC_RX_POR (0x1 << 8)
91 /* 0: Not accept 1: Accept unicast Packets(default) */
92 #define EMAC_RX_UCAD (0x1 << 16)
93 /* 0: Normal(default) 1: DA Filtering */
94 #define EMAC_RX_DAF (0x1 << 17)
95 /* 0: Not accept 1: Accept multicast Packets(default) */
96 #define EMAC_RX_MCO (0x1 << 20)
97 /* 0: Disable(default) 1: Enable Hash filter */
98 #define EMAC_RX_MHF (0x1 << 21)
99 /* 0: Not accept 1: Accept Broadcast Packets(default) */
100 #define EMAC_RX_BCO (0x1 << 22)
101 /* 0: Disable(default) 1: Enable SA Filtering */
102 #define EMAC_RX_SAF (0x1 << 24)
103 /* 0: Normal(default) 1: Inverse Filtering */
104 #define EMAC_RX_SAIF (0x1 << 25)
106 #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
107 EMAC_RX_MCO | EMAC_RX_BCO)
109 /* 0: Disable 1: Enable Receive Flow Control(default) */
110 #define EMAC_MAC_CTL0_RFC (0x1 << 2)
111 /* 0: Disable 1: Enable Transmit Flow Control(default) */
112 #define EMAC_MAC_CTL0_TFC (0x1 << 3)
114 #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
116 /* 0: Disable 1: Enable MAC Frame Length Checking(default) */
117 #define EMAC_MAC_CTL1_FLC (0x1 << 1)
118 /* 0: Disable(default) 1: Enable Huge Frame */
119 #define EMAC_MAC_CTL1_HF (0x1 << 2)
120 /* 0: Disable(default) 1: Enable MAC Delayed CRC */
121 #define EMAC_MAC_CTL1_DCRC (0x1 << 3)
122 /* 0: Disable 1: Enable MAC CRC(default) */
123 #define EMAC_MAC_CTL1_CRC (0x1 << 4)
124 /* 0: Disable 1: Enable MAC PAD Short frames(default) */
125 #define EMAC_MAC_CTL1_PC (0x1 << 5)
126 /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
127 #define EMAC_MAC_CTL1_VC (0x1 << 6)
128 /* 0: Disable(default) 1: Enable MAC auto detect Short frames */
129 #define EMAC_MAC_CTL1_ADP (0x1 << 7)
130 /* 0: Disable(default) 1: Enable */
131 #define EMAC_MAC_CTL1_PRE (0x1 << 8)
132 /* 0: Disable(default) 1: Enable */
133 #define EMAC_MAC_CTL1_LPE (0x1 << 9)
134 /* 0: Disable(default) 1: Enable no back off */
135 #define EMAC_MAC_CTL1_NB (0x1 << 12)
136 /* 0: Disable(default) 1: Enable */
137 #define EMAC_MAC_CTL1_BNB (0x1 << 13)
138 /* 0: Disable(default) 1: Enable */
139 #define EMAC_MAC_CTL1_ED (0x1 << 14)
141 #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
144 #define EMAC_MAC_IPGT 0x15
146 #define EMAC_MAC_NBTB_IPG1 0xc
147 #define EMAC_MAC_NBTB_IPG2 0x12
149 #define EMAC_MAC_CW 0x37
150 #define EMAC_MAC_RM 0xf
152 #define EMAC_MAC_MFL 0x0600
155 #define EMAC_CRCERR (0x1 << 4)
156 #define EMAC_LENERR (0x3 << 5)
158 #define EMAC_RX_BUFSIZE 2000
160 struct emac_eth_dev {
161 struct emac_regs *regs;
164 struct phy_device *phydev;
167 uchar rx_buf[EMAC_RX_BUFSIZE];
176 static void emac_inblk_32bit(void *reg, void *data, int count)
178 int cnt = (count + 3) >> 2;
190 static void emac_outblk_32bit(void *reg, void *data, int count)
192 int cnt = (count + 3) >> 2;
195 const u32 *buf = data;
203 /* Read a word from phyxcer */
204 static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
206 struct emac_eth_dev *priv = bus->priv;
207 struct emac_regs *regs = priv->regs;
209 /* issue the phy address and reg */
210 writel(addr << 8 | reg, ®s->mac_madr);
212 /* pull up the phy io line */
213 writel(0x1, ®s->mac_mcmd);
215 /* Wait read complete */
218 /* push down the phy io line */
219 writel(0x0, ®s->mac_mcmd);
222 return readl(®s->mac_mrdd);
225 /* Write a word to phyxcer */
226 static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
229 struct emac_eth_dev *priv = bus->priv;
230 struct emac_regs *regs = priv->regs;
232 /* issue the phy address and reg */
233 writel(addr << 8 | reg, ®s->mac_madr);
235 /* pull up the phy io line */
236 writel(0x1, ®s->mac_mcmd);
238 /* Wait write complete */
241 /* push down the phy io line */
242 writel(0x0, ®s->mac_mcmd);
245 writel(value, ®s->mac_mwtd);
250 static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
252 int ret, mask = 0xffffffff;
254 #ifdef CONFIG_PHY_ADDR
255 mask = 1 << CONFIG_PHY_ADDR;
258 priv->bus = mdio_alloc();
260 printf("Failed to allocate MDIO bus\n");
264 priv->bus->read = emac_mdio_read;
265 priv->bus->write = emac_mdio_write;
266 priv->bus->priv = priv;
267 strcpy(priv->bus->name, "emac");
269 ret = mdio_register(priv->bus);
273 priv->phydev = phy_find_by_mask(priv->bus, mask,
274 PHY_INTERFACE_MODE_MII);
278 phy_connect_dev(priv->phydev, dev);
279 phy_config(priv->phydev);
284 static void emac_setup(struct emac_eth_dev *priv)
286 struct emac_regs *regs = priv->regs;
290 writel(EMAC_TX_SETUP, ®s->tx_mode);
293 writel(EMAC_RX_SETUP, ®s->rx_ctl);
297 writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
301 if (priv->phydev->duplex == DUPLEX_FULL)
302 reg_val = (0x1 << 0);
303 writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
306 writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
309 writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
311 /* Set up Collison window */
312 writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
314 /* Set up Max Frame Length */
315 writel(EMAC_MAC_MFL, ®s->mac_maxf);
318 static void emac_reset(struct emac_eth_dev *priv)
320 struct emac_regs *regs = priv->regs;
322 debug("resetting device\n");
325 writel(0, ®s->ctl);
328 writel(1, ®s->ctl);
332 static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
334 struct emac_regs *regs = priv->regs;
335 u32 enetaddr_lo, enetaddr_hi;
337 enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
338 enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
340 writel(enetaddr_hi, ®s->mac_a0);
341 writel(enetaddr_lo, ®s->mac_a1);
346 static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
348 struct emac_regs *regs = priv->regs;
354 setbits_le32(®s->rx_ctl, 0x8);
360 clrbits_le32(®s->mac_ctl0, 0x1 << 15);
362 /* Clear RX counter */
363 writel(0x0, ®s->rx_fbc);
369 _sunxi_write_hwaddr(priv, enetaddr);
376 ret = phy_startup(priv->phydev);
378 printf("Could not initialize PHY %s\n",
379 priv->phydev->dev->name);
383 /* Print link status only once */
384 if (!priv->link_printed) {
385 printf("ENET Speed is %d Mbps - %s duplex connection\n",
387 priv->phydev->duplex ? "FULL" : "HALF");
388 priv->link_printed = 1;
391 /* Set EMAC SPEED depend on PHY */
392 if (priv->phydev->speed == SPEED_100)
393 setbits_le32(®s->mac_supp, 1 << 8);
395 clrbits_le32(®s->mac_supp, 1 << 8);
397 /* Set duplex depend on phy */
398 if (priv->phydev->duplex == DUPLEX_FULL)
399 setbits_le32(®s->mac_ctl1, 1 << 0);
401 clrbits_le32(®s->mac_ctl1, 1 << 0);
404 setbits_le32(®s->ctl, 0x7);
409 static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
411 struct emac_regs *regs = priv->regs;
412 struct emac_rxhdr rxhdr;
419 /* Check packet ready or not */
421 /* Race warning: The first packet might arrive with
422 * the interrupts disabled, but the second will fix
424 rxcount = readl(®s->rx_fbc);
427 rxcount = readl(®s->rx_fbc);
432 reg_val = readl(®s->rx_io_data);
433 if (reg_val != 0x0143414d) {
435 clrbits_le32(®s->ctl, 0x1 << 2);
438 setbits_le32(®s->rx_ctl, 0x1 << 3);
439 while (readl(®s->rx_ctl) & (0x1 << 3))
443 setbits_le32(®s->ctl, 0x1 << 2);
448 /* A packet ready now
453 emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
455 rx_len = rxhdr.rx_len;
456 rx_status = rxhdr.rx_status;
458 /* Packet Status check */
461 debug("RX: Bad Packet (runt)\n");
464 /* rx_status is identical to RSR register. */
465 if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
467 if (rx_status & EMAC_CRCERR)
468 printf("crc error\n");
469 if (rx_status & EMAC_LENERR)
470 printf("length error\n");
473 /* Move data from EMAC */
475 if (rx_len > EMAC_RX_BUFSIZE) {
476 printf("Received packet is too big (len=%d)\n", rx_len);
479 emac_inblk_32bit((void *)®s->rx_io_data, packet, rx_len);
483 return -EIO; /* Bad packet */
486 static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
489 struct emac_regs *regs = priv->regs;
491 /* Select channel 0 */
492 writel(0, ®s->tx_ins);
495 emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
498 writel(len, ®s->tx_pl0);
500 /* Start translate from fifo to phy */
501 setbits_le32(®s->tx_ctl0, 1);
506 static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
508 struct sunxi_sramc_regs *sram =
509 (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
510 struct emac_regs *regs = priv->regs;
513 /* Map SRAM to EMAC */
514 setbits_le32(&sram->ctrl1, 0x5 << 2);
516 /* Configure pin mux settings for MII Ethernet */
517 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
518 sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
520 /* Set up clock gating */
521 ret = clk_enable(&priv->clk);
523 dev_err(dev, "failed to enable emac clock\n");
528 clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
533 static int sunxi_emac_eth_start(struct udevice *dev)
535 struct eth_pdata *pdata = dev_get_platdata(dev);
537 return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
540 static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
542 struct emac_eth_dev *priv = dev_get_priv(dev);
544 return _sunxi_emac_eth_send(priv, packet, length);
547 static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
549 struct emac_eth_dev *priv = dev_get_priv(dev);
552 rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
553 *packetp = priv->rx_buf;
558 static void sunxi_emac_eth_stop(struct udevice *dev)
560 /* Nothing to do here */
563 static int sunxi_emac_eth_probe(struct udevice *dev)
565 struct eth_pdata *pdata = dev_get_platdata(dev);
566 struct emac_eth_dev *priv = dev_get_priv(dev);
569 priv->regs = (struct emac_regs *)pdata->iobase;
571 ret = clk_get_by_index(dev, 0, &priv->clk);
573 dev_err(dev, "failed to get emac clock\n");
577 ret = sunxi_emac_board_setup(priv);
581 return sunxi_emac_init_phy(priv, dev);
584 static const struct eth_ops sunxi_emac_eth_ops = {
585 .start = sunxi_emac_eth_start,
586 .send = sunxi_emac_eth_send,
587 .recv = sunxi_emac_eth_recv,
588 .stop = sunxi_emac_eth_stop,
591 static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
593 struct eth_pdata *pdata = dev_get_platdata(dev);
595 pdata->iobase = devfdt_get_addr(dev);
600 static const struct udevice_id sunxi_emac_eth_ids[] = {
601 { .compatible = "allwinner,sun4i-a10-emac" },
605 U_BOOT_DRIVER(eth_sunxi_emac) = {
606 .name = "eth_sunxi_emac",
608 .of_match = sunxi_emac_eth_ids,
609 .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
610 .probe = sunxi_emac_eth_probe,
611 .ops = &sunxi_emac_eth_ops,
612 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
613 .platdata_auto_alloc_size = sizeof(struct eth_pdata),