1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
6 * Ethernet driver for H3/A64/A83T based SoC's
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
14 #include <asm/arch/clock.h>
15 #include <asm/arch/gpio.h>
18 #include <fdt_support.h>
19 #include <linux/err.h>
23 #include <dt-bindings/pinctrl/sun4i-a10.h>
25 #include <asm-generic/gpio.h>
28 #define MDIO_CMD_MII_BUSY BIT(0)
29 #define MDIO_CMD_MII_WRITE BIT(1)
31 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
32 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
33 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
34 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
36 #define CONFIG_TX_DESCR_NUM 32
37 #define CONFIG_RX_DESCR_NUM 32
38 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
41 * The datasheet says that each descriptor can transfers up to 4096 bytes
42 * But later, the register documentation reduces that value to 2048,
43 * using 2048 cause strange behaviours and even BSP driver use 2047
45 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
47 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
48 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
50 #define H3_EPHY_DEFAULT_VALUE 0x58000
51 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
52 #define H3_EPHY_ADDR_SHIFT 20
53 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
54 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
55 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
56 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
58 #define SC_RMII_EN BIT(13)
59 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
60 #define SC_ETCS_MASK GENMASK(1, 0)
61 #define SC_ETCS_EXT_GMII 0x1
62 #define SC_ETCS_INT_GMII 0x2
64 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
66 #define AHB_GATE_OFFSET_EPHY 0
69 #define SUN8I_IOMUX_H3 2
70 #define SUN8I_IOMUX_R40 5
73 /* H3/A64 EMAC Register's offset */
74 #define EMAC_CTL0 0x00
75 #define EMAC_CTL1 0x04
76 #define EMAC_INT_STA 0x08
77 #define EMAC_INT_EN 0x0c
78 #define EMAC_TX_CTL0 0x10
79 #define EMAC_TX_CTL1 0x14
80 #define EMAC_TX_FLOW_CTL 0x1c
81 #define EMAC_TX_DMA_DESC 0x20
82 #define EMAC_RX_CTL0 0x24
83 #define EMAC_RX_CTL1 0x28
84 #define EMAC_RX_DMA_DESC 0x34
85 #define EMAC_MII_CMD 0x48
86 #define EMAC_MII_DATA 0x4c
87 #define EMAC_ADDR0_HIGH 0x50
88 #define EMAC_ADDR0_LOW 0x54
89 #define EMAC_TX_DMA_STA 0xb0
90 #define EMAC_TX_CUR_DESC 0xb4
91 #define EMAC_TX_CUR_BUF 0xb8
92 #define EMAC_RX_DMA_STA 0xc0
93 #define EMAC_RX_CUR_DESC 0xc4
95 DECLARE_GLOBAL_DATA_PTR;
104 struct emac_dma_desc {
109 } __aligned(ARCH_DMA_MINALIGN);
111 struct emac_eth_dev {
112 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
113 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
114 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
115 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
127 bool use_internal_phy;
129 enum emac_variant variant;
131 phys_addr_t sysctl_reg;
132 struct phy_device *phydev;
134 #ifdef CONFIG_DM_GPIO
135 struct gpio_desc reset_gpio;
140 struct sun8i_eth_pdata {
141 struct eth_pdata eth_pdata;
146 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
148 struct udevice *dev = bus->priv;
149 struct emac_eth_dev *priv = dev_get_priv(dev);
152 int timeout = CONFIG_MDIO_TIMEOUT;
154 miiaddr &= ~MDIO_CMD_MII_WRITE;
155 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
156 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
157 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
159 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
161 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
162 MDIO_CMD_MII_PHY_ADDR_MASK;
164 miiaddr |= MDIO_CMD_MII_BUSY;
166 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
168 start = get_timer(0);
169 while (get_timer(start) < timeout) {
170 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
171 return readl(priv->mac_reg + EMAC_MII_DATA);
178 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
181 struct udevice *dev = bus->priv;
182 struct emac_eth_dev *priv = dev_get_priv(dev);
185 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
187 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
188 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
189 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
191 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
192 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
193 MDIO_CMD_MII_PHY_ADDR_MASK;
195 miiaddr |= MDIO_CMD_MII_WRITE;
196 miiaddr |= MDIO_CMD_MII_BUSY;
198 writel(val, priv->mac_reg + EMAC_MII_DATA);
199 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
201 start = get_timer(0);
202 while (get_timer(start) < timeout) {
203 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
204 MDIO_CMD_MII_BUSY)) {
214 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
216 u32 macid_lo, macid_hi;
218 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
220 macid_hi = mac_id[4] + (mac_id[5] << 8);
222 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
223 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
228 static void sun8i_adjust_link(struct emac_eth_dev *priv,
229 struct phy_device *phydev)
233 v = readl(priv->mac_reg + EMAC_CTL0);
242 switch (phydev->speed) {
253 writel(v, priv->mac_reg + EMAC_CTL0);
256 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
258 if (priv->use_internal_phy) {
259 /* H3 based SoC's that has an Internal 100MBit PHY
260 * needs to be configured and powered up before use
262 *reg &= ~H3_EPHY_DEFAULT_MASK;
263 *reg |= H3_EPHY_DEFAULT_VALUE;
264 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
265 *reg &= ~H3_EPHY_SHUTDOWN;
266 *reg |= H3_EPHY_SELECT;
268 /* This is to select External Gigabit PHY on
269 * the boards with H3 SoC.
271 *reg &= ~H3_EPHY_SELECT;
276 static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
281 reg = readl(priv->sysctl_reg + 0x30);
283 if (priv->variant == R40_GMAC)
286 if (priv->variant == H3_EMAC) {
287 ret = sun8i_emac_set_syscon_ephy(priv, ®);
292 reg &= ~(SC_ETCS_MASK | SC_EPIT);
293 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
296 switch (priv->interface) {
297 case PHY_INTERFACE_MODE_MII:
300 case PHY_INTERFACE_MODE_RGMII:
301 reg |= SC_EPIT | SC_ETCS_INT_GMII;
303 case PHY_INTERFACE_MODE_RMII:
304 if (priv->variant == H3_EMAC ||
305 priv->variant == A64_EMAC) {
306 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
309 /* RMII not supported on A83T */
311 debug("%s: Invalid PHY interface\n", __func__);
315 writel(reg, priv->sysctl_reg + 0x30);
320 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
322 struct phy_device *phydev;
324 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
328 phy_connect_dev(phydev, dev);
330 priv->phydev = phydev;
331 phy_config(priv->phydev);
336 static void rx_descs_init(struct emac_eth_dev *priv)
338 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
339 char *rxbuffs = &priv->rxbuffer[0];
340 struct emac_dma_desc *desc_p;
343 /* flush Rx buffers */
344 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
347 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
348 desc_p = &desc_table_p[idx];
349 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
351 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
352 desc_p->st |= CONFIG_ETH_RXSIZE;
353 desc_p->status = BIT(31);
356 /* Correcting the last pointer of the chain */
357 desc_p->next = (uintptr_t)&desc_table_p[0];
359 flush_dcache_range((uintptr_t)priv->rx_chain,
360 (uintptr_t)priv->rx_chain +
361 sizeof(priv->rx_chain));
363 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
364 priv->rx_currdescnum = 0;
367 static void tx_descs_init(struct emac_eth_dev *priv)
369 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
370 char *txbuffs = &priv->txbuffer[0];
371 struct emac_dma_desc *desc_p;
374 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
375 desc_p = &desc_table_p[idx];
376 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
378 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
379 desc_p->status = (1 << 31);
383 /* Correcting the last pointer of the chain */
384 desc_p->next = (uintptr_t)&desc_table_p[0];
386 /* Flush all Tx buffer descriptors */
387 flush_dcache_range((uintptr_t)priv->tx_chain,
388 (uintptr_t)priv->tx_chain +
389 sizeof(priv->tx_chain));
391 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
392 priv->tx_currdescnum = 0;
395 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
400 reg = readl((priv->mac_reg + EMAC_CTL1));
404 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
406 reg = readl(priv->mac_reg + EMAC_CTL1);
407 } while ((reg & 0x01) != 0 && (--timeout));
409 printf("%s: Timeout\n", __func__);
414 /* Rewrite mac address after reset */
415 _sun8i_write_hwaddr(priv, enetaddr);
417 v = readl(priv->mac_reg + EMAC_TX_CTL1);
418 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
420 writel(v, priv->mac_reg + EMAC_TX_CTL1);
422 v = readl(priv->mac_reg + EMAC_RX_CTL1);
423 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
424 * complete frame has been written to RX DMA FIFO
427 writel(v, priv->mac_reg + EMAC_RX_CTL1);
430 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
432 /* Initialize rx/tx descriptors */
437 phy_startup(priv->phydev);
439 sun8i_adjust_link(priv, priv->phydev);
442 v = readl(priv->mac_reg + EMAC_RX_CTL1);
444 writel(v, priv->mac_reg + EMAC_RX_CTL1);
446 v = readl(priv->mac_reg + EMAC_TX_CTL1);
448 writel(v, priv->mac_reg + EMAC_TX_CTL1);
451 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
452 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
457 static int parse_phy_pins(struct udevice *dev)
459 struct emac_eth_dev *priv = dev_get_priv(dev);
461 const char *pin_name;
462 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
464 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
467 printf("WARNING: emac: cannot find pinctrl-0 node\n");
471 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
472 "drive-strength", ~0);
475 drive = SUN4I_PINCTRL_10_MA;
476 else if (drive <= 20)
477 drive = SUN4I_PINCTRL_20_MA;
478 else if (drive <= 30)
479 drive = SUN4I_PINCTRL_30_MA;
481 drive = SUN4I_PINCTRL_40_MA;
484 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
485 pull = SUN4I_PINCTRL_PULL_UP;
486 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
487 pull = SUN4I_PINCTRL_PULL_DOWN;
492 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
497 pin = sunxi_name_to_gpio(pin_name);
501 if (priv->variant == H3_EMAC)
502 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
503 else if (priv->variant == R40_GMAC)
504 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
506 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
509 sunxi_gpio_set_drv(pin, drive);
511 sunxi_gpio_set_pull(pin, pull);
515 printf("WARNING: emac: cannot find pins property\n");
522 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
524 u32 status, desc_num = priv->rx_currdescnum;
525 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
526 int length = -EAGAIN;
528 uintptr_t desc_start = (uintptr_t)desc_p;
529 uintptr_t desc_end = desc_start +
530 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
532 ulong data_start = (uintptr_t)desc_p->buf_addr;
535 /* Invalidate entire buffer descriptor */
536 invalidate_dcache_range(desc_start, desc_end);
538 status = desc_p->status;
540 /* Check for DMA own bit */
541 if (!(status & BIT(31))) {
542 length = (desc_p->status >> 16) & 0x3FFF;
546 debug("RX: Bad Packet (runt)\n");
549 data_end = data_start + length;
550 /* Invalidate received data */
551 invalidate_dcache_range(rounddown(data_start,
556 if (length > CONFIG_ETH_RXSIZE) {
557 printf("Received packet is too big (len=%d)\n",
561 *packetp = (uchar *)(ulong)desc_p->buf_addr;
569 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
572 u32 v, desc_num = priv->tx_currdescnum;
573 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
574 uintptr_t desc_start = (uintptr_t)desc_p;
575 uintptr_t desc_end = desc_start +
576 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
578 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
579 uintptr_t data_end = data_start +
580 roundup(len, ARCH_DMA_MINALIGN);
582 /* Invalidate entire buffer descriptor */
583 invalidate_dcache_range(desc_start, desc_end);
586 /* Mandatory undocumented bit */
587 desc_p->st |= BIT(24);
589 memcpy((void *)data_start, packet, len);
591 /* Flush data to be sent */
592 flush_dcache_range(data_start, data_end);
595 desc_p->st |= BIT(30);
596 desc_p->st |= BIT(31);
599 desc_p->st |= BIT(29);
600 desc_p->status = BIT(31);
602 /*Descriptors st and status field has changed, so FLUSH it */
603 flush_dcache_range(desc_start, desc_end);
605 /* Move to next Descriptor and wrap around */
606 if (++desc_num >= CONFIG_TX_DESCR_NUM)
608 priv->tx_currdescnum = desc_num;
611 v = readl(priv->mac_reg + EMAC_TX_CTL1);
612 v |= BIT(31);/* mandatory */
613 v |= BIT(30);/* mandatory */
614 writel(v, priv->mac_reg + EMAC_TX_CTL1);
619 static int sun8i_eth_write_hwaddr(struct udevice *dev)
621 struct eth_pdata *pdata = dev_get_platdata(dev);
622 struct emac_eth_dev *priv = dev_get_priv(dev);
624 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
627 static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
629 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
631 if (priv->variant == H3_EMAC) {
632 /* Only H3/H5 have clock controls for internal EPHY */
633 if (priv->use_internal_phy) {
634 /* Set clock gating for ephy */
635 setbits_le32(&ccm->bus_gate4,
636 BIT(AHB_GATE_OFFSET_EPHY));
639 setbits_le32(&ccm->ahb_reset2_cfg,
640 BIT(AHB_RESET_OFFSET_EPHY));
644 if (priv->variant == R40_GMAC) {
645 /* Set clock gating for emac */
646 setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
649 setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
651 /* Select RGMII for R40 */
652 setbits_le32(&ccm->gmac_clk_cfg,
653 CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
654 CCM_GMAC_CTRL_GPIT_RGMII);
655 setbits_le32(&ccm->gmac_clk_cfg,
656 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
658 /* Set clock gating for emac */
659 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
662 setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
666 #if defined(CONFIG_DM_GPIO)
667 static int sun8i_mdio_reset(struct mii_dev *bus)
669 struct udevice *dev = bus->priv;
670 struct emac_eth_dev *priv = dev_get_priv(dev);
671 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
674 if (!dm_gpio_is_valid(&priv->reset_gpio))
678 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
682 udelay(pdata->reset_delays[0]);
684 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
688 udelay(pdata->reset_delays[1]);
690 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
694 udelay(pdata->reset_delays[2]);
700 static int sun8i_mdio_init(const char *name, struct udevice *priv)
702 struct mii_dev *bus = mdio_alloc();
705 debug("Failed to allocate MDIO bus\n");
709 bus->read = sun8i_mdio_read;
710 bus->write = sun8i_mdio_write;
711 snprintf(bus->name, sizeof(bus->name), name);
712 bus->priv = (void *)priv;
713 #if defined(CONFIG_DM_GPIO)
714 bus->reset = sun8i_mdio_reset;
717 return mdio_register(bus);
720 static int sun8i_emac_eth_start(struct udevice *dev)
722 struct eth_pdata *pdata = dev_get_platdata(dev);
724 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
727 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
729 struct emac_eth_dev *priv = dev_get_priv(dev);
731 return _sun8i_emac_eth_send(priv, packet, length);
734 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
736 struct emac_eth_dev *priv = dev_get_priv(dev);
738 return _sun8i_eth_recv(priv, packetp);
741 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
743 u32 desc_num = priv->rx_currdescnum;
744 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
745 uintptr_t desc_start = (uintptr_t)desc_p;
746 uintptr_t desc_end = desc_start +
747 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
749 /* Make the current descriptor valid again */
750 desc_p->status |= BIT(31);
752 /* Flush Status field of descriptor */
753 flush_dcache_range(desc_start, desc_end);
755 /* Move to next desc and wrap-around condition. */
756 if (++desc_num >= CONFIG_RX_DESCR_NUM)
758 priv->rx_currdescnum = desc_num;
763 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
766 struct emac_eth_dev *priv = dev_get_priv(dev);
768 return _sun8i_free_pkt(priv);
771 static void sun8i_emac_eth_stop(struct udevice *dev)
773 struct emac_eth_dev *priv = dev_get_priv(dev);
775 /* Stop Rx/Tx transmitter */
776 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
777 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
780 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
782 phy_shutdown(priv->phydev);
785 static int sun8i_emac_eth_probe(struct udevice *dev)
787 struct eth_pdata *pdata = dev_get_platdata(dev);
788 struct emac_eth_dev *priv = dev_get_priv(dev);
790 priv->mac_reg = (void *)pdata->iobase;
792 sun8i_emac_board_setup(priv);
793 sun8i_emac_set_syscon(priv);
795 sun8i_mdio_init(dev->name, dev);
796 priv->bus = miiphy_get_dev_by_name(dev->name);
798 return sun8i_phy_init(priv, dev);
801 static const struct eth_ops sun8i_emac_eth_ops = {
802 .start = sun8i_emac_eth_start,
803 .write_hwaddr = sun8i_eth_write_hwaddr,
804 .send = sun8i_emac_eth_send,
805 .recv = sun8i_emac_eth_recv,
806 .free_pkt = sun8i_eth_free_pkt,
807 .stop = sun8i_emac_eth_stop,
810 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
812 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
813 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
814 struct emac_eth_dev *priv = dev_get_priv(dev);
815 const char *phy_mode;
817 int node = dev_of_offset(dev);
819 #ifdef CONFIG_DM_GPIO
820 int reset_flags = GPIOD_IS_OUT;
824 pdata->iobase = devfdt_get_addr(dev);
825 if (pdata->iobase == FDT_ADDR_T_NONE) {
826 debug("%s: Cannot find MAC base address\n", __func__);
830 priv->variant = dev_get_driver_data(dev);
832 if (!priv->variant) {
833 printf("%s: Missing variant\n", __func__);
837 if (priv->variant != R40_GMAC) {
838 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
840 debug("%s: cannot find syscon node\n", __func__);
843 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
845 debug("%s: cannot find reg property in syscon node\n",
849 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
851 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
852 debug("%s: Cannot find syscon base address\n",
858 pdata->phy_interface = -1;
860 priv->use_internal_phy = false;
862 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
864 debug("%s: Cannot find PHY address\n", __func__);
867 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
869 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
872 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
873 printf("phy interface%d\n", pdata->phy_interface);
875 if (pdata->phy_interface == -1) {
876 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
880 if (priv->variant == H3_EMAC) {
881 int parent = fdt_parent_offset(gd->fdt_blob, offset);
884 !fdt_node_check_compatible(gd->fdt_blob, parent,
885 "allwinner,sun8i-h3-mdio-internal"))
886 priv->use_internal_phy = true;
889 priv->interface = pdata->phy_interface;
891 if (!priv->use_internal_phy)
894 #ifdef CONFIG_DM_GPIO
895 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
896 "snps,reset-active-low"))
897 reset_flags |= GPIOD_ACTIVE_LOW;
899 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
900 &priv->reset_gpio, reset_flags);
903 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
904 "snps,reset-delays-us",
905 sun8i_pdata->reset_delays, 3);
906 } else if (ret == -ENOENT) {
914 static const struct udevice_id sun8i_emac_eth_ids[] = {
915 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
916 {.compatible = "allwinner,sun50i-a64-emac",
917 .data = (uintptr_t)A64_EMAC },
918 {.compatible = "allwinner,sun8i-a83t-emac",
919 .data = (uintptr_t)A83T_EMAC },
920 {.compatible = "allwinner,sun8i-r40-gmac",
921 .data = (uintptr_t)R40_GMAC },
925 U_BOOT_DRIVER(eth_sun8i_emac) = {
926 .name = "eth_sun8i_emac",
928 .of_match = sun8i_emac_eth_ids,
929 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
930 .probe = sun8i_emac_eth_probe,
931 .ops = &sun8i_emac_eth_ops,
932 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
933 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
934 .flags = DM_FLAG_ALLOC_PRIV_DMA,