1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
6 * Ethernet driver for H3/A64/A83T based SoC's
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
15 #include <asm/arch/clock.h>
16 #include <asm/arch/gpio.h>
20 #include <fdt_support.h>
21 #include <dm/device_compat.h>
22 #include <linux/err.h>
27 #include <dt-bindings/pinctrl/sun4i-a10.h>
28 #if CONFIG_IS_ENABLED(DM_GPIO)
29 #include <asm-generic/gpio.h>
32 #define MDIO_CMD_MII_BUSY BIT(0)
33 #define MDIO_CMD_MII_WRITE BIT(1)
35 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
36 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
37 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
38 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
40 #define CONFIG_TX_DESCR_NUM 32
41 #define CONFIG_RX_DESCR_NUM 32
42 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
45 * The datasheet says that each descriptor can transfers up to 4096 bytes
46 * But later, the register documentation reduces that value to 2048,
47 * using 2048 cause strange behaviours and even BSP driver use 2047
49 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
51 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
52 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
54 #define H3_EPHY_DEFAULT_VALUE 0x58000
55 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
56 #define H3_EPHY_ADDR_SHIFT 20
57 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
58 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
59 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
60 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
62 #define SC_RMII_EN BIT(13)
63 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
64 #define SC_ETCS_MASK GENMASK(1, 0)
65 #define SC_ETCS_EXT_GMII 0x1
66 #define SC_ETCS_INT_GMII 0x2
67 #define SC_ETXDC_MASK GENMASK(12, 10)
68 #define SC_ETXDC_OFFSET 10
69 #define SC_ERXDC_MASK GENMASK(9, 5)
70 #define SC_ERXDC_OFFSET 5
72 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
74 #define AHB_GATE_OFFSET_EPHY 0
77 #define SUN8I_IOMUX_H3 2
78 #define SUN8I_IOMUX_R40 5
81 /* H3/A64 EMAC Register's offset */
82 #define EMAC_CTL0 0x00
83 #define EMAC_CTL1 0x04
84 #define EMAC_INT_STA 0x08
85 #define EMAC_INT_EN 0x0c
86 #define EMAC_TX_CTL0 0x10
87 #define EMAC_TX_CTL1 0x14
88 #define EMAC_TX_FLOW_CTL 0x1c
89 #define EMAC_TX_DMA_DESC 0x20
90 #define EMAC_RX_CTL0 0x24
91 #define EMAC_RX_CTL1 0x28
92 #define EMAC_RX_DMA_DESC 0x34
93 #define EMAC_MII_CMD 0x48
94 #define EMAC_MII_DATA 0x4c
95 #define EMAC_ADDR0_HIGH 0x50
96 #define EMAC_ADDR0_LOW 0x54
97 #define EMAC_TX_DMA_STA 0xb0
98 #define EMAC_TX_CUR_DESC 0xb4
99 #define EMAC_TX_CUR_BUF 0xb8
100 #define EMAC_RX_DMA_STA 0xc0
101 #define EMAC_RX_CUR_DESC 0xc4
103 DECLARE_GLOBAL_DATA_PTR;
112 struct emac_dma_desc {
117 } __aligned(ARCH_DMA_MINALIGN);
119 struct emac_eth_dev {
120 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
121 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
122 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
123 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
135 bool use_internal_phy;
137 enum emac_variant variant;
139 phys_addr_t sysctl_reg;
140 struct phy_device *phydev;
144 struct reset_ctl tx_rst;
145 struct reset_ctl ephy_rst;
146 #if CONFIG_IS_ENABLED(DM_GPIO)
147 struct gpio_desc reset_gpio;
152 struct sun8i_eth_pdata {
153 struct eth_pdata eth_pdata;
160 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
162 struct udevice *dev = bus->priv;
163 struct emac_eth_dev *priv = dev_get_priv(dev);
166 int timeout = CONFIG_MDIO_TIMEOUT;
168 miiaddr &= ~MDIO_CMD_MII_WRITE;
169 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
170 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
171 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
173 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
175 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
176 MDIO_CMD_MII_PHY_ADDR_MASK;
178 miiaddr |= MDIO_CMD_MII_BUSY;
180 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
182 start = get_timer(0);
183 while (get_timer(start) < timeout) {
184 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
185 return readl(priv->mac_reg + EMAC_MII_DATA);
192 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
195 struct udevice *dev = bus->priv;
196 struct emac_eth_dev *priv = dev_get_priv(dev);
199 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
201 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
202 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
203 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
205 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
206 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
207 MDIO_CMD_MII_PHY_ADDR_MASK;
209 miiaddr |= MDIO_CMD_MII_WRITE;
210 miiaddr |= MDIO_CMD_MII_BUSY;
212 writel(val, priv->mac_reg + EMAC_MII_DATA);
213 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
215 start = get_timer(0);
216 while (get_timer(start) < timeout) {
217 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
218 MDIO_CMD_MII_BUSY)) {
228 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
230 u32 macid_lo, macid_hi;
232 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
234 macid_hi = mac_id[4] + (mac_id[5] << 8);
236 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
237 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
242 static void sun8i_adjust_link(struct emac_eth_dev *priv,
243 struct phy_device *phydev)
247 v = readl(priv->mac_reg + EMAC_CTL0);
256 switch (phydev->speed) {
267 writel(v, priv->mac_reg + EMAC_CTL0);
270 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
272 if (priv->use_internal_phy) {
273 /* H3 based SoC's that has an Internal 100MBit PHY
274 * needs to be configured and powered up before use
276 *reg &= ~H3_EPHY_DEFAULT_MASK;
277 *reg |= H3_EPHY_DEFAULT_VALUE;
278 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
279 *reg &= ~H3_EPHY_SHUTDOWN;
280 *reg |= H3_EPHY_SELECT;
282 /* This is to select External Gigabit PHY on
283 * the boards with H3 SoC.
285 *reg &= ~H3_EPHY_SELECT;
290 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
291 struct emac_eth_dev *priv)
296 if (priv->variant == R40_GMAC) {
297 /* Select RGMII for R40 */
298 reg = readl(priv->sysctl_reg + 0x164);
299 reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
300 CCM_GMAC_CTRL_GPIT_RGMII |
301 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
303 writel(reg, priv->sysctl_reg + 0x164);
307 reg = readl(priv->sysctl_reg + 0x30);
309 if (priv->variant == H3_EMAC) {
310 ret = sun8i_emac_set_syscon_ephy(priv, ®);
315 reg &= ~(SC_ETCS_MASK | SC_EPIT);
316 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
319 switch (priv->interface) {
320 case PHY_INTERFACE_MODE_MII:
323 case PHY_INTERFACE_MODE_RGMII:
324 reg |= SC_EPIT | SC_ETCS_INT_GMII;
326 case PHY_INTERFACE_MODE_RMII:
327 if (priv->variant == H3_EMAC ||
328 priv->variant == A64_EMAC) {
329 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
332 /* RMII not supported on A83T */
334 debug("%s: Invalid PHY interface\n", __func__);
338 if (pdata->tx_delay_ps)
339 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
342 if (pdata->rx_delay_ps)
343 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
346 writel(reg, priv->sysctl_reg + 0x30);
351 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
353 struct phy_device *phydev;
355 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
359 phy_connect_dev(phydev, dev);
361 priv->phydev = phydev;
362 phy_config(priv->phydev);
367 static void rx_descs_init(struct emac_eth_dev *priv)
369 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
370 char *rxbuffs = &priv->rxbuffer[0];
371 struct emac_dma_desc *desc_p;
374 /* flush Rx buffers */
375 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
378 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
379 desc_p = &desc_table_p[idx];
380 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
382 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
383 desc_p->st |= CONFIG_ETH_RXSIZE;
384 desc_p->status = BIT(31);
387 /* Correcting the last pointer of the chain */
388 desc_p->next = (uintptr_t)&desc_table_p[0];
390 flush_dcache_range((uintptr_t)priv->rx_chain,
391 (uintptr_t)priv->rx_chain +
392 sizeof(priv->rx_chain));
394 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
395 priv->rx_currdescnum = 0;
398 static void tx_descs_init(struct emac_eth_dev *priv)
400 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
401 char *txbuffs = &priv->txbuffer[0];
402 struct emac_dma_desc *desc_p;
405 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
406 desc_p = &desc_table_p[idx];
407 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
409 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
410 desc_p->status = (1 << 31);
414 /* Correcting the last pointer of the chain */
415 desc_p->next = (uintptr_t)&desc_table_p[0];
417 /* Flush all Tx buffer descriptors */
418 flush_dcache_range((uintptr_t)priv->tx_chain,
419 (uintptr_t)priv->tx_chain +
420 sizeof(priv->tx_chain));
422 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
423 priv->tx_currdescnum = 0;
426 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
431 reg = readl((priv->mac_reg + EMAC_CTL1));
435 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
437 reg = readl(priv->mac_reg + EMAC_CTL1);
438 } while ((reg & 0x01) != 0 && (--timeout));
440 printf("%s: Timeout\n", __func__);
445 /* Rewrite mac address after reset */
446 _sun8i_write_hwaddr(priv, enetaddr);
448 v = readl(priv->mac_reg + EMAC_TX_CTL1);
449 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
451 writel(v, priv->mac_reg + EMAC_TX_CTL1);
453 v = readl(priv->mac_reg + EMAC_RX_CTL1);
454 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
455 * complete frame has been written to RX DMA FIFO
458 writel(v, priv->mac_reg + EMAC_RX_CTL1);
461 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
463 /* Initialize rx/tx descriptors */
468 phy_startup(priv->phydev);
470 sun8i_adjust_link(priv, priv->phydev);
473 v = readl(priv->mac_reg + EMAC_RX_CTL1);
475 writel(v, priv->mac_reg + EMAC_RX_CTL1);
477 v = readl(priv->mac_reg + EMAC_TX_CTL1);
479 writel(v, priv->mac_reg + EMAC_TX_CTL1);
482 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
483 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
488 static int parse_phy_pins(struct udevice *dev)
490 struct emac_eth_dev *priv = dev_get_priv(dev);
492 const char *pin_name;
493 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
495 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
498 printf("WARNING: emac: cannot find pinctrl-0 node\n");
502 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
503 "drive-strength", ~0);
506 drive = SUN4I_PINCTRL_10_MA;
507 else if (drive <= 20)
508 drive = SUN4I_PINCTRL_20_MA;
509 else if (drive <= 30)
510 drive = SUN4I_PINCTRL_30_MA;
512 drive = SUN4I_PINCTRL_40_MA;
515 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
516 pull = SUN4I_PINCTRL_PULL_UP;
517 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
518 pull = SUN4I_PINCTRL_PULL_DOWN;
523 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
528 pin = sunxi_name_to_gpio(pin_name);
532 if (priv->variant == H3_EMAC)
533 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
534 else if (priv->variant == R40_GMAC)
535 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
537 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
540 sunxi_gpio_set_drv(pin, drive);
542 sunxi_gpio_set_pull(pin, pull);
546 printf("WARNING: emac: cannot find pins property\n");
553 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
555 u32 status, desc_num = priv->rx_currdescnum;
556 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
557 int length = -EAGAIN;
559 uintptr_t desc_start = (uintptr_t)desc_p;
560 uintptr_t desc_end = desc_start +
561 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
563 ulong data_start = (uintptr_t)desc_p->buf_addr;
566 /* Invalidate entire buffer descriptor */
567 invalidate_dcache_range(desc_start, desc_end);
569 status = desc_p->status;
571 /* Check for DMA own bit */
572 if (!(status & BIT(31))) {
573 length = (desc_p->status >> 16) & 0x3FFF;
577 debug("RX: Bad Packet (runt)\n");
580 data_end = data_start + length;
581 /* Invalidate received data */
582 invalidate_dcache_range(rounddown(data_start,
587 if (length > CONFIG_ETH_RXSIZE) {
588 printf("Received packet is too big (len=%d)\n",
592 *packetp = (uchar *)(ulong)desc_p->buf_addr;
600 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
603 u32 v, desc_num = priv->tx_currdescnum;
604 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
605 uintptr_t desc_start = (uintptr_t)desc_p;
606 uintptr_t desc_end = desc_start +
607 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
609 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
610 uintptr_t data_end = data_start +
611 roundup(len, ARCH_DMA_MINALIGN);
613 /* Invalidate entire buffer descriptor */
614 invalidate_dcache_range(desc_start, desc_end);
617 /* Mandatory undocumented bit */
618 desc_p->st |= BIT(24);
620 memcpy((void *)data_start, packet, len);
622 /* Flush data to be sent */
623 flush_dcache_range(data_start, data_end);
626 desc_p->st |= BIT(30);
627 desc_p->st |= BIT(31);
630 desc_p->st |= BIT(29);
631 desc_p->status = BIT(31);
633 /*Descriptors st and status field has changed, so FLUSH it */
634 flush_dcache_range(desc_start, desc_end);
636 /* Move to next Descriptor and wrap around */
637 if (++desc_num >= CONFIG_TX_DESCR_NUM)
639 priv->tx_currdescnum = desc_num;
642 v = readl(priv->mac_reg + EMAC_TX_CTL1);
643 v |= BIT(31);/* mandatory */
644 v |= BIT(30);/* mandatory */
645 writel(v, priv->mac_reg + EMAC_TX_CTL1);
650 static int sun8i_eth_write_hwaddr(struct udevice *dev)
652 struct eth_pdata *pdata = dev_get_platdata(dev);
653 struct emac_eth_dev *priv = dev_get_priv(dev);
655 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
658 static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
662 ret = clk_enable(&priv->tx_clk);
664 dev_err(dev, "failed to enable TX clock\n");
668 if (reset_valid(&priv->tx_rst)) {
669 ret = reset_deassert(&priv->tx_rst);
671 dev_err(dev, "failed to deassert TX reset\n");
676 /* Only H3/H5 have clock controls for internal EPHY */
677 if (clk_valid(&priv->ephy_clk)) {
678 ret = clk_enable(&priv->ephy_clk);
680 dev_err(dev, "failed to enable EPHY TX clock\n");
685 if (reset_valid(&priv->ephy_rst)) {
686 ret = reset_deassert(&priv->ephy_rst);
688 dev_err(dev, "failed to deassert EPHY TX clock\n");
696 clk_disable(&priv->tx_clk);
700 #if CONFIG_IS_ENABLED(DM_GPIO)
701 static int sun8i_mdio_reset(struct mii_dev *bus)
703 struct udevice *dev = bus->priv;
704 struct emac_eth_dev *priv = dev_get_priv(dev);
705 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
708 if (!dm_gpio_is_valid(&priv->reset_gpio))
712 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
716 udelay(pdata->reset_delays[0]);
718 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
722 udelay(pdata->reset_delays[1]);
724 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
728 udelay(pdata->reset_delays[2]);
734 static int sun8i_mdio_init(const char *name, struct udevice *priv)
736 struct mii_dev *bus = mdio_alloc();
739 debug("Failed to allocate MDIO bus\n");
743 bus->read = sun8i_mdio_read;
744 bus->write = sun8i_mdio_write;
745 snprintf(bus->name, sizeof(bus->name), name);
746 bus->priv = (void *)priv;
747 #if CONFIG_IS_ENABLED(DM_GPIO)
748 bus->reset = sun8i_mdio_reset;
751 return mdio_register(bus);
754 static int sun8i_emac_eth_start(struct udevice *dev)
756 struct eth_pdata *pdata = dev_get_platdata(dev);
758 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
761 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
763 struct emac_eth_dev *priv = dev_get_priv(dev);
765 return _sun8i_emac_eth_send(priv, packet, length);
768 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
770 struct emac_eth_dev *priv = dev_get_priv(dev);
772 return _sun8i_eth_recv(priv, packetp);
775 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
777 u32 desc_num = priv->rx_currdescnum;
778 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
779 uintptr_t desc_start = (uintptr_t)desc_p;
780 uintptr_t desc_end = desc_start +
781 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
783 /* Make the current descriptor valid again */
784 desc_p->status |= BIT(31);
786 /* Flush Status field of descriptor */
787 flush_dcache_range(desc_start, desc_end);
789 /* Move to next desc and wrap-around condition. */
790 if (++desc_num >= CONFIG_RX_DESCR_NUM)
792 priv->rx_currdescnum = desc_num;
797 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
800 struct emac_eth_dev *priv = dev_get_priv(dev);
802 return _sun8i_free_pkt(priv);
805 static void sun8i_emac_eth_stop(struct udevice *dev)
807 struct emac_eth_dev *priv = dev_get_priv(dev);
809 /* Stop Rx/Tx transmitter */
810 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
811 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
814 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
816 phy_shutdown(priv->phydev);
819 static int sun8i_emac_eth_probe(struct udevice *dev)
821 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
822 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
823 struct emac_eth_dev *priv = dev_get_priv(dev);
826 priv->mac_reg = (void *)pdata->iobase;
828 ret = sun8i_emac_board_setup(priv);
832 sun8i_emac_set_syscon(sun8i_pdata, priv);
834 sun8i_mdio_init(dev->name, dev);
835 priv->bus = miiphy_get_dev_by_name(dev->name);
837 return sun8i_phy_init(priv, dev);
840 static const struct eth_ops sun8i_emac_eth_ops = {
841 .start = sun8i_emac_eth_start,
842 .write_hwaddr = sun8i_eth_write_hwaddr,
843 .send = sun8i_emac_eth_send,
844 .recv = sun8i_emac_eth_recv,
845 .free_pkt = sun8i_eth_free_pkt,
846 .stop = sun8i_emac_eth_stop,
849 static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
851 int emac_node, ephy_node, ret, ephy_handle;
853 emac_node = fdt_path_offset(gd->fdt_blob,
854 "/soc/ethernet@1c30000");
856 debug("failed to get emac node\n");
859 ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
860 emac_node, "phy-handle");
862 /* look for mdio-mux node for internal PHY node */
863 ephy_node = fdt_path_offset(gd->fdt_blob,
864 "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
866 debug("failed to get mdio-mux with internal PHY\n");
870 /* This is not the phy we are looking for */
871 if (ephy_node != ephy_handle)
874 ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
875 "allwinner,sun8i-h3-mdio-internal");
877 debug("failed to find mdio-internal node\n");
881 ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
884 dev_err(dev, "failed to get EPHY TX clock\n");
888 ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
891 dev_err(dev, "failed to get EPHY TX reset\n");
895 priv->use_internal_phy = true;
900 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
902 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
903 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
904 struct emac_eth_dev *priv = dev_get_priv(dev);
905 const char *phy_mode;
907 int node = dev_of_offset(dev);
909 #if CONFIG_IS_ENABLED(DM_GPIO)
910 int reset_flags = GPIOD_IS_OUT;
914 pdata->iobase = devfdt_get_addr(dev);
915 if (pdata->iobase == FDT_ADDR_T_NONE) {
916 debug("%s: Cannot find MAC base address\n", __func__);
920 priv->variant = dev_get_driver_data(dev);
922 if (!priv->variant) {
923 printf("%s: Missing variant\n", __func__);
927 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
929 dev_err(dev, "failed to get TX clock\n");
933 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
934 if (ret && ret != -ENOENT) {
935 dev_err(dev, "failed to get TX reset\n");
939 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
941 debug("%s: cannot find syscon node\n", __func__);
945 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
947 debug("%s: cannot find reg property in syscon node\n",
951 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
953 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
954 debug("%s: Cannot find syscon base address\n", __func__);
958 pdata->phy_interface = -1;
960 priv->use_internal_phy = false;
962 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
964 debug("%s: Cannot find PHY address\n", __func__);
967 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
969 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
972 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
973 printf("phy interface%d\n", pdata->phy_interface);
975 if (pdata->phy_interface == -1) {
976 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
980 if (priv->variant == H3_EMAC) {
981 ret = sun8i_get_ephy_nodes(priv);
986 priv->interface = pdata->phy_interface;
988 if (!priv->use_internal_phy)
991 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
992 "allwinner,tx-delay-ps", 0);
993 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
994 printf("%s: Invalid TX delay value %d\n", __func__,
995 sun8i_pdata->tx_delay_ps);
997 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
998 "allwinner,rx-delay-ps", 0);
999 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
1000 printf("%s: Invalid RX delay value %d\n", __func__,
1001 sun8i_pdata->rx_delay_ps);
1003 #if CONFIG_IS_ENABLED(DM_GPIO)
1004 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
1005 "snps,reset-active-low"))
1006 reset_flags |= GPIOD_ACTIVE_LOW;
1008 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
1009 &priv->reset_gpio, reset_flags);
1012 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
1013 "snps,reset-delays-us",
1014 sun8i_pdata->reset_delays, 3);
1015 } else if (ret == -ENOENT) {
1023 static const struct udevice_id sun8i_emac_eth_ids[] = {
1024 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1025 {.compatible = "allwinner,sun50i-a64-emac",
1026 .data = (uintptr_t)A64_EMAC },
1027 {.compatible = "allwinner,sun8i-a83t-emac",
1028 .data = (uintptr_t)A83T_EMAC },
1029 {.compatible = "allwinner,sun8i-r40-gmac",
1030 .data = (uintptr_t)R40_GMAC },
1034 U_BOOT_DRIVER(eth_sun8i_emac) = {
1035 .name = "eth_sun8i_emac",
1037 .of_match = sun8i_emac_eth_ids,
1038 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
1039 .probe = sun8i_emac_eth_probe,
1040 .ops = &sun8i_emac_eth_ops,
1041 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
1042 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
1043 .flags = DM_FLAG_ALLOC_PRIV_DMA,