1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
6 * Ethernet driver for H3/A64/A83T based SoC's
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
14 #include <asm/arch/clock.h>
15 #include <asm/arch/gpio.h>
19 #include <fdt_support.h>
20 #include <linux/err.h>
25 #include <dt-bindings/pinctrl/sun4i-a10.h>
27 #include <asm-generic/gpio.h>
30 #define MDIO_CMD_MII_BUSY BIT(0)
31 #define MDIO_CMD_MII_WRITE BIT(1)
33 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
34 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
35 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
36 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
38 #define CONFIG_TX_DESCR_NUM 32
39 #define CONFIG_RX_DESCR_NUM 32
40 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
43 * The datasheet says that each descriptor can transfers up to 4096 bytes
44 * But later, the register documentation reduces that value to 2048,
45 * using 2048 cause strange behaviours and even BSP driver use 2047
47 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
49 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
50 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
52 #define H3_EPHY_DEFAULT_VALUE 0x58000
53 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
54 #define H3_EPHY_ADDR_SHIFT 20
55 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
56 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
57 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
58 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
60 #define SC_RMII_EN BIT(13)
61 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
62 #define SC_ETCS_MASK GENMASK(1, 0)
63 #define SC_ETCS_EXT_GMII 0x1
64 #define SC_ETCS_INT_GMII 0x2
65 #define SC_ETXDC_MASK GENMASK(12, 10)
66 #define SC_ETXDC_OFFSET 10
67 #define SC_ERXDC_MASK GENMASK(9, 5)
68 #define SC_ERXDC_OFFSET 5
70 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
72 #define AHB_GATE_OFFSET_EPHY 0
75 #define SUN8I_IOMUX_H3 2
76 #define SUN8I_IOMUX_R40 5
79 /* H3/A64 EMAC Register's offset */
80 #define EMAC_CTL0 0x00
81 #define EMAC_CTL1 0x04
82 #define EMAC_INT_STA 0x08
83 #define EMAC_INT_EN 0x0c
84 #define EMAC_TX_CTL0 0x10
85 #define EMAC_TX_CTL1 0x14
86 #define EMAC_TX_FLOW_CTL 0x1c
87 #define EMAC_TX_DMA_DESC 0x20
88 #define EMAC_RX_CTL0 0x24
89 #define EMAC_RX_CTL1 0x28
90 #define EMAC_RX_DMA_DESC 0x34
91 #define EMAC_MII_CMD 0x48
92 #define EMAC_MII_DATA 0x4c
93 #define EMAC_ADDR0_HIGH 0x50
94 #define EMAC_ADDR0_LOW 0x54
95 #define EMAC_TX_DMA_STA 0xb0
96 #define EMAC_TX_CUR_DESC 0xb4
97 #define EMAC_TX_CUR_BUF 0xb8
98 #define EMAC_RX_DMA_STA 0xc0
99 #define EMAC_RX_CUR_DESC 0xc4
101 DECLARE_GLOBAL_DATA_PTR;
110 struct emac_dma_desc {
115 } __aligned(ARCH_DMA_MINALIGN);
117 struct emac_eth_dev {
118 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
119 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
120 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
121 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
133 bool use_internal_phy;
135 enum emac_variant variant;
137 phys_addr_t sysctl_reg;
138 struct phy_device *phydev;
142 struct reset_ctl tx_rst;
143 struct reset_ctl ephy_rst;
144 #ifdef CONFIG_DM_GPIO
145 struct gpio_desc reset_gpio;
150 struct sun8i_eth_pdata {
151 struct eth_pdata eth_pdata;
158 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
160 struct udevice *dev = bus->priv;
161 struct emac_eth_dev *priv = dev_get_priv(dev);
164 int timeout = CONFIG_MDIO_TIMEOUT;
166 miiaddr &= ~MDIO_CMD_MII_WRITE;
167 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
168 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
169 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
171 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
173 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
174 MDIO_CMD_MII_PHY_ADDR_MASK;
176 miiaddr |= MDIO_CMD_MII_BUSY;
178 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
180 start = get_timer(0);
181 while (get_timer(start) < timeout) {
182 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
183 return readl(priv->mac_reg + EMAC_MII_DATA);
190 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
193 struct udevice *dev = bus->priv;
194 struct emac_eth_dev *priv = dev_get_priv(dev);
197 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
199 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
200 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
201 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
203 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
204 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
205 MDIO_CMD_MII_PHY_ADDR_MASK;
207 miiaddr |= MDIO_CMD_MII_WRITE;
208 miiaddr |= MDIO_CMD_MII_BUSY;
210 writel(val, priv->mac_reg + EMAC_MII_DATA);
211 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
213 start = get_timer(0);
214 while (get_timer(start) < timeout) {
215 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
216 MDIO_CMD_MII_BUSY)) {
226 static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
228 u32 macid_lo, macid_hi;
230 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
232 macid_hi = mac_id[4] + (mac_id[5] << 8);
234 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
235 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
240 static void sun8i_adjust_link(struct emac_eth_dev *priv,
241 struct phy_device *phydev)
245 v = readl(priv->mac_reg + EMAC_CTL0);
254 switch (phydev->speed) {
265 writel(v, priv->mac_reg + EMAC_CTL0);
268 static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
270 if (priv->use_internal_phy) {
271 /* H3 based SoC's that has an Internal 100MBit PHY
272 * needs to be configured and powered up before use
274 *reg &= ~H3_EPHY_DEFAULT_MASK;
275 *reg |= H3_EPHY_DEFAULT_VALUE;
276 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
277 *reg &= ~H3_EPHY_SHUTDOWN;
278 *reg |= H3_EPHY_SELECT;
280 /* This is to select External Gigabit PHY on
281 * the boards with H3 SoC.
283 *reg &= ~H3_EPHY_SELECT;
288 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
289 struct emac_eth_dev *priv)
294 if (priv->variant == R40_GMAC) {
295 /* Select RGMII for R40 */
296 reg = readl(priv->sysctl_reg + 0x164);
297 reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
298 CCM_GMAC_CTRL_GPIT_RGMII |
299 CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
301 writel(reg, priv->sysctl_reg + 0x164);
305 reg = readl(priv->sysctl_reg + 0x30);
307 if (priv->variant == H3_EMAC) {
308 ret = sun8i_emac_set_syscon_ephy(priv, ®);
313 reg &= ~(SC_ETCS_MASK | SC_EPIT);
314 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
317 switch (priv->interface) {
318 case PHY_INTERFACE_MODE_MII:
321 case PHY_INTERFACE_MODE_RGMII:
322 reg |= SC_EPIT | SC_ETCS_INT_GMII;
324 case PHY_INTERFACE_MODE_RMII:
325 if (priv->variant == H3_EMAC ||
326 priv->variant == A64_EMAC) {
327 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
330 /* RMII not supported on A83T */
332 debug("%s: Invalid PHY interface\n", __func__);
336 if (pdata->tx_delay_ps)
337 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
340 if (pdata->rx_delay_ps)
341 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
344 writel(reg, priv->sysctl_reg + 0x30);
349 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
351 struct phy_device *phydev;
353 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
357 phy_connect_dev(phydev, dev);
359 priv->phydev = phydev;
360 phy_config(priv->phydev);
365 static void rx_descs_init(struct emac_eth_dev *priv)
367 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
368 char *rxbuffs = &priv->rxbuffer[0];
369 struct emac_dma_desc *desc_p;
372 /* flush Rx buffers */
373 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
376 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
377 desc_p = &desc_table_p[idx];
378 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
380 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
381 desc_p->st |= CONFIG_ETH_RXSIZE;
382 desc_p->status = BIT(31);
385 /* Correcting the last pointer of the chain */
386 desc_p->next = (uintptr_t)&desc_table_p[0];
388 flush_dcache_range((uintptr_t)priv->rx_chain,
389 (uintptr_t)priv->rx_chain +
390 sizeof(priv->rx_chain));
392 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
393 priv->rx_currdescnum = 0;
396 static void tx_descs_init(struct emac_eth_dev *priv)
398 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
399 char *txbuffs = &priv->txbuffer[0];
400 struct emac_dma_desc *desc_p;
403 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
404 desc_p = &desc_table_p[idx];
405 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
407 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
408 desc_p->status = (1 << 31);
412 /* Correcting the last pointer of the chain */
413 desc_p->next = (uintptr_t)&desc_table_p[0];
415 /* Flush all Tx buffer descriptors */
416 flush_dcache_range((uintptr_t)priv->tx_chain,
417 (uintptr_t)priv->tx_chain +
418 sizeof(priv->tx_chain));
420 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
421 priv->tx_currdescnum = 0;
424 static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
429 reg = readl((priv->mac_reg + EMAC_CTL1));
433 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
435 reg = readl(priv->mac_reg + EMAC_CTL1);
436 } while ((reg & 0x01) != 0 && (--timeout));
438 printf("%s: Timeout\n", __func__);
443 /* Rewrite mac address after reset */
444 _sun8i_write_hwaddr(priv, enetaddr);
446 v = readl(priv->mac_reg + EMAC_TX_CTL1);
447 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
449 writel(v, priv->mac_reg + EMAC_TX_CTL1);
451 v = readl(priv->mac_reg + EMAC_RX_CTL1);
452 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
453 * complete frame has been written to RX DMA FIFO
456 writel(v, priv->mac_reg + EMAC_RX_CTL1);
459 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
461 /* Initialize rx/tx descriptors */
466 phy_startup(priv->phydev);
468 sun8i_adjust_link(priv, priv->phydev);
471 v = readl(priv->mac_reg + EMAC_RX_CTL1);
473 writel(v, priv->mac_reg + EMAC_RX_CTL1);
475 v = readl(priv->mac_reg + EMAC_TX_CTL1);
477 writel(v, priv->mac_reg + EMAC_TX_CTL1);
480 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
481 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
486 static int parse_phy_pins(struct udevice *dev)
488 struct emac_eth_dev *priv = dev_get_priv(dev);
490 const char *pin_name;
491 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
493 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
496 printf("WARNING: emac: cannot find pinctrl-0 node\n");
500 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
501 "drive-strength", ~0);
504 drive = SUN4I_PINCTRL_10_MA;
505 else if (drive <= 20)
506 drive = SUN4I_PINCTRL_20_MA;
507 else if (drive <= 30)
508 drive = SUN4I_PINCTRL_30_MA;
510 drive = SUN4I_PINCTRL_40_MA;
513 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
514 pull = SUN4I_PINCTRL_PULL_UP;
515 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
516 pull = SUN4I_PINCTRL_PULL_DOWN;
521 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
526 pin = sunxi_name_to_gpio(pin_name);
530 if (priv->variant == H3_EMAC)
531 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
532 else if (priv->variant == R40_GMAC)
533 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
535 sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
538 sunxi_gpio_set_drv(pin, drive);
540 sunxi_gpio_set_pull(pin, pull);
544 printf("WARNING: emac: cannot find pins property\n");
551 static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
553 u32 status, desc_num = priv->rx_currdescnum;
554 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
555 int length = -EAGAIN;
557 uintptr_t desc_start = (uintptr_t)desc_p;
558 uintptr_t desc_end = desc_start +
559 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
561 ulong data_start = (uintptr_t)desc_p->buf_addr;
564 /* Invalidate entire buffer descriptor */
565 invalidate_dcache_range(desc_start, desc_end);
567 status = desc_p->status;
569 /* Check for DMA own bit */
570 if (!(status & BIT(31))) {
571 length = (desc_p->status >> 16) & 0x3FFF;
575 debug("RX: Bad Packet (runt)\n");
578 data_end = data_start + length;
579 /* Invalidate received data */
580 invalidate_dcache_range(rounddown(data_start,
585 if (length > CONFIG_ETH_RXSIZE) {
586 printf("Received packet is too big (len=%d)\n",
590 *packetp = (uchar *)(ulong)desc_p->buf_addr;
598 static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
601 u32 v, desc_num = priv->tx_currdescnum;
602 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
603 uintptr_t desc_start = (uintptr_t)desc_p;
604 uintptr_t desc_end = desc_start +
605 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
607 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
608 uintptr_t data_end = data_start +
609 roundup(len, ARCH_DMA_MINALIGN);
611 /* Invalidate entire buffer descriptor */
612 invalidate_dcache_range(desc_start, desc_end);
615 /* Mandatory undocumented bit */
616 desc_p->st |= BIT(24);
618 memcpy((void *)data_start, packet, len);
620 /* Flush data to be sent */
621 flush_dcache_range(data_start, data_end);
624 desc_p->st |= BIT(30);
625 desc_p->st |= BIT(31);
628 desc_p->st |= BIT(29);
629 desc_p->status = BIT(31);
631 /*Descriptors st and status field has changed, so FLUSH it */
632 flush_dcache_range(desc_start, desc_end);
634 /* Move to next Descriptor and wrap around */
635 if (++desc_num >= CONFIG_TX_DESCR_NUM)
637 priv->tx_currdescnum = desc_num;
640 v = readl(priv->mac_reg + EMAC_TX_CTL1);
641 v |= BIT(31);/* mandatory */
642 v |= BIT(30);/* mandatory */
643 writel(v, priv->mac_reg + EMAC_TX_CTL1);
648 static int sun8i_eth_write_hwaddr(struct udevice *dev)
650 struct eth_pdata *pdata = dev_get_platdata(dev);
651 struct emac_eth_dev *priv = dev_get_priv(dev);
653 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
656 static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
660 ret = clk_enable(&priv->tx_clk);
662 dev_err(dev, "failed to enable TX clock\n");
666 if (reset_valid(&priv->tx_rst)) {
667 ret = reset_deassert(&priv->tx_rst);
669 dev_err(dev, "failed to deassert TX reset\n");
674 /* Only H3/H5 have clock controls for internal EPHY */
675 if (clk_valid(&priv->ephy_clk)) {
676 ret = clk_enable(&priv->ephy_clk);
678 dev_err(dev, "failed to enable EPHY TX clock\n");
683 if (reset_valid(&priv->ephy_rst)) {
684 ret = reset_deassert(&priv->ephy_rst);
686 dev_err(dev, "failed to deassert EPHY TX clock\n");
694 clk_disable(&priv->tx_clk);
698 #if defined(CONFIG_DM_GPIO)
699 static int sun8i_mdio_reset(struct mii_dev *bus)
701 struct udevice *dev = bus->priv;
702 struct emac_eth_dev *priv = dev_get_priv(dev);
703 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
706 if (!dm_gpio_is_valid(&priv->reset_gpio))
710 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
714 udelay(pdata->reset_delays[0]);
716 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
720 udelay(pdata->reset_delays[1]);
722 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
726 udelay(pdata->reset_delays[2]);
732 static int sun8i_mdio_init(const char *name, struct udevice *priv)
734 struct mii_dev *bus = mdio_alloc();
737 debug("Failed to allocate MDIO bus\n");
741 bus->read = sun8i_mdio_read;
742 bus->write = sun8i_mdio_write;
743 snprintf(bus->name, sizeof(bus->name), name);
744 bus->priv = (void *)priv;
745 #if defined(CONFIG_DM_GPIO)
746 bus->reset = sun8i_mdio_reset;
749 return mdio_register(bus);
752 static int sun8i_emac_eth_start(struct udevice *dev)
754 struct eth_pdata *pdata = dev_get_platdata(dev);
756 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
759 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
761 struct emac_eth_dev *priv = dev_get_priv(dev);
763 return _sun8i_emac_eth_send(priv, packet, length);
766 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
768 struct emac_eth_dev *priv = dev_get_priv(dev);
770 return _sun8i_eth_recv(priv, packetp);
773 static int _sun8i_free_pkt(struct emac_eth_dev *priv)
775 u32 desc_num = priv->rx_currdescnum;
776 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
777 uintptr_t desc_start = (uintptr_t)desc_p;
778 uintptr_t desc_end = desc_start +
779 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
781 /* Make the current descriptor valid again */
782 desc_p->status |= BIT(31);
784 /* Flush Status field of descriptor */
785 flush_dcache_range(desc_start, desc_end);
787 /* Move to next desc and wrap-around condition. */
788 if (++desc_num >= CONFIG_RX_DESCR_NUM)
790 priv->rx_currdescnum = desc_num;
795 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
798 struct emac_eth_dev *priv = dev_get_priv(dev);
800 return _sun8i_free_pkt(priv);
803 static void sun8i_emac_eth_stop(struct udevice *dev)
805 struct emac_eth_dev *priv = dev_get_priv(dev);
807 /* Stop Rx/Tx transmitter */
808 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
809 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
812 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
814 phy_shutdown(priv->phydev);
817 static int sun8i_emac_eth_probe(struct udevice *dev)
819 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
820 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
821 struct emac_eth_dev *priv = dev_get_priv(dev);
824 priv->mac_reg = (void *)pdata->iobase;
826 ret = sun8i_emac_board_setup(priv);
830 sun8i_emac_set_syscon(sun8i_pdata, priv);
832 sun8i_mdio_init(dev->name, dev);
833 priv->bus = miiphy_get_dev_by_name(dev->name);
835 return sun8i_phy_init(priv, dev);
838 static const struct eth_ops sun8i_emac_eth_ops = {
839 .start = sun8i_emac_eth_start,
840 .write_hwaddr = sun8i_eth_write_hwaddr,
841 .send = sun8i_emac_eth_send,
842 .recv = sun8i_emac_eth_recv,
843 .free_pkt = sun8i_eth_free_pkt,
844 .stop = sun8i_emac_eth_stop,
847 static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
849 int emac_node, ephy_node, ret, ephy_handle;
851 emac_node = fdt_path_offset(gd->fdt_blob,
852 "/soc/ethernet@1c30000");
854 debug("failed to get emac node\n");
857 ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
858 emac_node, "phy-handle");
860 /* look for mdio-mux node for internal PHY node */
861 ephy_node = fdt_path_offset(gd->fdt_blob,
862 "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
864 debug("failed to get mdio-mux with internal PHY\n");
868 /* This is not the phy we are looking for */
869 if (ephy_node != ephy_handle)
872 ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
873 "allwinner,sun8i-h3-mdio-internal");
875 debug("failed to find mdio-internal node\n");
879 ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
882 dev_err(dev, "failed to get EPHY TX clock\n");
886 ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
889 dev_err(dev, "failed to get EPHY TX reset\n");
893 priv->use_internal_phy = true;
898 static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
900 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
901 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
902 struct emac_eth_dev *priv = dev_get_priv(dev);
903 const char *phy_mode;
905 int node = dev_of_offset(dev);
907 #ifdef CONFIG_DM_GPIO
908 int reset_flags = GPIOD_IS_OUT;
912 pdata->iobase = devfdt_get_addr(dev);
913 if (pdata->iobase == FDT_ADDR_T_NONE) {
914 debug("%s: Cannot find MAC base address\n", __func__);
918 priv->variant = dev_get_driver_data(dev);
920 if (!priv->variant) {
921 printf("%s: Missing variant\n", __func__);
925 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
927 dev_err(dev, "failed to get TX clock\n");
931 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
932 if (ret && ret != -ENOENT) {
933 dev_err(dev, "failed to get TX reset\n");
937 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
939 debug("%s: cannot find syscon node\n", __func__);
943 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
945 debug("%s: cannot find reg property in syscon node\n",
949 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
951 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
952 debug("%s: Cannot find syscon base address\n", __func__);
956 pdata->phy_interface = -1;
958 priv->use_internal_phy = false;
960 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
962 debug("%s: Cannot find PHY address\n", __func__);
965 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
967 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
970 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
971 printf("phy interface%d\n", pdata->phy_interface);
973 if (pdata->phy_interface == -1) {
974 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
978 if (priv->variant == H3_EMAC) {
979 ret = sun8i_get_ephy_nodes(priv);
984 priv->interface = pdata->phy_interface;
986 if (!priv->use_internal_phy)
989 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
990 "allwinner,tx-delay-ps", 0);
991 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
992 printf("%s: Invalid TX delay value %d\n", __func__,
993 sun8i_pdata->tx_delay_ps);
995 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
996 "allwinner,rx-delay-ps", 0);
997 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
998 printf("%s: Invalid RX delay value %d\n", __func__,
999 sun8i_pdata->rx_delay_ps);
1001 #ifdef CONFIG_DM_GPIO
1002 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
1003 "snps,reset-active-low"))
1004 reset_flags |= GPIOD_ACTIVE_LOW;
1006 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
1007 &priv->reset_gpio, reset_flags);
1010 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
1011 "snps,reset-delays-us",
1012 sun8i_pdata->reset_delays, 3);
1013 } else if (ret == -ENOENT) {
1021 static const struct udevice_id sun8i_emac_eth_ids[] = {
1022 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1023 {.compatible = "allwinner,sun50i-a64-emac",
1024 .data = (uintptr_t)A64_EMAC },
1025 {.compatible = "allwinner,sun8i-a83t-emac",
1026 .data = (uintptr_t)A83T_EMAC },
1027 {.compatible = "allwinner,sun8i-r40-gmac",
1028 .data = (uintptr_t)R40_GMAC },
1032 U_BOOT_DRIVER(eth_sun8i_emac) = {
1033 .name = "eth_sun8i_emac",
1035 .of_match = sun8i_emac_eth_ids,
1036 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
1037 .probe = sun8i_emac_eth_probe,
1038 .ops = &sun8i_emac_eth_ops,
1039 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
1040 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
1041 .flags = DM_FLAG_ALLOC_PRIV_DMA,