2 * sh_eth.h - Driver for Renesas SuperH ethernet controller.
4 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
5 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/types.h>
14 #define SHETHER_NAME "sh_eth"
16 #if defined(CONFIG_SH)
17 /* Malloc returns addresses in the P1 area (cacheable). However we need to
18 use area P2 (non-cacheable) */
19 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
21 /* The ethernet controller needs to use physical addresses */
22 #if defined(CONFIG_SH_32BIT)
23 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
25 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
27 #elif defined(CONFIG_ARM)
32 #define ADDR_TO_PHY(addr) ((int)(addr))
33 #define ADDR_TO_P2(addr) (addr)
34 #endif /* defined(CONFIG_SH) */
36 /* base padding size is 16 */
37 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
38 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
41 /* Number of supported ports */
42 #define MAX_PORT_NUM 2
44 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
45 buffers must be a multiple of 32 bytes */
46 #define MAX_BUF_SIZE (48 * 32)
48 /* The number of tx descriptors must be large enough to point to 5 or more
49 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
50 We use one descriptor per frame */
53 /* The size of the tx descriptor is determined by how much padding is used.
54 4, 20, or 52 bytes of padding can be used */
55 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
57 /* Tx descriptor. We always use 3 bytes of padding */
61 u32 td2; /* Buffer start */
62 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
65 /* There is no limitation in the number of rx descriptors */
68 /* The size of the rx descriptor is determined by how much padding is used.
69 4, 20, or 52 bytes of padding can be used */
70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
71 /* aligned cache line size */
72 #define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
74 /* Rx descriptor. We always use 4 bytes of padding */
78 u32 rd2; /* Buffer start */
79 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
83 struct tx_desc_s *tx_desc_alloc;
84 struct tx_desc_s *tx_desc_base;
85 struct tx_desc_s *tx_desc_cur;
86 struct rx_desc_s *rx_desc_alloc;
87 struct rx_desc_s *rx_desc_base;
88 struct rx_desc_s *rx_desc_cur;
93 struct eth_device *dev;
94 struct phy_device *phydev;
100 struct sh_eth_info port_info[MAX_PORT_NUM];
103 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
105 /* E-DMAC registers */
134 /* Ether registers */
168 RMIIMR, /* R8A7790 */
174 /* This value must be written at last. */
175 SH_ETH_MAX_REGISTER_OFFSET,
178 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
232 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
285 /* Register Address */
286 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
287 #define SH_ETH_TYPE_GETHER
288 #define BASE_IO_ADDR 0xfee00000
289 #elif defined(CONFIG_CPU_SH7757) || \
290 defined(CONFIG_CPU_SH7752) || \
291 defined(CONFIG_CPU_SH7753)
292 #if defined(CONFIG_SH_ETHER_USE_GETHER)
293 #define SH_ETH_TYPE_GETHER
294 #define BASE_IO_ADDR 0xfee00000
296 #define SH_ETH_TYPE_ETHER
297 #define BASE_IO_ADDR 0xfef00000
299 #elif defined(CONFIG_CPU_SH7724)
300 #define SH_ETH_TYPE_ETHER
301 #define BASE_IO_ADDR 0xA4600000
302 #elif defined(CONFIG_R8A7740)
303 #define SH_ETH_TYPE_GETHER
304 #define BASE_IO_ADDR 0xE9A00000
305 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
306 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
307 #define SH_ETH_TYPE_ETHER
308 #define BASE_IO_ADDR 0xEE700200
309 #elif defined(CONFIG_R7S72100)
310 #define SH_ETH_TYPE_RZ
311 #define BASE_IO_ADDR 0xE8203000
316 * Copy from Linux driver source code
318 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
321 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
323 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
328 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
329 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
330 EDMR_SRST = 0x03, /* Receive/Send reset */
331 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
332 EDMR_EL = 0x40, /* Litte endian */
333 #elif defined(SH_ETH_TYPE_ETHER)
335 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
336 EDMR_EL = 0x40, /* Litte endian */
342 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
343 # define EMDR_DESC EDMR_DL1
344 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
345 # define EMDR_DESC EDMR_DL0
346 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
351 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
355 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
364 #if defined(CONFIG_CPU_SH7757) || \
365 defined(CONFIG_CPU_SH7752) || \
366 defined(CONFIG_CPU_SH7753)
367 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
369 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
380 TPAUSER_TPAUSE = 0x0000ffff,
381 TPAUSER_UNLIMITED = 0,
386 BCFR_RPAUSE = 0x0000ffff,
392 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
396 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
400 #if defined(SH_ETH_TYPE_ETHER)
401 EESR_TWB = 0x40000000,
403 EESR_TWB = 0xC0000000,
404 EESR_TC1 = 0x20000000,
405 EESR_TUC = 0x10000000,
406 EESR_ROC = 0x80000000,
408 EESR_TABT = 0x04000000,
409 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
410 #if defined(SH_ETH_TYPE_ETHER)
411 EESR_ADE = 0x00800000,
413 EESR_ECI = 0x00400000,
414 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
415 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
416 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
417 #if defined(SH_ETH_TYPE_ETHER)
418 EESR_CND = 0x00000800,
420 EESR_DLC = 0x00000400,
421 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
422 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
423 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
424 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
425 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
429 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
430 # define TX_CHECK (EESR_TC1 | EESR_FTC)
431 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
432 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
433 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
436 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
437 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
438 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
439 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
444 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
445 DMAC_M_RABT = 0x02000000,
446 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
447 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
448 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
449 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
450 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
451 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
452 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
453 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
454 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
455 DMAC_M_RINT1 = 0x00000001,
458 /* Receive descriptor bit */
460 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
461 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
462 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
463 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
464 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
465 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
466 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
467 RD_RFS1 = 0x00000001,
469 #define RDF1ST RD_RFP1
470 #define RDFEND RD_RFP0
471 #define RD_RFP (RD_RFP1|RD_RFP0)
480 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
481 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
482 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
484 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
485 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
487 /* Transfer descriptor bit */
489 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
490 defined(SH_ETH_TYPE_RZ)
491 TD_TACT = 0x80000000,
493 TD_TACT = 0x7fffffff,
495 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
496 TD_TFP0 = 0x10000000,
498 #define TDF1ST TD_TFP1
499 #define TDFEND TD_TFP0
500 #define TD_TFP (TD_TFP1|TD_TFP0)
503 enum RECV_RST_BIT { RMCR_RST = 0x01, };
505 enum FELIC_MODE_BIT {
506 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
507 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
508 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
510 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
511 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
512 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
513 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
514 ECMR_PRM = 0x00000001,
515 #ifdef CONFIG_CPU_SH7724
516 ECMR_RTM = 0x00000010,
517 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
518 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
519 ECMR_RTM = 0x00000004,
524 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
525 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
526 ECMR_RXF | ECMR_TXF | ECMR_MCT)
527 #elif defined(SH_ETH_TYPE_ETHER)
528 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
530 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
534 enum ECSR_STATUS_BIT {
535 #if defined(SH_ETH_TYPE_ETHER)
536 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
539 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
542 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
543 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
545 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
546 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
550 enum ECSIPR_STATUS_MASK_BIT {
551 #if defined(SH_ETH_TYPE_ETHER)
552 ECSIPR_BRCRXIP = 0x20,
553 ECSIPR_PSRTOIP = 0x10,
554 #elif defined(SH_ETY_TYPE_GETHER)
555 ECSIPR_PSRTOIP = 0x10,
558 ECSIPR_LCHNGIP = 0x04,
563 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
564 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
566 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
567 ECSIPR_ICDIP | ECSIPR_MPDIP)
582 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
583 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
584 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
585 DESC_I_RINT1 = 0x0001,
590 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
591 RPADIR_PADR = 0x0003f,
594 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
595 # define RPADIR_INIT (0x00)
597 # define RPADIR_INIT (RPADIR_PADS1)
602 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
605 static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
608 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
609 const u16 *reg_offset = sh_eth_offset_gigabit;
610 #elif defined(SH_ETH_TYPE_ETHER)
611 const u16 *reg_offset = sh_eth_offset_fast_sh4;
615 return (unsigned long)port->iobase + reg_offset[enum_index];
618 static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
621 outl(data, sh_eth_reg_addr(port, enum_index));
624 static inline unsigned long sh_eth_read(struct sh_eth_info *port,
627 return inl(sh_eth_reg_addr(port, enum_index));