2 * sh_eth.h - Driver for Renesas SuperH ethernet controler.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <asm/types.h>
26 #define SHETHER_NAME "sh_eth"
28 /* Malloc returns addresses in the P1 area (cacheable). However we need to
29 use area P2 (non-cacheable) */
30 #define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
32 /* The ethernet controller needs to use physical addresses */
33 #if defined(CONFIG_SH_32BIT)
34 #define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
36 #define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
39 /* Number of supported ports */
40 #define MAX_PORT_NUM 2
42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
43 buffers must be a multiple of 32 bytes */
44 #define MAX_BUF_SIZE (48 * 32)
46 /* The number of tx descriptors must be large enough to point to 5 or more
47 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
48 We use one descriptor per frame */
51 /* The size of the tx descriptor is determined by how much padding is used.
52 4, 20, or 52 bytes of padding can be used */
53 #define TX_DESC_PADDING 4
54 #define TX_DESC_SIZE (12 + TX_DESC_PADDING)
56 /* Tx descriptor. We always use 3 bytes of padding */
60 u32 td2; /* Buffer start */
64 /* There is no limitation in the number of rx descriptors */
67 /* The size of the rx descriptor is determined by how much padding is used.
68 4, 20, or 52 bytes of padding can be used */
69 #define RX_DESC_PADDING 4
70 #define RX_DESC_SIZE (12 + RX_DESC_PADDING)
72 /* Rx descriptor. We always use 4 bytes of padding */
76 u32 rd2; /* Buffer start */
81 struct tx_desc_s *tx_desc_malloc;
82 struct tx_desc_s *tx_desc_base;
83 struct tx_desc_s *tx_desc_cur;
84 struct rx_desc_s *rx_desc_malloc;
85 struct rx_desc_s *rx_desc_base;
86 struct rx_desc_s *rx_desc_cur;
91 struct eth_device *dev;
92 struct phy_device *phydev;
97 struct sh_eth_info port_info[MAX_PORT_NUM];
100 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
102 /* E-DMAC registers */
131 /* Ether registers */
170 /* This value must be written at last. */
171 SH_ETH_MAX_REGISTER_OFFSET,
174 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
228 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
280 /* Register Address */
281 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
282 #define SH_ETH_TYPE_GETHER
283 #define BASE_IO_ADDR 0xfee00000
284 #elif defined(CONFIG_CPU_SH7757)
285 #define SH_ETH_TYPE_ETHER
286 #define BASE_IO_ADDR 0xfef00000
287 #elif defined(CONFIG_CPU_SH7724)
288 #define SH_ETH_TYPE_ETHER
289 #define BASE_IO_ADDR 0xA4600000
294 * Copy from Linux driver source code
296 #if defined(SH_ETH_TYPE_GETHER)
299 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
301 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
306 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
307 #if defined(SH_ETH_TYPE_GETHER)
308 EDMR_SRST = 0x03, /* Receive/Send reset */
309 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
310 EDMR_EL = 0x40, /* Litte endian */
311 #elif defined(SH_ETH_TYPE_ETHER)
313 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
314 EDMR_EL = 0x40, /* Litte endian */
321 #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
325 #if defined(SH_ETH_TYPE_GETHER)
334 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
344 TPAUSER_TPAUSE = 0x0000ffff,
345 TPAUSER_UNLIMITED = 0,
350 BCFR_RPAUSE = 0x0000ffff,
356 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
360 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
365 #if defined(SH_ETH_TYPE_ETHER)
366 EESR_TWB = 0x40000000,
368 EESR_TWB = 0xC0000000,
369 EESR_TC1 = 0x20000000,
370 EESR_TUC = 0x10000000,
371 EESR_ROC = 0x80000000,
373 EESR_TABT = 0x04000000,
374 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
375 #if defined(SH_ETH_TYPE_ETHER)
376 EESR_ADE = 0x00800000,
378 EESR_ECI = 0x00400000,
379 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
380 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
381 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
382 #if defined(SH_ETH_TYPE_ETHER)
383 EESR_CND = 0x00000800,
385 EESR_DLC = 0x00000400,
386 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
387 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
388 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
389 rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
390 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
394 #if defined(SH_ETH_TYPE_GETHER)
395 # define TX_CHECK (EESR_TC1 | EESR_FTC)
396 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
397 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
398 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
401 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
402 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
403 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
404 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
409 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
410 DMAC_M_RABT = 0x02000000,
411 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
412 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
413 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
414 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
415 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
416 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
417 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
418 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
419 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
420 DMAC_M_RINT1 = 0x00000001,
423 /* Receive descriptor bit */
425 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
426 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
427 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
428 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
429 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
430 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
431 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
432 RD_RFS1 = 0x00000001,
434 #define RDF1ST RD_RFP1
435 #define RDFEND RD_RFP0
436 #define RD_RFP (RD_RFP1|RD_RFP0)
445 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
446 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
447 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
449 #define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
450 #define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
452 /* Transfer descriptor bit */
454 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
455 TD_TACT = 0x80000000,
457 TD_TACT = 0x7fffffff,
459 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
460 TD_TFP0 = 0x10000000,
462 #define TDF1ST TD_TFP1
463 #define TDFEND TD_TFP0
464 #define TD_TFP (TD_TFP1|TD_TFP0)
467 enum RECV_RST_BIT { RMCR_RST = 0x01, };
469 enum FELIC_MODE_BIT {
470 #if defined(SH_ETH_TYPE_GETHER)
471 ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
472 ECMR_RZPF = 0x00100000,
474 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
475 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
476 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
477 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
478 ECMR_PRM = 0x00000001,
479 #ifdef CONFIG_CPU_SH7724
480 ECMR_RTM = 0x00000010,
485 #if defined(SH_ETH_TYPE_GETHER)
486 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
488 #elif defined(SH_ETH_TYPE_ETHER)
489 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
491 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
495 enum ECSR_STATUS_BIT {
496 #if defined(SH_ETH_TYPE_ETHER)
497 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
500 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
503 #if defined(SH_ETH_TYPE_GETHER)
504 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
506 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
507 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
511 enum ECSIPR_STATUS_MASK_BIT {
512 #if defined(SH_ETH_TYPE_ETHER)
513 ECSIPR_BRCRXIP = 0x20,
514 ECSIPR_PSRTOIP = 0x10,
515 #elif defined(SH_ETY_TYPE_GETHER)
516 ECSIPR_PSRTOIP = 0x10,
519 ECSIPR_LCHNGIP = 0x04,
524 #if defined(SH_ETH_TYPE_GETHER)
525 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
527 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
528 ECSIPR_ICDIP | ECSIPR_MPDIP)
543 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
544 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
545 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
546 DESC_I_RINT1 = 0x0001,
551 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
552 RPADIR_PADR = 0x0003f,
555 #if defined(SH_ETH_TYPE_GETHER)
556 # define RPADIR_INIT (0x00)
558 # define RPADIR_INIT (RPADIR_PADS1)
563 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
566 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
569 #if defined(SH_ETH_TYPE_GETHER)
570 const u16 *reg_offset = sh_eth_offset_gigabit;
571 #elif defined(SH_ETH_TYPE_ETHER)
572 const u16 *reg_offset = sh_eth_offset_fast_sh4;
576 return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
579 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
582 outl(data, sh_eth_reg_addr(eth, enum_index));
585 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
588 return inl(sh_eth_reg_addr(eth, enum_index));