drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <env.h>
  14 #include <malloc.h>
  15 #include <net.h>
  16 #include <netdev.h>
  17 #include <miiphy.h>
  18 #include <linux/errno.h>
  19 #include <asm/io.h>
  20
  21 #ifdef CONFIG_DM_ETH
  22 #include <clk.h>
  23 #include <dm.h>
  24 #include <linux/mii.h>
  25 #include <asm/gpio.h>
  26 #endif
  27
  28 #include "sh_eth.h"
  29
  30 #ifndef CONFIG_SH_ETHER_USE_PORT
  31 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  32 #endif
  33 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  35 #endif
  36
  37 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  38         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  39 #define flush_cache_wback(addr, len)    \
  40                 flush_dcache_range((unsigned long)addr, \
  41                 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  42 #else
  43 #define flush_cache_wback(...)
  44 #endif
  45
  46 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  47 #define invalidate_cache(addr, len)             \
  48         {       \
  49                 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;  \
  50                 unsigned long start, end;       \
  51                 \
  52                 start = (unsigned long)addr;    \
  53                 end = start + len;              \
  54                 start &= ~(line_size - 1);      \
  55                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  56                 \
  57                 invalidate_dcache_range(start, end);    \
  58         }
  59 #else
  60 #define invalidate_cache(...)
  61 #endif
  62
  63 #define TIMEOUT_CNT 1000
  64
  65 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  66 {
  67         int ret = 0, timeout;
  68         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  69
  70         if (!packet || len > 0xffff) {
  71                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  72                 ret = -EINVAL;
  73                 goto err;
  74         }
  75
  76         /* packet must be a 4 byte boundary */
  77         if ((uintptr_t)packet & 3) {
  78                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  79                                 , __func__);
  80                 ret = -EFAULT;
  81                 goto err;
  82         }
  83
  84         /* Update tx descriptor */
  85         flush_cache_wback(packet, len);
  86         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  87         port_info->tx_desc_cur->td1 = len << 16;
  88         /* Must preserve the end of descriptor list indication */
  89         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  90                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  91         else
  92                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  93
  94         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  95
  96         /* Restart the transmitter if disabled */
  97         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  98                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
  99
 100         /* Wait until packet is transmitted */
 101         timeout = TIMEOUT_CNT;
 102         do {
 103                 invalidate_cache(port_info->tx_desc_cur,
 104                                  sizeof(struct tx_desc_s));
 105                 udelay(100);
 106         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 107
 108         if (timeout < 0) {
 109                 printf(SHETHER_NAME ": transmit timeout\n");
 110                 ret = -ETIMEDOUT;
 111                 goto err;
 112         }
 113
 114         port_info->tx_desc_cur++;
 115         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 116                 port_info->tx_desc_cur = port_info->tx_desc_base;
 117
 118 err:
 119         return ret;
 120 }
 121
 122 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 123 {
 124         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 125
 126         /* Check if the rx descriptor is ready */
 127         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 128         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 129                 return -EINVAL;
 130
 131         /* Check for errors */
 132         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 133                 return -EINVAL;
 134
 135         return port_info->rx_desc_cur->rd1 & 0xffff;
 136 }
 137
 138 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 139 {
 140         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 141
 142         /* Make current descriptor available again */
 143         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 144                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 145         else
 146                 port_info->rx_desc_cur->rd0 = RD_RACT;
 147
 148         flush_cache_wback(port_info->rx_desc_cur,
 149                           sizeof(struct rx_desc_s));
 150
 151         /* Point to the next descriptor */
 152         port_info->rx_desc_cur++;
 153         if (port_info->rx_desc_cur >=
 154             port_info->rx_desc_base + NUM_RX_DESC)
 155                 port_info->rx_desc_cur = port_info->rx_desc_base;
 156 }
 157
 158 static int sh_eth_reset(struct sh_eth_dev *eth)
 159 {
 160         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 161 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 162         int ret = 0, i;
 163
 164         /* Start e-dmac transmitter and receiver */
 165         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 166
 167         /* Perform a software reset and wait for it to complete */
 168         sh_eth_write(port_info, EDMR_SRST, EDMR);
 169         for (i = 0; i < TIMEOUT_CNT; i++) {
 170                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 171                         break;
 172                 udelay(1000);
 173         }
 174
 175         if (i == TIMEOUT_CNT) {
 176                 printf(SHETHER_NAME  ": Software reset timeout\n");
 177                 ret = -EIO;
 178         }
 179
 180         return ret;
 181 #else
 182         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 183         mdelay(3);
 184         sh_eth_write(port_info,
 185                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 186
 187         return 0;
 188 #endif
 189 }
 190
 191 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 192 {
 193         int i, ret = 0;
 194         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 195         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 196         struct tx_desc_s *cur_tx_desc;
 197
 198         /*
 199          * Allocate rx descriptors. They must be aligned to size of struct
 200          * tx_desc_s.
 201          */
 202         port_info->tx_desc_alloc =
 203                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 204         if (!port_info->tx_desc_alloc) {
 205                 printf(SHETHER_NAME ": memalign failed\n");
 206                 ret = -ENOMEM;
 207                 goto err;
 208         }
 209
 210         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 211
 212         /* Make sure we use a P2 address (non-cacheable) */
 213         port_info->tx_desc_base =
 214                 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
 215         port_info->tx_desc_cur = port_info->tx_desc_base;
 216
 217         /* Initialize all descriptors */
 218         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 219              cur_tx_desc++, i++) {
 220                 cur_tx_desc->td0 = 0x00;
 221                 cur_tx_desc->td1 = 0x00;
 222                 cur_tx_desc->td2 = 0x00;
 223         }
 224
 225         /* Mark the end of the descriptors */
 226         cur_tx_desc--;
 227         cur_tx_desc->td0 |= TD_TDLE;
 228
 229         /*
 230          * Point the controller to the tx descriptor list. Must use physical
 231          * addresses
 232          */
 233         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 234 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 235         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 236         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 237         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 238 #endif
 239
 240 err:
 241         return ret;
 242 }
 243
 244 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 245 {
 246         int i, ret = 0;
 247         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 248         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 249         struct rx_desc_s *cur_rx_desc;
 250         u8 *rx_buf;
 251
 252         /*
 253          * Allocate rx descriptors. They must be aligned to size of struct
 254          * rx_desc_s.
 255          */
 256         port_info->rx_desc_alloc =
 257                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 258         if (!port_info->rx_desc_alloc) {
 259                 printf(SHETHER_NAME ": memalign failed\n");
 260                 ret = -ENOMEM;
 261                 goto err;
 262         }
 263
 264         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 265
 266         /* Make sure we use a P2 address (non-cacheable) */
 267         port_info->rx_desc_base =
 268                 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 269
 270         port_info->rx_desc_cur = port_info->rx_desc_base;
 271
 272         /*
 273          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 274          * aligned and in P2 area.
 275          */
 276         port_info->rx_buf_alloc =
 277                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 278         if (!port_info->rx_buf_alloc) {
 279                 printf(SHETHER_NAME ": alloc failed\n");
 280                 ret = -ENOMEM;
 281                 goto err_buf_alloc;
 282         }
 283
 284         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 285
 286         /* Initialize all descriptors */
 287         for (cur_rx_desc = port_info->rx_desc_base,
 288              rx_buf = port_info->rx_buf_base, i = 0;
 289              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 290                 cur_rx_desc->rd0 = RD_RACT;
 291                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 292                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 293         }
 294
 295         /* Mark the end of the descriptors */
 296         cur_rx_desc--;
 297         cur_rx_desc->rd0 |= RD_RDLE;
 298
 299         /* Point the controller to the rx descriptor list */
 300         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 301 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 302         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 303         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 304         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 305 #endif
 306
 307         return ret;
 308
 309 err_buf_alloc:
 310         free(port_info->rx_desc_alloc);
 311         port_info->rx_desc_alloc = NULL;
 312
 313 err:
 314         return ret;
 315 }
 316
 317 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 318 {
 319         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 320
 321         if (port_info->tx_desc_alloc) {
 322                 free(port_info->tx_desc_alloc);
 323                 port_info->tx_desc_alloc = NULL;
 324         }
 325 }
 326
 327 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 328 {
 329         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 330
 331         if (port_info->rx_desc_alloc) {
 332                 free(port_info->rx_desc_alloc);
 333                 port_info->rx_desc_alloc = NULL;
 334         }
 335
 336         if (port_info->rx_buf_alloc) {
 337                 free(port_info->rx_buf_alloc);
 338                 port_info->rx_buf_alloc = NULL;
 339         }
 340 }
 341
 342 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 343 {
 344         int ret = 0;
 345
 346         ret = sh_eth_tx_desc_init(eth);
 347         if (ret)
 348                 goto err_tx_init;
 349
 350         ret = sh_eth_rx_desc_init(eth);
 351         if (ret)
 352                 goto err_rx_init;
 353
 354         return ret;
 355 err_rx_init:
 356         sh_eth_tx_desc_free(eth);
 357
 358 err_tx_init:
 359         return ret;
 360 }
 361
 362 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 363                                 unsigned char *mac)
 364 {
 365         u32 val;
 366
 367         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 368         sh_eth_write(port_info, val, MAHR);
 369
 370         val = (mac[4] << 8) | mac[5];
 371         sh_eth_write(port_info, val, MALR);
 372 }
 373
 374 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 375 {
 376         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 377         unsigned long edmr;
 378
 379         /* Configure e-dmac registers */
 380         edmr = sh_eth_read(port_info, EDMR);
 381         edmr &= ~EMDR_DESC_R;
 382         edmr |= EMDR_DESC | EDMR_EL;
 383 #if defined(CONFIG_R8A77980)
 384         edmr |= EDMR_NBST;
 385 #endif
 386         sh_eth_write(port_info, edmr, EDMR);
 387
 388         sh_eth_write(port_info, 0, EESIPR);
 389         sh_eth_write(port_info, 0, TRSCER);
 390         sh_eth_write(port_info, 0, TFTR);
 391         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 392         sh_eth_write(port_info, RMCR_RST, RMCR);
 393 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 394         sh_eth_write(port_info, 0, RPADIR);
 395 #endif
 396         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 397
 398         /* Configure e-mac registers */
 399         sh_eth_write(port_info, 0, ECSIPR);
 400
 401         /* Set Mac address */
 402         sh_eth_write_hwaddr(port_info, mac);
 403
 404         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 405 #if defined(SH_ETH_TYPE_GETHER)
 406         sh_eth_write(port_info, 0, PIPR);
 407 #endif
 408 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 409         sh_eth_write(port_info, APR_AP, APR);
 410         sh_eth_write(port_info, MPR_MP, MPR);
 411         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 412 #endif
 413
 414 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 415         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 416 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 417         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 418 #endif
 419 }
 420
 421 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 422 {
 423         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 424         struct phy_device *phy = port_info->phydev;
 425         int ret = 0;
 426         u32 val = 0;
 427
 428         /* Set the transfer speed */
 429         if (phy->speed == 100) {
 430                 printf(SHETHER_NAME ": 100Base/");
 431 #if defined(SH_ETH_TYPE_GETHER)
 432                 sh_eth_write(port_info, GECMR_100B, GECMR);
 433 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 434                 sh_eth_write(port_info, 1, RTRATE);
 435 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 436                 val = ECMR_RTM;
 437 #endif
 438         } else if (phy->speed == 10) {
 439                 printf(SHETHER_NAME ": 10Base/");
 440 #if defined(SH_ETH_TYPE_GETHER)
 441                 sh_eth_write(port_info, GECMR_10B, GECMR);
 442 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 443                 sh_eth_write(port_info, 0, RTRATE);
 444 #endif
 445         }
 446 #if defined(SH_ETH_TYPE_GETHER)
 447         else if (phy->speed == 1000) {
 448                 printf(SHETHER_NAME ": 1000Base/");
 449                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 450         }
 451 #endif
 452
 453         /* Check if full duplex mode is supported by the phy */
 454         if (phy->duplex) {
 455                 printf("Full\n");
 456                 sh_eth_write(port_info,
 457                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 458                              ECMR);
 459         } else {
 460                 printf("Half\n");
 461                 sh_eth_write(port_info,
 462                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 463                              ECMR);
 464         }
 465
 466         return ret;
 467 }
 468
 469 static void sh_eth_start(struct sh_eth_dev *eth)
 470 {
 471         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 472
 473         /*
 474          * Enable the e-dmac receiver only. The transmitter will be enabled when
 475          * we have something to transmit
 476          */
 477         sh_eth_write(port_info, EDRRR_R, EDRRR);
 478 }
 479
 480 static void sh_eth_stop(struct sh_eth_dev *eth)
 481 {
 482         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 483
 484         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 485 }
 486
 487 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 488 {
 489         int ret = 0;
 490
 491         ret = sh_eth_reset(eth);
 492         if (ret)
 493                 return ret;
 494
 495         ret = sh_eth_desc_init(eth);
 496         if (ret)
 497                 return ret;
 498
 499         sh_eth_mac_regs_config(eth, mac);
 500
 501         return 0;
 502 }
 503
 504 static int sh_eth_start_common(struct sh_eth_dev *eth)
 505 {
 506         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 507         int ret;
 508
 509         ret = phy_startup(port_info->phydev);
 510         if (ret) {
 511                 printf(SHETHER_NAME ": phy startup failure\n");
 512                 return ret;
 513         }
 514
 515         ret = sh_eth_phy_regs_config(eth);
 516         if (ret)
 517                 return ret;
 518
 519         sh_eth_start(eth);
 520
 521         return 0;
 522 }
 523
 524 #ifndef CONFIG_DM_ETH
 525 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
 526 {
 527         int ret = 0;
 528         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 529         struct eth_device *dev = port_info->dev;
 530         struct phy_device *phydev;
 531
 532         phydev = phy_connect(
 533                         miiphy_get_dev_by_name(dev->name),
 534                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 535         port_info->phydev = phydev;
 536         phy_config(phydev);
 537
 538         return ret;
 539 }
 540
 541 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
 542 {
 543         struct sh_eth_dev *eth = dev->priv;
 544
 545         return sh_eth_send_common(eth, packet, len);
 546 }
 547
 548 static int sh_eth_recv_common(struct sh_eth_dev *eth)
 549 {
 550         int len = 0;
 551         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 552         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 553
 554         len = sh_eth_recv_start(eth);
 555         if (len > 0) {
 556                 invalidate_cache(packet, len);
 557                 net_process_received_packet(packet, len);
 558                 sh_eth_recv_finish(eth);
 559         } else
 560                 len = 0;
 561
 562         /* Restart the receiver if disabled */
 563         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 564                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 565
 566         return len;
 567 }
 568
 569 static int sh_eth_recv_legacy(struct eth_device *dev)
 570 {
 571         struct sh_eth_dev *eth = dev->priv;
 572
 573         return sh_eth_recv_common(eth);
 574 }
 575
 576 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
 577 {
 578         struct sh_eth_dev *eth = dev->priv;
 579         int ret;
 580
 581         ret = sh_eth_init_common(eth, dev->enetaddr);
 582         if (ret)
 583                 return ret;
 584
 585         ret = sh_eth_phy_config_legacy(eth);
 586         if (ret) {
 587                 printf(SHETHER_NAME ": phy config timeout\n");
 588                 goto err_start;
 589         }
 590
 591         ret = sh_eth_start_common(eth);
 592         if (ret)
 593                 goto err_start;
 594
 595         return 0;
 596
 597 err_start:
 598         sh_eth_tx_desc_free(eth);
 599         sh_eth_rx_desc_free(eth);
 600         return ret;
 601 }
 602
 603 void sh_eth_halt_legacy(struct eth_device *dev)
 604 {
 605         struct sh_eth_dev *eth = dev->priv;
 606
 607         sh_eth_stop(eth);
 608 }
 609
 610 int sh_eth_initialize(bd_t *bd)
 611 {
 612         int ret = 0;
 613         struct sh_eth_dev *eth = NULL;
 614         struct eth_device *dev = NULL;
 615         struct mii_dev *mdiodev;
 616
 617         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 618         if (!eth) {
 619                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 620                 ret = -ENOMEM;
 621                 goto err;
 622         }
 623
 624         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 625         if (!dev) {
 626                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 627                 ret = -ENOMEM;
 628                 goto err;
 629         }
 630         memset(dev, 0, sizeof(struct eth_device));
 631         memset(eth, 0, sizeof(struct sh_eth_dev));
 632
 633         eth->port = CONFIG_SH_ETHER_USE_PORT;
 634         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 635         eth->port_info[eth->port].iobase =
 636                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 637
 638         dev->priv = (void *)eth;
 639         dev->iobase = 0;
 640         dev->init = sh_eth_init_legacy;
 641         dev->halt = sh_eth_halt_legacy;
 642         dev->send = sh_eth_send_legacy;
 643         dev->recv = sh_eth_recv_legacy;
 644         eth->port_info[eth->port].dev = dev;
 645
 646         strcpy(dev->name, SHETHER_NAME);
 647
 648         /* Register Device to EtherNet subsystem  */
 649         eth_register(dev);
 650
 651         bb_miiphy_buses[0].priv = eth;
 652         mdiodev = mdio_alloc();
 653         if (!mdiodev)
 654                 return -ENOMEM;
 655         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 656         mdiodev->read = bb_miiphy_read;
 657         mdiodev->write = bb_miiphy_write;
 658
 659         ret = mdio_register(mdiodev);
 660         if (ret < 0)
 661                 return ret;
 662
 663         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 664                 puts("Please set MAC address\n");
 665
 666         return ret;
 667
 668 err:
 669         if (dev)
 670                 free(dev);
 671
 672         if (eth)
 673                 free(eth);
 674
 675         printf(SHETHER_NAME ": Failed\n");
 676         return ret;
 677 }
 678
 679 #else /* CONFIG_DM_ETH */
 680
 681 struct sh_ether_priv {
 682         struct sh_eth_dev       shdev;
 683
 684         struct mii_dev          *bus;
 685         phys_addr_t             iobase;
 686         struct clk              clk;
 687         struct gpio_desc        reset_gpio;
 688 };
 689
 690 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 691 {
 692         struct sh_ether_priv *priv = dev_get_priv(dev);
 693         struct sh_eth_dev *eth = &priv->shdev;
 694
 695         return sh_eth_send_common(eth, packet, len);
 696 }
 697
 698 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 699 {
 700         struct sh_ether_priv *priv = dev_get_priv(dev);
 701         struct sh_eth_dev *eth = &priv->shdev;
 702         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 703         uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
 704         int len;
 705
 706         len = sh_eth_recv_start(eth);
 707         if (len > 0) {
 708                 invalidate_cache(packet, len);
 709                 *packetp = packet;
 710
 711                 return len;
 712         } else {
 713                 len = 0;
 714
 715                 /* Restart the receiver if disabled */
 716                 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 717                         sh_eth_write(port_info, EDRRR_R, EDRRR);
 718
 719                 return -EAGAIN;
 720         }
 721 }
 722
 723 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 724 {
 725         struct sh_ether_priv *priv = dev_get_priv(dev);
 726         struct sh_eth_dev *eth = &priv->shdev;
 727         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 728
 729         sh_eth_recv_finish(eth);
 730
 731         /* Restart the receiver if disabled */
 732         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 733                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 734
 735         return 0;
 736 }
 737
 738 static int sh_ether_write_hwaddr(struct udevice *dev)
 739 {
 740         struct sh_ether_priv *priv = dev_get_priv(dev);
 741         struct sh_eth_dev *eth = &priv->shdev;
 742         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 743         struct eth_pdata *pdata = dev_get_platdata(dev);
 744
 745         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 746
 747         return 0;
 748 }
 749
 750 static int sh_eth_phy_config(struct udevice *dev)
 751 {
 752         struct sh_ether_priv *priv = dev_get_priv(dev);
 753         struct eth_pdata *pdata = dev_get_platdata(dev);
 754         struct sh_eth_dev *eth = &priv->shdev;
 755         int ret = 0;
 756         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 757         struct phy_device *phydev;
 758         int mask = 0xffffffff;
 759
 760         phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
 761         if (!phydev)
 762                 return -ENODEV;
 763
 764         phy_connect_dev(phydev, dev);
 765
 766         port_info->phydev = phydev;
 767         phy_config(phydev);
 768
 769         return ret;
 770 }
 771
 772 static int sh_ether_start(struct udevice *dev)
 773 {
 774         struct sh_ether_priv *priv = dev_get_priv(dev);
 775         struct eth_pdata *pdata = dev_get_platdata(dev);
 776         struct sh_eth_dev *eth = &priv->shdev;
 777         int ret;
 778
 779         ret = sh_eth_init_common(eth, pdata->enetaddr);
 780         if (ret)
 781                 return ret;
 782
 783         ret = sh_eth_start_common(eth);
 784         if (ret)
 785                 goto err_start;
 786
 787         return 0;
 788
 789 err_start:
 790         sh_eth_tx_desc_free(eth);
 791         sh_eth_rx_desc_free(eth);
 792         return ret;
 793 }
 794
 795 static void sh_ether_stop(struct udevice *dev)
 796 {
 797         struct sh_ether_priv *priv = dev_get_priv(dev);
 798         struct sh_eth_dev *eth = &priv->shdev;
 799         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 800
 801         phy_shutdown(port_info->phydev);
 802         sh_eth_stop(&priv->shdev);
 803 }
 804
 805 static int sh_ether_probe(struct udevice *udev)
 806 {
 807         struct eth_pdata *pdata = dev_get_platdata(udev);
 808         struct sh_ether_priv *priv = dev_get_priv(udev);
 809         struct sh_eth_dev *eth = &priv->shdev;
 810         struct ofnode_phandle_args phandle_args;
 811         struct mii_dev *mdiodev;
 812         int ret;
 813
 814         priv->iobase = pdata->iobase;
 815
 816 #if CONFIG_IS_ENABLED(CLK)
 817         ret = clk_get_by_index(udev, 0, &priv->clk);
 818         if (ret < 0)
 819                 return ret;
 820 #endif
 821
 822         ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
 823         if (!ret) {
 824                 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
 825                                            &priv->reset_gpio, GPIOD_IS_OUT);
 826         }
 827
 828         if (!dm_gpio_is_valid(&priv->reset_gpio)) {
 829                 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
 830                                      GPIOD_IS_OUT);
 831         }
 832
 833         mdiodev = mdio_alloc();
 834         if (!mdiodev) {
 835                 ret = -ENOMEM;
 836                 return ret;
 837         }
 838
 839         mdiodev->read = bb_miiphy_read;
 840         mdiodev->write = bb_miiphy_write;
 841         bb_miiphy_buses[0].priv = eth;
 842         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 843
 844         ret = mdio_register(mdiodev);
 845         if (ret < 0)
 846                 goto err_mdio_register;
 847
 848         priv->bus = miiphy_get_dev_by_name(udev->name);
 849
 850         eth->port = CONFIG_SH_ETHER_USE_PORT;
 851         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 852         eth->port_info[eth->port].iobase =
 853                 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 854
 855 #if CONFIG_IS_ENABLED(CLK)
 856         ret = clk_enable(&priv->clk);
 857         if (ret)
 858                 goto err_mdio_register;
 859 #endif
 860
 861         ret = sh_eth_phy_config(udev);
 862         if (ret) {
 863                 printf(SHETHER_NAME ": phy config timeout\n");
 864                 goto err_phy_config;
 865         }
 866
 867         return 0;
 868
 869 err_phy_config:
 870 #if CONFIG_IS_ENABLED(CLK)
 871         clk_disable(&priv->clk);
 872 #endif
 873 err_mdio_register:
 874         mdio_free(mdiodev);
 875         return ret;
 876 }
 877
 878 static int sh_ether_remove(struct udevice *udev)
 879 {
 880         struct sh_ether_priv *priv = dev_get_priv(udev);
 881         struct sh_eth_dev *eth = &priv->shdev;
 882         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 883
 884 #if CONFIG_IS_ENABLED(CLK)
 885         clk_disable(&priv->clk);
 886 #endif
 887         free(port_info->phydev);
 888         mdio_unregister(priv->bus);
 889         mdio_free(priv->bus);
 890
 891         if (dm_gpio_is_valid(&priv->reset_gpio))
 892                 dm_gpio_free(udev, &priv->reset_gpio);
 893
 894         return 0;
 895 }
 896
 897 static const struct eth_ops sh_ether_ops = {
 898         .start                  = sh_ether_start,
 899         .send                   = sh_ether_send,
 900         .recv                   = sh_ether_recv,
 901         .free_pkt               = sh_ether_free_pkt,
 902         .stop                   = sh_ether_stop,
 903         .write_hwaddr           = sh_ether_write_hwaddr,
 904 };
 905
 906 int sh_ether_ofdata_to_platdata(struct udevice *dev)
 907 {
 908         struct eth_pdata *pdata = dev_get_platdata(dev);
 909         const char *phy_mode;
 910         const fdt32_t *cell;
 911         int ret = 0;
 912
 913         pdata->iobase = devfdt_get_addr(dev);
 914         pdata->phy_interface = -1;
 915         phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 916                                NULL);
 917         if (phy_mode)
 918                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 919         if (pdata->phy_interface == -1) {
 920                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 921                 return -EINVAL;
 922         }
 923
 924         pdata->max_speed = 1000;
 925         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 926         if (cell)
 927                 pdata->max_speed = fdt32_to_cpu(*cell);
 928
 929         sprintf(bb_miiphy_buses[0].name, dev->name);
 930
 931         return ret;
 932 }
 933
 934 static const struct udevice_id sh_ether_ids[] = {
 935         { .compatible = "renesas,ether-r7s72100" },
 936         { .compatible = "renesas,ether-r8a7790" },
 937         { .compatible = "renesas,ether-r8a7791" },
 938         { .compatible = "renesas,ether-r8a7793" },
 939         { .compatible = "renesas,ether-r8a7794" },
 940         { .compatible = "renesas,gether-r8a77980" },
 941         { }
 942 };
 943
 944 U_BOOT_DRIVER(eth_sh_ether) = {
 945         .name           = "sh_ether",
 946         .id             = UCLASS_ETH,
 947         .of_match       = sh_ether_ids,
 948         .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
 949         .probe          = sh_ether_probe,
 950         .remove         = sh_ether_remove,
 951         .ops            = &sh_ether_ops,
 952         .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
 953         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 954         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 955 };
 956 #endif
 957
 958 /******* for bb_miiphy *******/
 959 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 960 {
 961         return 0;
 962 }
 963
 964 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 965 {
 966         struct sh_eth_dev *eth = bus->priv;
 967         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 968
 969         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 970
 971         return 0;
 972 }
 973
 974 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 975 {
 976         struct sh_eth_dev *eth = bus->priv;
 977         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 978
 979         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 980
 981         return 0;
 982 }
 983
 984 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 985 {
 986         struct sh_eth_dev *eth = bus->priv;
 987         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 988
 989         if (v)
 990                 sh_eth_write(port_info,
 991                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 992         else
 993                 sh_eth_write(port_info,
 994                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
 995
 996         return 0;
 997 }
 998
 999 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1000 {
1001         struct sh_eth_dev *eth = bus->priv;
1002         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1003
1004         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1005
1006         return 0;
1007 }
1008
1009 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1010 {
1011         struct sh_eth_dev *eth = bus->priv;
1012         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1013
1014         if (v)
1015                 sh_eth_write(port_info,
1016                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1017         else
1018                 sh_eth_write(port_info,
1019                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1020
1021         return 0;
1022 }
1023
1024 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1025 {
1026         udelay(10);
1027
1028         return 0;
1029 }
1030
1031 struct bb_miiphy_bus bb_miiphy_buses[] = {
1032         {
1033                 .name           = "sh_eth",
1034                 .init           = sh_eth_bb_init,
1035                 .mdio_active    = sh_eth_bb_mdio_active,
1036                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
1037                 .set_mdio       = sh_eth_bb_set_mdio,
1038                 .get_mdio       = sh_eth_bb_get_mdio,
1039                 .set_mdc        = sh_eth_bb_set_mdc,
1040                 .delay          = sh_eth_bb_delay,
1041         }
1042 };
1043
1044 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);