drivers/net/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * sh_eth.c - Driver for Renesas ethernet controller.
   4  *
   5  * Copyright (C) 2008, 2011 Renesas Solutions Corp.
   6  * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
   7  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   8  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   9  */
  10
  11 #include <config.h>
  12 #include <common.h>
  13 #include <cpu_func.h>
  14 #include <env.h>
  15 #include <malloc.h>
  16 #include <net.h>
  17 #include <netdev.h>
  18 #include <miiphy.h>
  19 #include <linux/errno.h>
  20 #include <asm/io.h>
  21
  22 #ifdef CONFIG_DM_ETH
  23 #include <clk.h>
  24 #include <dm.h>
  25 #include <linux/mii.h>
  26 #include <asm/gpio.h>
  27 #endif
  28
  29 #include "sh_eth.h"
  30
  31 #ifndef CONFIG_SH_ETHER_USE_PORT
  32 # error "Please define CONFIG_SH_ETHER_USE_PORT"
  33 #endif
  34 #ifndef CONFIG_SH_ETHER_PHY_ADDR
  35 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  36 #endif
  37
  38 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  39         !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  40 #define flush_cache_wback(addr, len)    \
  41                 flush_dcache_range((unsigned long)addr, \
  42                 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  43 #else
  44 #define flush_cache_wback(...)
  45 #endif
  46
  47 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  48 #define invalidate_cache(addr, len)             \
  49         {       \
  50                 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;  \
  51                 unsigned long start, end;       \
  52                 \
  53                 start = (unsigned long)addr;    \
  54                 end = start + len;              \
  55                 start &= ~(line_size - 1);      \
  56                 end = ((end + line_size - 1) & ~(line_size - 1));       \
  57                 \
  58                 invalidate_dcache_range(start, end);    \
  59         }
  60 #else
  61 #define invalidate_cache(...)
  62 #endif
  63
  64 #define TIMEOUT_CNT 1000
  65
  66 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  67 {
  68         int ret = 0, timeout;
  69         struct sh_eth_info *port_info = &eth->port_info[eth->port];
  70
  71         if (!packet || len > 0xffff) {
  72                 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  73                 ret = -EINVAL;
  74                 goto err;
  75         }
  76
  77         /* packet must be a 4 byte boundary */
  78         if ((uintptr_t)packet & 3) {
  79                 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  80                                 , __func__);
  81                 ret = -EFAULT;
  82                 goto err;
  83         }
  84
  85         /* Update tx descriptor */
  86         flush_cache_wback(packet, len);
  87         port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  88         port_info->tx_desc_cur->td1 = len << 16;
  89         /* Must preserve the end of descriptor list indication */
  90         if (port_info->tx_desc_cur->td0 & TD_TDLE)
  91                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  92         else
  93                 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  94
  95         flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  96
  97         /* Restart the transmitter if disabled */
  98         if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  99                 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
 100
 101         /* Wait until packet is transmitted */
 102         timeout = TIMEOUT_CNT;
 103         do {
 104                 invalidate_cache(port_info->tx_desc_cur,
 105                                  sizeof(struct tx_desc_s));
 106                 udelay(100);
 107         } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
 108
 109         if (timeout < 0) {
 110                 printf(SHETHER_NAME ": transmit timeout\n");
 111                 ret = -ETIMEDOUT;
 112                 goto err;
 113         }
 114
 115         port_info->tx_desc_cur++;
 116         if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
 117                 port_info->tx_desc_cur = port_info->tx_desc_base;
 118
 119 err:
 120         return ret;
 121 }
 122
 123 static int sh_eth_recv_start(struct sh_eth_dev *eth)
 124 {
 125         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 126
 127         /* Check if the rx descriptor is ready */
 128         invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
 129         if (port_info->rx_desc_cur->rd0 & RD_RACT)
 130                 return -EINVAL;
 131
 132         /* Check for errors */
 133         if (port_info->rx_desc_cur->rd0 & RD_RFE)
 134                 return -EINVAL;
 135
 136         return port_info->rx_desc_cur->rd1 & 0xffff;
 137 }
 138
 139 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
 140 {
 141         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 142
 143         /* Make current descriptor available again */
 144         if (port_info->rx_desc_cur->rd0 & RD_RDLE)
 145                 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
 146         else
 147                 port_info->rx_desc_cur->rd0 = RD_RACT;
 148
 149         flush_cache_wback(port_info->rx_desc_cur,
 150                           sizeof(struct rx_desc_s));
 151
 152         /* Point to the next descriptor */
 153         port_info->rx_desc_cur++;
 154         if (port_info->rx_desc_cur >=
 155             port_info->rx_desc_base + NUM_RX_DESC)
 156                 port_info->rx_desc_cur = port_info->rx_desc_base;
 157 }
 158
 159 static int sh_eth_reset(struct sh_eth_dev *eth)
 160 {
 161         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 162 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 163         int ret = 0, i;
 164
 165         /* Start e-dmac transmitter and receiver */
 166         sh_eth_write(port_info, EDSR_ENALL, EDSR);
 167
 168         /* Perform a software reset and wait for it to complete */
 169         sh_eth_write(port_info, EDMR_SRST, EDMR);
 170         for (i = 0; i < TIMEOUT_CNT; i++) {
 171                 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
 172                         break;
 173                 udelay(1000);
 174         }
 175
 176         if (i == TIMEOUT_CNT) {
 177                 printf(SHETHER_NAME  ": Software reset timeout\n");
 178                 ret = -EIO;
 179         }
 180
 181         return ret;
 182 #else
 183         sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
 184         mdelay(3);
 185         sh_eth_write(port_info,
 186                      sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
 187
 188         return 0;
 189 #endif
 190 }
 191
 192 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 193 {
 194         int i, ret = 0;
 195         u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
 196         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 197         struct tx_desc_s *cur_tx_desc;
 198
 199         /*
 200          * Allocate rx descriptors. They must be aligned to size of struct
 201          * tx_desc_s.
 202          */
 203         port_info->tx_desc_alloc =
 204                 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
 205         if (!port_info->tx_desc_alloc) {
 206                 printf(SHETHER_NAME ": memalign failed\n");
 207                 ret = -ENOMEM;
 208                 goto err;
 209         }
 210
 211         flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
 212
 213         /* Make sure we use a P2 address (non-cacheable) */
 214         port_info->tx_desc_base =
 215                 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
 216         port_info->tx_desc_cur = port_info->tx_desc_base;
 217
 218         /* Initialize all descriptors */
 219         for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
 220              cur_tx_desc++, i++) {
 221                 cur_tx_desc->td0 = 0x00;
 222                 cur_tx_desc->td1 = 0x00;
 223                 cur_tx_desc->td2 = 0x00;
 224         }
 225
 226         /* Mark the end of the descriptors */
 227         cur_tx_desc--;
 228         cur_tx_desc->td0 |= TD_TDLE;
 229
 230         /*
 231          * Point the controller to the tx descriptor list. Must use physical
 232          * addresses
 233          */
 234         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
 235 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 236         sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
 237         sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
 238         sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
 239 #endif
 240
 241 err:
 242         return ret;
 243 }
 244
 245 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 246 {
 247         int i, ret = 0;
 248         u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
 249         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 250         struct rx_desc_s *cur_rx_desc;
 251         u8 *rx_buf;
 252
 253         /*
 254          * Allocate rx descriptors. They must be aligned to size of struct
 255          * rx_desc_s.
 256          */
 257         port_info->rx_desc_alloc =
 258                 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
 259         if (!port_info->rx_desc_alloc) {
 260                 printf(SHETHER_NAME ": memalign failed\n");
 261                 ret = -ENOMEM;
 262                 goto err;
 263         }
 264
 265         flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
 266
 267         /* Make sure we use a P2 address (non-cacheable) */
 268         port_info->rx_desc_base =
 269                 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 270
 271         port_info->rx_desc_cur = port_info->rx_desc_base;
 272
 273         /*
 274          * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
 275          * aligned and in P2 area.
 276          */
 277         port_info->rx_buf_alloc =
 278                 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
 279         if (!port_info->rx_buf_alloc) {
 280                 printf(SHETHER_NAME ": alloc failed\n");
 281                 ret = -ENOMEM;
 282                 goto err_buf_alloc;
 283         }
 284
 285         port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 286
 287         /* Initialize all descriptors */
 288         for (cur_rx_desc = port_info->rx_desc_base,
 289              rx_buf = port_info->rx_buf_base, i = 0;
 290              i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
 291                 cur_rx_desc->rd0 = RD_RACT;
 292                 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
 293                 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
 294         }
 295
 296         /* Mark the end of the descriptors */
 297         cur_rx_desc--;
 298         cur_rx_desc->rd0 |= RD_RDLE;
 299
 300         /* Point the controller to the rx descriptor list */
 301         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
 302 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 303         sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
 304         sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
 305         sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
 306 #endif
 307
 308         return ret;
 309
 310 err_buf_alloc:
 311         free(port_info->rx_desc_alloc);
 312         port_info->rx_desc_alloc = NULL;
 313
 314 err:
 315         return ret;
 316 }
 317
 318 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
 319 {
 320         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 321
 322         if (port_info->tx_desc_alloc) {
 323                 free(port_info->tx_desc_alloc);
 324                 port_info->tx_desc_alloc = NULL;
 325         }
 326 }
 327
 328 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
 329 {
 330         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 331
 332         if (port_info->rx_desc_alloc) {
 333                 free(port_info->rx_desc_alloc);
 334                 port_info->rx_desc_alloc = NULL;
 335         }
 336
 337         if (port_info->rx_buf_alloc) {
 338                 free(port_info->rx_buf_alloc);
 339                 port_info->rx_buf_alloc = NULL;
 340         }
 341 }
 342
 343 static int sh_eth_desc_init(struct sh_eth_dev *eth)
 344 {
 345         int ret = 0;
 346
 347         ret = sh_eth_tx_desc_init(eth);
 348         if (ret)
 349                 goto err_tx_init;
 350
 351         ret = sh_eth_rx_desc_init(eth);
 352         if (ret)
 353                 goto err_rx_init;
 354
 355         return ret;
 356 err_rx_init:
 357         sh_eth_tx_desc_free(eth);
 358
 359 err_tx_init:
 360         return ret;
 361 }
 362
 363 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
 364                                 unsigned char *mac)
 365 {
 366         u32 val;
 367
 368         val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
 369         sh_eth_write(port_info, val, MAHR);
 370
 371         val = (mac[4] << 8) | mac[5];
 372         sh_eth_write(port_info, val, MALR);
 373 }
 374
 375 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 376 {
 377         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 378         unsigned long edmr;
 379
 380         /* Configure e-dmac registers */
 381         edmr = sh_eth_read(port_info, EDMR);
 382         edmr &= ~EMDR_DESC_R;
 383         edmr |= EMDR_DESC | EDMR_EL;
 384 #if defined(CONFIG_R8A77980)
 385         edmr |= EDMR_NBST;
 386 #endif
 387         sh_eth_write(port_info, edmr, EDMR);
 388
 389         sh_eth_write(port_info, 0, EESIPR);
 390         sh_eth_write(port_info, 0, TRSCER);
 391         sh_eth_write(port_info, 0, TFTR);
 392         sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
 393         sh_eth_write(port_info, RMCR_RST, RMCR);
 394 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 395         sh_eth_write(port_info, 0, RPADIR);
 396 #endif
 397         sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
 398
 399         /* Configure e-mac registers */
 400         sh_eth_write(port_info, 0, ECSIPR);
 401
 402         /* Set Mac address */
 403         sh_eth_write_hwaddr(port_info, mac);
 404
 405         sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
 406 #if defined(SH_ETH_TYPE_GETHER)
 407         sh_eth_write(port_info, 0, PIPR);
 408 #endif
 409 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 410         sh_eth_write(port_info, APR_AP, APR);
 411         sh_eth_write(port_info, MPR_MP, MPR);
 412         sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
 413 #endif
 414
 415 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
 416         sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
 417 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 418         sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 419 #endif
 420 }
 421
 422 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
 423 {
 424         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 425         struct phy_device *phy = port_info->phydev;
 426         int ret = 0;
 427         u32 val = 0;
 428
 429         /* Set the transfer speed */
 430         if (phy->speed == 100) {
 431                 printf(SHETHER_NAME ": 100Base/");
 432 #if defined(SH_ETH_TYPE_GETHER)
 433                 sh_eth_write(port_info, GECMR_100B, GECMR);
 434 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 435                 sh_eth_write(port_info, 1, RTRATE);
 436 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
 437                 val = ECMR_RTM;
 438 #endif
 439         } else if (phy->speed == 10) {
 440                 printf(SHETHER_NAME ": 10Base/");
 441 #if defined(SH_ETH_TYPE_GETHER)
 442                 sh_eth_write(port_info, GECMR_10B, GECMR);
 443 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
 444                 sh_eth_write(port_info, 0, RTRATE);
 445 #endif
 446         }
 447 #if defined(SH_ETH_TYPE_GETHER)
 448         else if (phy->speed == 1000) {
 449                 printf(SHETHER_NAME ": 1000Base/");
 450                 sh_eth_write(port_info, GECMR_1000B, GECMR);
 451         }
 452 #endif
 453
 454         /* Check if full duplex mode is supported by the phy */
 455         if (phy->duplex) {
 456                 printf("Full\n");
 457                 sh_eth_write(port_info,
 458                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
 459                              ECMR);
 460         } else {
 461                 printf("Half\n");
 462                 sh_eth_write(port_info,
 463                              val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
 464                              ECMR);
 465         }
 466
 467         return ret;
 468 }
 469
 470 static void sh_eth_start(struct sh_eth_dev *eth)
 471 {
 472         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 473
 474         /*
 475          * Enable the e-dmac receiver only. The transmitter will be enabled when
 476          * we have something to transmit
 477          */
 478         sh_eth_write(port_info, EDRRR_R, EDRRR);
 479 }
 480
 481 static void sh_eth_stop(struct sh_eth_dev *eth)
 482 {
 483         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 484
 485         sh_eth_write(port_info, ~EDRRR_R, EDRRR);
 486 }
 487
 488 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
 489 {
 490         int ret = 0;
 491
 492         ret = sh_eth_reset(eth);
 493         if (ret)
 494                 return ret;
 495
 496         ret = sh_eth_desc_init(eth);
 497         if (ret)
 498                 return ret;
 499
 500         sh_eth_mac_regs_config(eth, mac);
 501
 502         return 0;
 503 }
 504
 505 static int sh_eth_start_common(struct sh_eth_dev *eth)
 506 {
 507         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 508         int ret;
 509
 510         ret = phy_startup(port_info->phydev);
 511         if (ret) {
 512                 printf(SHETHER_NAME ": phy startup failure\n");
 513                 return ret;
 514         }
 515
 516         ret = sh_eth_phy_regs_config(eth);
 517         if (ret)
 518                 return ret;
 519
 520         sh_eth_start(eth);
 521
 522         return 0;
 523 }
 524
 525 #ifndef CONFIG_DM_ETH
 526 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
 527 {
 528         int ret = 0;
 529         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 530         struct eth_device *dev = port_info->dev;
 531         struct phy_device *phydev;
 532
 533         phydev = phy_connect(
 534                         miiphy_get_dev_by_name(dev->name),
 535                         port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
 536         port_info->phydev = phydev;
 537         phy_config(phydev);
 538
 539         return ret;
 540 }
 541
 542 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
 543 {
 544         struct sh_eth_dev *eth = dev->priv;
 545
 546         return sh_eth_send_common(eth, packet, len);
 547 }
 548
 549 static int sh_eth_recv_common(struct sh_eth_dev *eth)
 550 {
 551         int len = 0;
 552         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 553         uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
 554
 555         len = sh_eth_recv_start(eth);
 556         if (len > 0) {
 557                 invalidate_cache(packet, len);
 558                 net_process_received_packet(packet, len);
 559                 sh_eth_recv_finish(eth);
 560         } else
 561                 len = 0;
 562
 563         /* Restart the receiver if disabled */
 564         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 565                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 566
 567         return len;
 568 }
 569
 570 static int sh_eth_recv_legacy(struct eth_device *dev)
 571 {
 572         struct sh_eth_dev *eth = dev->priv;
 573
 574         return sh_eth_recv_common(eth);
 575 }
 576
 577 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
 578 {
 579         struct sh_eth_dev *eth = dev->priv;
 580         int ret;
 581
 582         ret = sh_eth_init_common(eth, dev->enetaddr);
 583         if (ret)
 584                 return ret;
 585
 586         ret = sh_eth_phy_config_legacy(eth);
 587         if (ret) {
 588                 printf(SHETHER_NAME ": phy config timeout\n");
 589                 goto err_start;
 590         }
 591
 592         ret = sh_eth_start_common(eth);
 593         if (ret)
 594                 goto err_start;
 595
 596         return 0;
 597
 598 err_start:
 599         sh_eth_tx_desc_free(eth);
 600         sh_eth_rx_desc_free(eth);
 601         return ret;
 602 }
 603
 604 void sh_eth_halt_legacy(struct eth_device *dev)
 605 {
 606         struct sh_eth_dev *eth = dev->priv;
 607
 608         sh_eth_stop(eth);
 609 }
 610
 611 int sh_eth_initialize(bd_t *bd)
 612 {
 613         int ret = 0;
 614         struct sh_eth_dev *eth = NULL;
 615         struct eth_device *dev = NULL;
 616         struct mii_dev *mdiodev;
 617
 618         eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
 619         if (!eth) {
 620                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 621                 ret = -ENOMEM;
 622                 goto err;
 623         }
 624
 625         dev = (struct eth_device *)malloc(sizeof(struct eth_device));
 626         if (!dev) {
 627                 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
 628                 ret = -ENOMEM;
 629                 goto err;
 630         }
 631         memset(dev, 0, sizeof(struct eth_device));
 632         memset(eth, 0, sizeof(struct sh_eth_dev));
 633
 634         eth->port = CONFIG_SH_ETHER_USE_PORT;
 635         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 636         eth->port_info[eth->port].iobase =
 637                 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
 638
 639         dev->priv = (void *)eth;
 640         dev->iobase = 0;
 641         dev->init = sh_eth_init_legacy;
 642         dev->halt = sh_eth_halt_legacy;
 643         dev->send = sh_eth_send_legacy;
 644         dev->recv = sh_eth_recv_legacy;
 645         eth->port_info[eth->port].dev = dev;
 646
 647         strcpy(dev->name, SHETHER_NAME);
 648
 649         /* Register Device to EtherNet subsystem  */
 650         eth_register(dev);
 651
 652         bb_miiphy_buses[0].priv = eth;
 653         mdiodev = mdio_alloc();
 654         if (!mdiodev)
 655                 return -ENOMEM;
 656         strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
 657         mdiodev->read = bb_miiphy_read;
 658         mdiodev->write = bb_miiphy_write;
 659
 660         ret = mdio_register(mdiodev);
 661         if (ret < 0)
 662                 return ret;
 663
 664         if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
 665                 puts("Please set MAC address\n");
 666
 667         return ret;
 668
 669 err:
 670         if (dev)
 671                 free(dev);
 672
 673         if (eth)
 674                 free(eth);
 675
 676         printf(SHETHER_NAME ": Failed\n");
 677         return ret;
 678 }
 679
 680 #else /* CONFIG_DM_ETH */
 681
 682 struct sh_ether_priv {
 683         struct sh_eth_dev       shdev;
 684
 685         struct mii_dev          *bus;
 686         phys_addr_t             iobase;
 687         struct clk              clk;
 688         struct gpio_desc        reset_gpio;
 689 };
 690
 691 static int sh_ether_send(struct udevice *dev, void *packet, int len)
 692 {
 693         struct sh_ether_priv *priv = dev_get_priv(dev);
 694         struct sh_eth_dev *eth = &priv->shdev;
 695
 696         return sh_eth_send_common(eth, packet, len);
 697 }
 698
 699 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
 700 {
 701         struct sh_ether_priv *priv = dev_get_priv(dev);
 702         struct sh_eth_dev *eth = &priv->shdev;
 703         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 704         uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
 705         int len;
 706
 707         len = sh_eth_recv_start(eth);
 708         if (len > 0) {
 709                 invalidate_cache(packet, len);
 710                 *packetp = packet;
 711
 712                 return len;
 713         } else {
 714                 len = 0;
 715
 716                 /* Restart the receiver if disabled */
 717                 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 718                         sh_eth_write(port_info, EDRRR_R, EDRRR);
 719
 720                 return -EAGAIN;
 721         }
 722 }
 723
 724 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
 725 {
 726         struct sh_ether_priv *priv = dev_get_priv(dev);
 727         struct sh_eth_dev *eth = &priv->shdev;
 728         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 729
 730         sh_eth_recv_finish(eth);
 731
 732         /* Restart the receiver if disabled */
 733         if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
 734                 sh_eth_write(port_info, EDRRR_R, EDRRR);
 735
 736         return 0;
 737 }
 738
 739 static int sh_ether_write_hwaddr(struct udevice *dev)
 740 {
 741         struct sh_ether_priv *priv = dev_get_priv(dev);
 742         struct sh_eth_dev *eth = &priv->shdev;
 743         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 744         struct eth_pdata *pdata = dev_get_platdata(dev);
 745
 746         sh_eth_write_hwaddr(port_info, pdata->enetaddr);
 747
 748         return 0;
 749 }
 750
 751 static int sh_eth_phy_config(struct udevice *dev)
 752 {
 753         struct sh_ether_priv *priv = dev_get_priv(dev);
 754         struct eth_pdata *pdata = dev_get_platdata(dev);
 755         struct sh_eth_dev *eth = &priv->shdev;
 756         int ret = 0;
 757         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 758         struct phy_device *phydev;
 759         int mask = 0xffffffff;
 760
 761         phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
 762         if (!phydev)
 763                 return -ENODEV;
 764
 765         phy_connect_dev(phydev, dev);
 766
 767         port_info->phydev = phydev;
 768         phy_config(phydev);
 769
 770         return ret;
 771 }
 772
 773 static int sh_ether_start(struct udevice *dev)
 774 {
 775         struct sh_ether_priv *priv = dev_get_priv(dev);
 776         struct eth_pdata *pdata = dev_get_platdata(dev);
 777         struct sh_eth_dev *eth = &priv->shdev;
 778         int ret;
 779
 780         ret = sh_eth_init_common(eth, pdata->enetaddr);
 781         if (ret)
 782                 return ret;
 783
 784         ret = sh_eth_start_common(eth);
 785         if (ret)
 786                 goto err_start;
 787
 788         return 0;
 789
 790 err_start:
 791         sh_eth_tx_desc_free(eth);
 792         sh_eth_rx_desc_free(eth);
 793         return ret;
 794 }
 795
 796 static void sh_ether_stop(struct udevice *dev)
 797 {
 798         struct sh_ether_priv *priv = dev_get_priv(dev);
 799         struct sh_eth_dev *eth = &priv->shdev;
 800         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 801
 802         phy_shutdown(port_info->phydev);
 803         sh_eth_stop(&priv->shdev);
 804 }
 805
 806 static int sh_ether_probe(struct udevice *udev)
 807 {
 808         struct eth_pdata *pdata = dev_get_platdata(udev);
 809         struct sh_ether_priv *priv = dev_get_priv(udev);
 810         struct sh_eth_dev *eth = &priv->shdev;
 811         struct ofnode_phandle_args phandle_args;
 812         struct mii_dev *mdiodev;
 813         int ret;
 814
 815         priv->iobase = pdata->iobase;
 816
 817 #if CONFIG_IS_ENABLED(CLK)
 818         ret = clk_get_by_index(udev, 0, &priv->clk);
 819         if (ret < 0)
 820                 return ret;
 821 #endif
 822
 823         ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
 824         if (!ret) {
 825                 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
 826                                            &priv->reset_gpio, GPIOD_IS_OUT);
 827         }
 828
 829         if (!dm_gpio_is_valid(&priv->reset_gpio)) {
 830                 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
 831                                      GPIOD_IS_OUT);
 832         }
 833
 834         mdiodev = mdio_alloc();
 835         if (!mdiodev) {
 836                 ret = -ENOMEM;
 837                 return ret;
 838         }
 839
 840         mdiodev->read = bb_miiphy_read;
 841         mdiodev->write = bb_miiphy_write;
 842         bb_miiphy_buses[0].priv = eth;
 843         snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
 844
 845         ret = mdio_register(mdiodev);
 846         if (ret < 0)
 847                 goto err_mdio_register;
 848
 849         priv->bus = miiphy_get_dev_by_name(udev->name);
 850
 851         eth->port = CONFIG_SH_ETHER_USE_PORT;
 852         eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
 853         eth->port_info[eth->port].iobase =
 854                 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 855
 856 #if CONFIG_IS_ENABLED(CLK)
 857         ret = clk_enable(&priv->clk);
 858         if (ret)
 859                 goto err_mdio_register;
 860 #endif
 861
 862         ret = sh_eth_init_common(eth, pdata->enetaddr);
 863         if (ret)
 864                 goto err_phy_config;
 865
 866         ret = sh_eth_phy_config(udev);
 867         if (ret) {
 868                 printf(SHETHER_NAME ": phy config timeout\n");
 869                 goto err_phy_config;
 870         }
 871
 872         return 0;
 873
 874 err_phy_config:
 875 #if CONFIG_IS_ENABLED(CLK)
 876         clk_disable(&priv->clk);
 877 #endif
 878 err_mdio_register:
 879         mdio_free(mdiodev);
 880         return ret;
 881 }
 882
 883 static int sh_ether_remove(struct udevice *udev)
 884 {
 885         struct sh_ether_priv *priv = dev_get_priv(udev);
 886         struct sh_eth_dev *eth = &priv->shdev;
 887         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 888
 889 #if CONFIG_IS_ENABLED(CLK)
 890         clk_disable(&priv->clk);
 891 #endif
 892         free(port_info->phydev);
 893         mdio_unregister(priv->bus);
 894         mdio_free(priv->bus);
 895
 896         if (dm_gpio_is_valid(&priv->reset_gpio))
 897                 dm_gpio_free(udev, &priv->reset_gpio);
 898
 899         return 0;
 900 }
 901
 902 static const struct eth_ops sh_ether_ops = {
 903         .start                  = sh_ether_start,
 904         .send                   = sh_ether_send,
 905         .recv                   = sh_ether_recv,
 906         .free_pkt               = sh_ether_free_pkt,
 907         .stop                   = sh_ether_stop,
 908         .write_hwaddr           = sh_ether_write_hwaddr,
 909 };
 910
 911 int sh_ether_ofdata_to_platdata(struct udevice *dev)
 912 {
 913         struct eth_pdata *pdata = dev_get_platdata(dev);
 914         const char *phy_mode;
 915         const fdt32_t *cell;
 916         int ret = 0;
 917
 918         pdata->iobase = devfdt_get_addr(dev);
 919         pdata->phy_interface = -1;
 920         phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 921                                NULL);
 922         if (phy_mode)
 923                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 924         if (pdata->phy_interface == -1) {
 925                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 926                 return -EINVAL;
 927         }
 928
 929         pdata->max_speed = 1000;
 930         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
 931         if (cell)
 932                 pdata->max_speed = fdt32_to_cpu(*cell);
 933
 934         sprintf(bb_miiphy_buses[0].name, dev->name);
 935
 936         return ret;
 937 }
 938
 939 static const struct udevice_id sh_ether_ids[] = {
 940         { .compatible = "renesas,ether-r7s72100" },
 941         { .compatible = "renesas,ether-r8a7790" },
 942         { .compatible = "renesas,ether-r8a7791" },
 943         { .compatible = "renesas,ether-r8a7793" },
 944         { .compatible = "renesas,ether-r8a7794" },
 945         { .compatible = "renesas,gether-r8a77980" },
 946         { }
 947 };
 948
 949 U_BOOT_DRIVER(eth_sh_ether) = {
 950         .name           = "sh_ether",
 951         .id             = UCLASS_ETH,
 952         .of_match       = sh_ether_ids,
 953         .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
 954         .probe          = sh_ether_probe,
 955         .remove         = sh_ether_remove,
 956         .ops            = &sh_ether_ops,
 957         .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
 958         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 959         .flags          = DM_FLAG_ALLOC_PRIV_DMA,
 960 };
 961 #endif
 962
 963 /******* for bb_miiphy *******/
 964 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 965 {
 966         return 0;
 967 }
 968
 969 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 970 {
 971         struct sh_eth_dev *eth = bus->priv;
 972         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 973
 974         sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
 975
 976         return 0;
 977 }
 978
 979 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 980 {
 981         struct sh_eth_dev *eth = bus->priv;
 982         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 983
 984         sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
 985
 986         return 0;
 987 }
 988
 989 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 990 {
 991         struct sh_eth_dev *eth = bus->priv;
 992         struct sh_eth_info *port_info = &eth->port_info[eth->port];
 993
 994         if (v)
 995                 sh_eth_write(port_info,
 996                              sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
 997         else
 998                 sh_eth_write(port_info,
 999                              sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
1000
1001         return 0;
1002 }
1003
1004 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1005 {
1006         struct sh_eth_dev *eth = bus->priv;
1007         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1008
1009         *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1010
1011         return 0;
1012 }
1013
1014 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1015 {
1016         struct sh_eth_dev *eth = bus->priv;
1017         struct sh_eth_info *port_info = &eth->port_info[eth->port];
1018
1019         if (v)
1020                 sh_eth_write(port_info,
1021                              sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1022         else
1023                 sh_eth_write(port_info,
1024                              sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1025
1026         return 0;
1027 }
1028
1029 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1030 {
1031         udelay(10);
1032
1033         return 0;
1034 }
1035
1036 struct bb_miiphy_bus bb_miiphy_buses[] = {
1037         {
1038                 .name           = "sh_eth",
1039                 .init           = sh_eth_bb_init,
1040                 .mdio_active    = sh_eth_bb_mdio_active,
1041                 .mdio_tristate  = sh_eth_bb_mdio_tristate,
1042                 .set_mdio       = sh_eth_bb_set_mdio,
1043                 .get_mdio       = sh_eth_bb_get_mdio,
1044                 .set_mdc        = sh_eth_bb_set_mdc,
1045                 .delay          = sh_eth_bb_delay,
1046         }
1047 };
1048
1049 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);