2 * sh_eth.c - Driver for Renesas ethernet controller.
4 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
5 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
6 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
7 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/errno.h>
23 #ifndef CONFIG_SH_ETHER_USE_PORT
24 # error "Please define CONFIG_SH_ETHER_USE_PORT"
26 #ifndef CONFIG_SH_ETHER_PHY_ADDR
27 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
30 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
31 #define flush_cache_wback(addr, len) \
32 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
34 #define flush_cache_wback(...)
37 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
38 #define invalidate_cache(addr, len) \
40 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
45 start &= ~(line_size - 1); \
46 end = ((end + line_size - 1) & ~(line_size - 1)); \
48 invalidate_dcache_range(start, end); \
51 #define invalidate_cache(...)
54 #define TIMEOUT_CNT 1000
56 int sh_eth_send(struct eth_device *dev, void *packet, int len)
58 struct sh_eth_dev *eth = dev->priv;
59 int port = eth->port, ret = 0, timeout;
60 struct sh_eth_info *port_info = ð->port_info[port];
62 if (!packet || len > 0xffff) {
63 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
68 /* packet must be a 4 byte boundary */
69 if ((int)packet & 3) {
70 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
76 /* Update tx descriptor */
77 flush_cache_wback(packet, len);
78 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
79 port_info->tx_desc_cur->td1 = len << 16;
80 /* Must preserve the end of descriptor list indication */
81 if (port_info->tx_desc_cur->td0 & TD_TDLE)
82 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
84 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
86 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
88 /* Restart the transmitter if disabled */
89 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
90 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
92 /* Wait until packet is transmitted */
93 timeout = TIMEOUT_CNT;
95 invalidate_cache(port_info->tx_desc_cur,
96 sizeof(struct tx_desc_s));
98 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
101 printf(SHETHER_NAME ": transmit timeout\n");
106 port_info->tx_desc_cur++;
107 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
108 port_info->tx_desc_cur = port_info->tx_desc_base;
114 int sh_eth_recv(struct eth_device *dev)
116 struct sh_eth_dev *eth = dev->priv;
117 int port = eth->port, len = 0;
118 struct sh_eth_info *port_info = ð->port_info[port];
121 /* Check if the rx descriptor is ready */
122 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
123 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
124 /* Check for errors */
125 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
126 len = port_info->rx_desc_cur->rd1 & 0xffff;
128 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
129 invalidate_cache(packet, len);
130 net_process_received_packet(packet, len);
133 /* Make current descriptor available again */
134 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
135 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
137 port_info->rx_desc_cur->rd0 = RD_RACT;
139 flush_cache_wback(port_info->rx_desc_cur,
140 sizeof(struct rx_desc_s));
142 /* Point to the next descriptor */
143 port_info->rx_desc_cur++;
144 if (port_info->rx_desc_cur >=
145 port_info->rx_desc_base + NUM_RX_DESC)
146 port_info->rx_desc_cur = port_info->rx_desc_base;
149 /* Restart the receiver if disabled */
150 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
151 sh_eth_write(port_info, EDRRR_R, EDRRR);
156 static int sh_eth_reset(struct sh_eth_dev *eth)
158 struct sh_eth_info *port_info = ð->port_info[eth->port];
159 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
162 /* Start e-dmac transmitter and receiver */
163 sh_eth_write(port_info, EDSR_ENALL, EDSR);
165 /* Perform a software reset and wait for it to complete */
166 sh_eth_write(port_info, EDMR_SRST, EDMR);
167 for (i = 0; i < TIMEOUT_CNT; i++) {
168 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
173 if (i == TIMEOUT_CNT) {
174 printf(SHETHER_NAME ": Software reset timeout\n");
180 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
182 sh_eth_write(port_info,
183 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
189 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
191 int port = eth->port, i, ret = 0;
192 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
193 struct sh_eth_info *port_info = ð->port_info[port];
194 struct tx_desc_s *cur_tx_desc;
197 * Allocate rx descriptors. They must be aligned to size of struct
200 port_info->tx_desc_alloc =
201 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
202 if (!port_info->tx_desc_alloc) {
203 printf(SHETHER_NAME ": memalign failed\n");
208 flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
210 /* Make sure we use a P2 address (non-cacheable) */
211 port_info->tx_desc_base =
212 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
213 port_info->tx_desc_cur = port_info->tx_desc_base;
215 /* Initialize all descriptors */
216 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
217 cur_tx_desc++, i++) {
218 cur_tx_desc->td0 = 0x00;
219 cur_tx_desc->td1 = 0x00;
220 cur_tx_desc->td2 = 0x00;
223 /* Mark the end of the descriptors */
225 cur_tx_desc->td0 |= TD_TDLE;
228 * Point the controller to the tx descriptor list. Must use physical
231 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
232 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
233 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
234 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
235 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
242 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
244 int port = eth->port, i, ret = 0;
245 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
246 struct sh_eth_info *port_info = ð->port_info[port];
247 struct rx_desc_s *cur_rx_desc;
251 * Allocate rx descriptors. They must be aligned to size of struct
254 port_info->rx_desc_alloc =
255 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
256 if (!port_info->rx_desc_alloc) {
257 printf(SHETHER_NAME ": memalign failed\n");
262 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
264 /* Make sure we use a P2 address (non-cacheable) */
265 port_info->rx_desc_base =
266 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
268 port_info->rx_desc_cur = port_info->rx_desc_base;
271 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
272 * aligned and in P2 area.
274 port_info->rx_buf_alloc =
275 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
276 if (!port_info->rx_buf_alloc) {
277 printf(SHETHER_NAME ": alloc failed\n");
282 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
284 /* Initialize all descriptors */
285 for (cur_rx_desc = port_info->rx_desc_base,
286 rx_buf = port_info->rx_buf_base, i = 0;
287 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
288 cur_rx_desc->rd0 = RD_RACT;
289 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
290 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
293 /* Mark the end of the descriptors */
295 cur_rx_desc->rd0 |= RD_RDLE;
297 /* Point the controller to the rx descriptor list */
298 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
299 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
300 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
301 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
302 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
308 free(port_info->rx_desc_alloc);
309 port_info->rx_desc_alloc = NULL;
315 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
317 int port = eth->port;
318 struct sh_eth_info *port_info = ð->port_info[port];
320 if (port_info->tx_desc_alloc) {
321 free(port_info->tx_desc_alloc);
322 port_info->tx_desc_alloc = NULL;
326 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
328 int port = eth->port;
329 struct sh_eth_info *port_info = ð->port_info[port];
331 if (port_info->rx_desc_alloc) {
332 free(port_info->rx_desc_alloc);
333 port_info->rx_desc_alloc = NULL;
336 if (port_info->rx_buf_alloc) {
337 free(port_info->rx_buf_alloc);
338 port_info->rx_buf_alloc = NULL;
342 static int sh_eth_desc_init(struct sh_eth_dev *eth)
346 ret = sh_eth_tx_desc_init(eth);
350 ret = sh_eth_rx_desc_init(eth);
356 sh_eth_tx_desc_free(eth);
362 static int sh_eth_phy_config(struct sh_eth_dev *eth)
364 int port = eth->port, ret = 0;
365 struct sh_eth_info *port_info = ð->port_info[port];
366 struct eth_device *dev = port_info->dev;
367 struct phy_device *phydev;
369 phydev = phy_connect(
370 miiphy_get_dev_by_name(dev->name),
371 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
372 port_info->phydev = phydev;
378 static int sh_eth_config(struct sh_eth_dev *eth)
380 int port = eth->port, ret = 0;
382 struct sh_eth_info *port_info = ð->port_info[port];
383 struct eth_device *dev = port_info->dev;
384 struct phy_device *phy;
386 /* Configure e-dmac registers */
387 sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
388 (EMDR_DESC | EDMR_EL), EDMR);
390 sh_eth_write(port_info, 0, EESIPR);
391 sh_eth_write(port_info, 0, TRSCER);
392 sh_eth_write(port_info, 0, TFTR);
393 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
394 sh_eth_write(port_info, RMCR_RST, RMCR);
395 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
396 sh_eth_write(port_info, 0, RPADIR);
398 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
400 /* Configure e-mac registers */
401 sh_eth_write(port_info, 0, ECSIPR);
403 /* Set Mac address */
404 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
405 dev->enetaddr[2] << 8 | dev->enetaddr[3];
406 sh_eth_write(port_info, val, MAHR);
408 val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
409 sh_eth_write(port_info, val, MALR);
411 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
412 #if defined(SH_ETH_TYPE_GETHER)
413 sh_eth_write(port_info, 0, PIPR);
415 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
416 sh_eth_write(port_info, APR_AP, APR);
417 sh_eth_write(port_info, MPR_MP, MPR);
418 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
421 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
422 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
423 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
424 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
425 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
428 ret = sh_eth_phy_config(eth);
430 printf(SHETHER_NAME ": phy config timeout\n");
433 phy = port_info->phydev;
434 ret = phy_startup(phy);
436 printf(SHETHER_NAME ": phy startup failure\n");
442 /* Set the transfer speed */
443 if (phy->speed == 100) {
444 printf(SHETHER_NAME ": 100Base/");
445 #if defined(SH_ETH_TYPE_GETHER)
446 sh_eth_write(port_info, GECMR_100B, GECMR);
447 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
448 sh_eth_write(port_info, 1, RTRATE);
449 #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
450 defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
451 defined(CONFIG_R8A7794)
454 } else if (phy->speed == 10) {
455 printf(SHETHER_NAME ": 10Base/");
456 #if defined(SH_ETH_TYPE_GETHER)
457 sh_eth_write(port_info, GECMR_10B, GECMR);
458 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
459 sh_eth_write(port_info, 0, RTRATE);
462 #if defined(SH_ETH_TYPE_GETHER)
463 else if (phy->speed == 1000) {
464 printf(SHETHER_NAME ": 1000Base/");
465 sh_eth_write(port_info, GECMR_1000B, GECMR);
469 /* Check if full duplex mode is supported by the phy */
472 sh_eth_write(port_info,
473 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
477 sh_eth_write(port_info,
478 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
488 static void sh_eth_start(struct sh_eth_dev *eth)
490 struct sh_eth_info *port_info = ð->port_info[eth->port];
493 * Enable the e-dmac receiver only. The transmitter will be enabled when
494 * we have something to transmit
496 sh_eth_write(port_info, EDRRR_R, EDRRR);
499 static void sh_eth_stop(struct sh_eth_dev *eth)
501 struct sh_eth_info *port_info = ð->port_info[eth->port];
503 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
506 int sh_eth_init(struct eth_device *dev, bd_t *bd)
509 struct sh_eth_dev *eth = dev->priv;
511 ret = sh_eth_reset(eth);
515 ret = sh_eth_desc_init(eth);
519 ret = sh_eth_config(eth);
528 sh_eth_tx_desc_free(eth);
529 sh_eth_rx_desc_free(eth);
535 void sh_eth_halt(struct eth_device *dev)
537 struct sh_eth_dev *eth = dev->priv;
542 int sh_eth_initialize(bd_t *bd)
545 struct sh_eth_dev *eth = NULL;
546 struct eth_device *dev = NULL;
547 struct mii_dev *mdiodev;
549 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
551 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
556 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
558 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
562 memset(dev, 0, sizeof(struct eth_device));
563 memset(eth, 0, sizeof(struct sh_eth_dev));
565 eth->port = CONFIG_SH_ETHER_USE_PORT;
566 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
567 eth->port_info[eth->port].iobase =
568 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
570 dev->priv = (void *)eth;
572 dev->init = sh_eth_init;
573 dev->halt = sh_eth_halt;
574 dev->send = sh_eth_send;
575 dev->recv = sh_eth_recv;
576 eth->port_info[eth->port].dev = dev;
578 strcpy(dev->name, SHETHER_NAME);
580 /* Register Device to EtherNet subsystem */
583 bb_miiphy_buses[0].priv = eth;
584 mdiodev = mdio_alloc();
587 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
588 mdiodev->read = bb_miiphy_read;
589 mdiodev->write = bb_miiphy_write;
591 ret = mdio_register(mdiodev);
595 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
596 puts("Please set MAC address\n");
607 printf(SHETHER_NAME ": Failed\n");
611 /******* for bb_miiphy *******/
612 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
617 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
619 struct sh_eth_dev *eth = bus->priv;
620 struct sh_eth_info *port_info = ð->port_info[eth->port];
622 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
627 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
629 struct sh_eth_dev *eth = bus->priv;
630 struct sh_eth_info *port_info = ð->port_info[eth->port];
632 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
637 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
639 struct sh_eth_dev *eth = bus->priv;
640 struct sh_eth_info *port_info = ð->port_info[eth->port];
643 sh_eth_write(port_info,
644 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
646 sh_eth_write(port_info,
647 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
652 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
654 struct sh_eth_dev *eth = bus->priv;
655 struct sh_eth_info *port_info = ð->port_info[eth->port];
657 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
662 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
664 struct sh_eth_dev *eth = bus->priv;
665 struct sh_eth_info *port_info = ð->port_info[eth->port];
668 sh_eth_write(port_info,
669 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
671 sh_eth_write(port_info,
672 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
677 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
684 struct bb_miiphy_bus bb_miiphy_buses[] = {
687 .init = sh_eth_bb_init,
688 .mdio_active = sh_eth_bb_mdio_active,
689 .mdio_tristate = sh_eth_bb_mdio_tristate,
690 .set_mdio = sh_eth_bb_set_mdio,
691 .get_mdio = sh_eth_bb_get_mdio,
692 .set_mdc = sh_eth_bb_set_mdc,
693 .delay = sh_eth_bb_delay,
697 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);