2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * SPDX-License-Identifier: GPL-2.0+
16 * Portions of this code based on:
17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18 * for Linux kernel 2.4.x.
20 * Written 2002 ShuChen <shuchen@realtek.com.tw>
21 * See Linux Driver for full information
23 * Linux Driver Version 1.27a, 10.02.2002
26 * Jean Chen of RealTek Semiconductor Corp. for
27 * providing the evaluation NIC used to develop
28 * this driver. RealTek's support for Etherboot
34 * v1.0 11-26-2003 timlegge Initial port of Linux driver
35 * v1.5 01-17-2004 timlegge Initial driver output cleanup
37 * Indent Options: indent -kr -i8
38 ***************************************************************************/
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
51 #undef DEBUG_RTL8169_TX
52 #undef DEBUG_RTL8169_RX
54 #define drv_version "v1.5"
55 #define drv_date "01-17-2004"
59 /* Condensed operations for readability. */
60 #define currticks() get_timer(0)
64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
66 /* MAC address length*/
67 #define MAC_ADDR_LEN 6
69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
70 #define MAX_ETH_FRAME_SIZE 1536
72 #define TX_FIFO_THRESH 256 /* In bytes */
74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
82 #ifdef CONFIG_SYS_RX_ETH_BUFFER
83 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
85 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
87 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
88 #define RX_BUF_LEN 8192
90 #define RTL_MIN_IO_SIZE 0x80
91 #define TX_TIMEOUT (6*HZ)
93 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
94 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97 #define RTL_R8(reg) readb (ioaddr + (reg))
98 #define RTL_R16(reg) readw (ioaddr + (reg))
99 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
101 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
102 #define ETH_ALEN MAC_ADDR_LEN
105 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
106 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
108 enum RTL8169_registers {
109 MAC0 = 0, /* Ethernet hardware address. */
110 MAR0 = 8, /* Multicast filter. */
111 TxDescStartAddrLow = 0x20,
112 TxDescStartAddrHigh = 0x24,
113 TxHDescStartAddrLow = 0x28,
114 TxHDescStartAddrHigh = 0x2c,
139 RxDescStartAddrLow = 0xE4,
140 RxDescStartAddrHigh = 0xE8,
143 FuncEventMask = 0xF4,
144 FuncPresetState = 0xF8,
145 FuncForceEvent = 0xFC,
148 enum RTL8169_register_content {
149 /*InterruptStatusBits */
153 TxDescUnavail = 0x80,
176 Cfg9346_Unlock = 0xC0,
181 AcceptBroadcast = 0x08,
182 AcceptMulticast = 0x04,
184 AcceptAllPhys = 0x01,
191 TxInterFrameGapShift = 24,
192 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
194 /*rtl8169_PHYstatus */
204 /*GIGABIT_PHY_registers */
207 PHY_AUTO_NEGO_REG = 4,
208 PHY_1000_CTRL_REG = 9,
210 /*GIGABIT_PHY_REG_BIT */
211 PHY_Restart_Auto_Nego = 0x0200,
212 PHY_Enable_Auto_Nego = 0x1000,
214 /* PHY_STAT_REG = 1; */
215 PHY_Auto_Nego_Comp = 0x0020,
217 /* PHY_AUTO_NEGO_REG = 4; */
218 PHY_Cap_10_Half = 0x0020,
219 PHY_Cap_10_Full = 0x0040,
220 PHY_Cap_100_Half = 0x0080,
221 PHY_Cap_100_Full = 0x0100,
223 /* PHY_1000_CTRL_REG = 9; */
224 PHY_Cap_1000_Full = 0x0200,
236 TBILinkOK = 0x02000000,
241 u8 version; /* depend on RTL8169 docs */
242 u32 RxConfigMask; /* should clear the bits supported by this chip */
243 } rtl_chip_info[] = {
244 {"RTL-8169", 0x00, 0xff7e1880,},
245 {"RTL-8169", 0x04, 0xff7e1880,},
246 {"RTL-8169", 0x00, 0xff7e1880,},
247 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
248 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
249 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
250 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
251 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
252 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
253 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
254 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
255 {"RTL-8101e", 0x34, 0xff7e1880,},
256 {"RTL-8100e", 0x32, 0xff7e1880,},
259 enum _DescStatusBit {
280 #define RTL8169_DESC_SIZE 16
282 #if ARCH_DMA_MINALIGN > 256
283 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
285 # define RTL8169_ALIGN 256
289 * Warn if the cache-line size is larger than the descriptor size. In such
290 * cases the driver will likely fail because the CPU needs to flush the cache
291 * when requeuing RX buffers, therefore descriptors written by the hardware
294 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
295 #warning cache-line size is larger than descriptor size
298 /* Define the TX Descriptor */
299 DEFINE_ALIGN_BUFFER(struct TxDesc, tx_ring, NUM_TX_DESC, RTL8169_ALIGN);
301 /* Define the RX Descriptor */
302 DEFINE_ALIGN_BUFFER(struct RxDesc, rx_ring, NUM_RX_DESC, RTL8169_ALIGN);
305 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
306 * descriptors point to a part of this buffer.
308 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
311 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
312 * descriptors point to a part of this buffer.
314 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
316 struct rtl8169_private {
317 void *mmio_addr; /* memory map physical address */
319 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
320 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
321 unsigned long dirty_tx;
322 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
323 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
324 unsigned char *RxBufferRings; /* Index of Rx Buffer */
325 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
326 unsigned char *Tx_skbuff[NUM_TX_DESC];
329 static struct rtl8169_private *tpc;
331 static const u16 rtl8169_intr_mask =
332 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
334 static const unsigned int rtl8169_rx_config =
335 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
337 static struct pci_device_id supported[] = {
338 {PCI_VENDOR_ID_REALTEK, 0x8167},
339 {PCI_VENDOR_ID_REALTEK, 0x8168},
340 {PCI_VENDOR_ID_REALTEK, 0x8169},
344 void mdio_write(int RegAddr, int value)
348 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
351 for (i = 2000; i > 0; i--) {
352 /* Check if the RTL8169 has completed writing to the specified MII register */
353 if (!(RTL_R32(PHYAR) & 0x80000000)) {
361 int mdio_read(int RegAddr)
365 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
368 for (i = 2000; i > 0; i--) {
369 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
370 if (RTL_R32(PHYAR) & 0x80000000) {
371 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
380 static int rtl8169_init_board(struct eth_device *dev)
386 printf ("%s\n", __FUNCTION__);
388 ioaddr = dev->iobase;
390 /* Soft reset the chip. */
391 RTL_W8(ChipCmd, CmdReset);
393 /* Check that the chip has finished the reset. */
394 for (i = 1000; i > 0; i--)
395 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
400 /* identify chip attached to board */
401 tmp = RTL_R32(TxConfig);
402 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
404 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
405 if (tmp == rtl_chip_info[i].version) {
411 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
412 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
413 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
421 * Cache maintenance functions. These are simple wrappers around the more
422 * general purpose flush_cache() and invalidate_dcache_range() functions.
425 static void rtl_inval_rx_desc(struct RxDesc *desc)
427 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
428 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
430 invalidate_dcache_range(start, end);
433 static void rtl_flush_rx_desc(struct RxDesc *desc)
435 flush_cache((unsigned long)desc, sizeof(*desc));
438 static void rtl_inval_tx_desc(struct TxDesc *desc)
440 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
441 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
443 invalidate_dcache_range(start, end);
446 static void rtl_flush_tx_desc(struct TxDesc *desc)
448 flush_cache((unsigned long)desc, sizeof(*desc));
451 static void rtl_inval_buffer(void *buf, size_t size)
453 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
454 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
456 invalidate_dcache_range(start, end);
459 static void rtl_flush_buffer(void *buf, size_t size)
461 flush_cache((unsigned long)buf, size);
464 /**************************************************************************
465 RECV - Receive a frame
466 ***************************************************************************/
467 static int rtl_recv(struct eth_device *dev)
469 /* return true if there's an ethernet packet ready to read */
470 /* nic->packet should contain data on return */
471 /* nic->packetlen should contain length of data */
475 #ifdef DEBUG_RTL8169_RX
476 printf ("%s\n", __FUNCTION__);
478 ioaddr = dev->iobase;
480 cur_rx = tpc->cur_rx;
482 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
484 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
485 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
486 unsigned char rxdata[RX_BUF_LEN];
487 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
488 status) & 0x00001FFF) - 4;
490 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
491 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
493 if (cur_rx == NUM_RX_DESC - 1)
494 tpc->RxDescArray[cur_rx].status =
495 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
497 tpc->RxDescArray[cur_rx].status =
498 cpu_to_le32(OWNbit + RX_BUF_SIZE);
499 tpc->RxDescArray[cur_rx].buf_addr =
500 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
501 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
503 NetReceive(rxdata, length);
507 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
508 tpc->cur_rx = cur_rx;
512 ushort sts = RTL_R8(IntrStatus);
513 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
514 udelay(100); /* wait */
516 tpc->cur_rx = cur_rx;
517 return (0); /* initially as this is called to flush the input */
521 /**************************************************************************
522 SEND - Transmit a frame
523 ***************************************************************************/
524 static int rtl_send(struct eth_device *dev, void *packet, int length)
526 /* send the packet to destination */
530 int entry = tpc->cur_tx % NUM_TX_DESC;
534 #ifdef DEBUG_RTL8169_TX
535 int stime = currticks();
536 printf ("%s\n", __FUNCTION__);
537 printf("sending %d bytes\n", len);
540 ioaddr = dev->iobase;
542 /* point to the current txb incase multiple tx_rings are used */
543 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
544 memcpy(ptxb, (char *)packet, (int)length);
545 rtl_flush_buffer(ptxb, length);
547 while (len < ETH_ZLEN)
550 tpc->TxDescArray[entry].buf_Haddr = 0;
551 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb));
552 if (entry != (NUM_TX_DESC - 1)) {
553 tpc->TxDescArray[entry].status =
554 cpu_to_le32((OWNbit | FSbit | LSbit) |
555 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
557 tpc->TxDescArray[entry].status =
558 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
559 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
561 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
562 RTL_W8(TxPoll, 0x40); /* set polling bit */
565 to = currticks() + TX_TIMEOUT;
567 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
568 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
569 && (currticks() < to)); /* wait */
571 if (currticks() >= to) {
572 #ifdef DEBUG_RTL8169_TX
573 puts("tx timeout/error\n");
574 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
578 #ifdef DEBUG_RTL8169_TX
583 /* Delay to make net console (nc) work properly */
588 static void rtl8169_set_rx_mode(struct eth_device *dev)
590 u32 mc_filter[2]; /* Multicast hash filter */
595 printf ("%s\n", __FUNCTION__);
599 /* Too many to filter perfectly -- accept all multicasts. */
600 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
601 mc_filter[1] = mc_filter[0] = 0xffffffff;
603 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
604 rtl_chip_info[tpc->chipset].RxConfigMask);
606 RTL_W32(RxConfig, tmp);
607 RTL_W32(MAR0 + 0, mc_filter[0]);
608 RTL_W32(MAR0 + 4, mc_filter[1]);
611 static void rtl8169_hw_start(struct eth_device *dev)
616 int stime = currticks();
617 printf ("%s\n", __FUNCTION__);
621 /* Soft reset the chip. */
622 RTL_W8(ChipCmd, CmdReset);
624 /* Check that the chip has finished the reset. */
625 for (i = 1000; i > 0; i--) {
626 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
633 RTL_W8(Cfg9346, Cfg9346_Unlock);
635 /* RTL-8169sb/8110sb or previous version */
636 if (tpc->chipset <= 5)
637 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
639 RTL_W8(EarlyTxThres, EarlyTxThld);
641 /* For gigabit rtl8169 */
642 RTL_W16(RxMaxSize, RxPacketMaxSize);
644 /* Set Rx Config register */
645 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
646 rtl_chip_info[tpc->chipset].RxConfigMask);
647 RTL_W32(RxConfig, i);
649 /* Set DMA burst size and Interframe Gap Time */
650 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
651 (InterFrameGap << TxInterFrameGapShift));
656 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray));
657 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
658 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray));
659 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
661 /* RTL-8169sc/8110sc or later version */
662 if (tpc->chipset > 5)
663 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
665 RTL_W8(Cfg9346, Cfg9346_Lock);
668 RTL_W32(RxMissed, 0);
670 rtl8169_set_rx_mode(dev);
672 /* no early-rx interrupts */
673 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
676 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
680 static void rtl8169_init_ring(struct eth_device *dev)
685 int stime = currticks();
686 printf ("%s\n", __FUNCTION__);
692 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
693 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
695 for (i = 0; i < NUM_TX_DESC; i++) {
696 tpc->Tx_skbuff[i] = &txb[i];
699 for (i = 0; i < NUM_RX_DESC; i++) {
700 if (i == (NUM_RX_DESC - 1))
701 tpc->RxDescArray[i].status =
702 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
704 tpc->RxDescArray[i].status =
705 cpu_to_le32(OWNbit + RX_BUF_SIZE);
707 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
708 tpc->RxDescArray[i].buf_addr =
709 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
710 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
714 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
718 /**************************************************************************
719 RESET - Finish setting up the ethernet interface
720 ***************************************************************************/
721 static int rtl_reset(struct eth_device *dev, bd_t *bis)
726 int stime = currticks();
727 printf ("%s\n", __FUNCTION__);
730 rtl8169_init_ring(dev);
731 rtl8169_hw_start(dev);
732 /* Construct a perfect filter frame with the mac address as first match
733 * and broadcast for all others */
734 for (i = 0; i < 192; i++)
737 txb[0] = dev->enetaddr[0];
738 txb[1] = dev->enetaddr[1];
739 txb[2] = dev->enetaddr[2];
740 txb[3] = dev->enetaddr[3];
741 txb[4] = dev->enetaddr[4];
742 txb[5] = dev->enetaddr[5];
745 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
750 /**************************************************************************
751 HALT - Turn off ethernet interface
752 ***************************************************************************/
753 static void rtl_halt(struct eth_device *dev)
758 printf ("%s\n", __FUNCTION__);
761 ioaddr = dev->iobase;
763 /* Stop the chip's Tx and Rx DMA processes. */
764 RTL_W8(ChipCmd, 0x00);
766 /* Disable interrupts by clearing the interrupt mask. */
767 RTL_W16(IntrMask, 0x0000);
769 RTL_W32(RxMissed, 0);
771 for (i = 0; i < NUM_RX_DESC; i++) {
772 tpc->RxBufferRing[i] = NULL;
776 /**************************************************************************
777 INIT - Look for an adapter, this routine's visible to the outside
778 ***************************************************************************/
780 #define board_found 1
782 static int rtl_init(struct eth_device *dev, bd_t *bis)
784 static int board_idx = -1;
786 int option = -1, Cap10_100 = 0, Cap1000 = 0;
789 printf ("%s\n", __FUNCTION__);
792 ioaddr = dev->iobase;
796 /* point to private storage */
799 rc = rtl8169_init_board(dev);
803 /* Get MAC address. FIXME: read EEPROM */
804 for (i = 0; i < MAC_ADDR_LEN; i++)
805 dev->enetaddr[i] = RTL_R8(MAC0 + i);
808 printf("chipset = %d\n", tpc->chipset);
809 printf("MAC Address");
810 for (i = 0; i < MAC_ADDR_LEN; i++)
811 printf(":%02x", dev->enetaddr[i]);
816 /* Print out some hardware info */
817 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
820 /* if TBI is not endbled */
821 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
822 int val = mdio_read(PHY_AUTO_NEGO_REG);
824 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
825 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
828 printf("%s: Force-mode Enabled.\n", dev->name);
830 Cap10_100 = 0, Cap1000 = 0;
833 Cap10_100 = PHY_Cap_10_Half;
834 Cap1000 = PHY_Cap_Null;
837 Cap10_100 = PHY_Cap_10_Full;
838 Cap1000 = PHY_Cap_Null;
841 Cap10_100 = PHY_Cap_100_Half;
842 Cap1000 = PHY_Cap_Null;
845 Cap10_100 = PHY_Cap_100_Full;
846 Cap1000 = PHY_Cap_Null;
849 Cap10_100 = PHY_Cap_Null;
850 Cap1000 = PHY_Cap_1000_Full;
855 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
856 mdio_write(PHY_1000_CTRL_REG, Cap1000);
859 printf("%s: Auto-negotiation Enabled.\n",
862 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
863 mdio_write(PHY_AUTO_NEGO_REG,
864 PHY_Cap_10_Half | PHY_Cap_10_Full |
865 PHY_Cap_100_Half | PHY_Cap_100_Full |
868 /* enable 1000 Full Mode */
869 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
873 /* Enable auto-negotiation and restart auto-nigotiation */
874 mdio_write(PHY_CTRL_REG,
875 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
878 /* wait for auto-negotiation process */
879 for (i = 10000; i > 0; i--) {
880 /* check if auto-negotiation complete */
881 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
883 option = RTL_R8(PHYstatus);
884 if (option & _1000bpsF) {
886 printf("%s: 1000Mbps Full-duplex operation.\n",
891 printf("%s: %sMbps %s-duplex operation.\n",
893 (option & _100bps) ? "100" :
895 (option & FullDup) ? "Full" :
903 } /* end for-loop to wait for auto-negotiation process */
909 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
911 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
915 tpc->TxDescArray = tx_ring;
916 tpc->RxDescArray = rx_ring;
921 int rtl8169_initialize(bd_t *bis)
925 struct eth_device *dev;
934 if ((devno = pci_find_devices(supported, idx++)) < 0)
937 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
948 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
951 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
953 dev = (struct eth_device *)malloc(sizeof *dev);
955 printf("Can not allocate memory of rtl8169\n");
959 memset(dev, 0, sizeof(*dev));
960 sprintf (dev->name, "RTL8169#%d", card_number);
962 dev->priv = (void *) devno;
963 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
965 dev->init = rtl_reset;
966 dev->halt = rtl_halt;
967 dev->send = rtl_send;
968 dev->recv = rtl_recv;