2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * SPDX-License-Identifier: GPL-2.0+
16 * Portions of this code based on:
17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18 * for Linux kernel 2.4.x.
20 * Written 2002 ShuChen <shuchen@realtek.com.tw>
21 * See Linux Driver for full information
23 * Linux Driver Version 1.27a, 10.02.2002
26 * Jean Chen of RealTek Semiconductor Corp. for
27 * providing the evaluation NIC used to develop
28 * this driver. RealTek's support for Etherboot
34 * v1.0 11-26-2003 timlegge Initial port of Linux driver
35 * v1.5 01-17-2004 timlegge Initial driver output cleanup
37 * Indent Options: indent -kr -i8
38 ***************************************************************************/
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
52 #undef DEBUG_RTL8169_TX
53 #undef DEBUG_RTL8169_RX
55 #define drv_version "v1.5"
56 #define drv_date "01-17-2004"
60 /* Condensed operations for readability. */
61 #define currticks() get_timer(0)
65 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
67 /* MAC address length*/
68 #define MAC_ADDR_LEN 6
70 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
71 #define MAX_ETH_FRAME_SIZE 1536
73 #define TX_FIFO_THRESH 256 /* In bytes */
75 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
76 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
78 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
79 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
80 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
82 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
83 #ifdef CONFIG_SYS_RX_ETH_BUFFER
84 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER
86 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
88 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
89 #define RX_BUF_LEN 8192
91 #define RTL_MIN_IO_SIZE 0x80
92 #define TX_TIMEOUT (6*HZ)
94 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
95 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
96 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
97 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
98 #define RTL_R8(reg) readb (ioaddr + (reg))
99 #define RTL_R16(reg) readw (ioaddr + (reg))
100 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
102 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
103 #define ETH_ALEN MAC_ADDR_LEN
106 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
107 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
109 enum RTL8169_registers {
110 MAC0 = 0, /* Ethernet hardware address. */
111 MAR0 = 8, /* Multicast filter. */
112 TxDescStartAddrLow = 0x20,
113 TxDescStartAddrHigh = 0x24,
114 TxHDescStartAddrLow = 0x28,
115 TxHDescStartAddrHigh = 0x2c,
140 RxDescStartAddrLow = 0xE4,
141 RxDescStartAddrHigh = 0xE8,
144 FuncEventMask = 0xF4,
145 FuncPresetState = 0xF8,
146 FuncForceEvent = 0xFC,
149 enum RTL8169_register_content {
150 /*InterruptStatusBits */
154 TxDescUnavail = 0x80,
177 Cfg9346_Unlock = 0xC0,
182 AcceptBroadcast = 0x08,
183 AcceptMulticast = 0x04,
185 AcceptAllPhys = 0x01,
192 TxInterFrameGapShift = 24,
193 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
195 /*rtl8169_PHYstatus */
205 /*GIGABIT_PHY_registers */
208 PHY_AUTO_NEGO_REG = 4,
209 PHY_1000_CTRL_REG = 9,
211 /*GIGABIT_PHY_REG_BIT */
212 PHY_Restart_Auto_Nego = 0x0200,
213 PHY_Enable_Auto_Nego = 0x1000,
215 /* PHY_STAT_REG = 1; */
216 PHY_Auto_Nego_Comp = 0x0020,
218 /* PHY_AUTO_NEGO_REG = 4; */
219 PHY_Cap_10_Half = 0x0020,
220 PHY_Cap_10_Full = 0x0040,
221 PHY_Cap_100_Half = 0x0080,
222 PHY_Cap_100_Full = 0x0100,
224 /* PHY_1000_CTRL_REG = 9; */
225 PHY_Cap_1000_Full = 0x0200,
237 TBILinkOK = 0x02000000,
242 u8 version; /* depend on RTL8169 docs */
243 u32 RxConfigMask; /* should clear the bits supported by this chip */
244 } rtl_chip_info[] = {
245 {"RTL-8169", 0x00, 0xff7e1880,},
246 {"RTL-8169", 0x04, 0xff7e1880,},
247 {"RTL-8169", 0x00, 0xff7e1880,},
248 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
249 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
250 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
251 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
252 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
253 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
254 {"RTL-8168d/8111d", 0x28, 0xff7e1880,},
255 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
256 {"RTL-8168/8111g", 0x4c, 0xff7e1880,},
257 {"RTL-8101e", 0x34, 0xff7e1880,},
258 {"RTL-8100e", 0x32, 0xff7e1880,},
261 enum _DescStatusBit {
282 #define RTL8169_DESC_SIZE 16
284 #if ARCH_DMA_MINALIGN > 256
285 # define RTL8169_ALIGN ARCH_DMA_MINALIGN
287 # define RTL8169_ALIGN 256
291 * Warn if the cache-line size is larger than the descriptor size. In such
292 * cases the driver will likely fail because the CPU needs to flush the cache
293 * when requeuing RX buffers, therefore descriptors written by the hardware
296 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
297 * the driver to allocate descriptors from a pool of non-cached memory.
299 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
300 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && !defined(CONFIG_SYS_DCACHE_OFF)
301 #warning cache-line size is larger than descriptor size
306 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All
307 * descriptors point to a part of this buffer.
309 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
312 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All
313 * descriptors point to a part of this buffer.
315 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN);
317 struct rtl8169_private {
318 void *mmio_addr; /* memory map physical address */
320 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
321 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
322 unsigned long dirty_tx;
323 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
324 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
325 unsigned char *RxBufferRings; /* Index of Rx Buffer */
326 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
327 unsigned char *Tx_skbuff[NUM_TX_DESC];
330 static struct rtl8169_private *tpc;
332 static const u16 rtl8169_intr_mask =
333 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
335 static const unsigned int rtl8169_rx_config =
336 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
338 static struct pci_device_id supported[] = {
339 {PCI_VENDOR_ID_REALTEK, 0x8167},
340 {PCI_VENDOR_ID_REALTEK, 0x8168},
341 {PCI_VENDOR_ID_REALTEK, 0x8169},
345 void mdio_write(int RegAddr, int value)
349 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
352 for (i = 2000; i > 0; i--) {
353 /* Check if the RTL8169 has completed writing to the specified MII register */
354 if (!(RTL_R32(PHYAR) & 0x80000000)) {
362 int mdio_read(int RegAddr)
366 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
369 for (i = 2000; i > 0; i--) {
370 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
371 if (RTL_R32(PHYAR) & 0x80000000) {
372 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
381 static int rtl8169_init_board(struct eth_device *dev)
387 printf ("%s\n", __FUNCTION__);
389 ioaddr = dev->iobase;
391 /* Soft reset the chip. */
392 RTL_W8(ChipCmd, CmdReset);
394 /* Check that the chip has finished the reset. */
395 for (i = 1000; i > 0; i--)
396 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
401 /* identify chip attached to board */
402 tmp = RTL_R32(TxConfig);
403 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
405 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
406 if (tmp == rtl_chip_info[i].version) {
412 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
413 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
414 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
422 * TX and RX descriptors are 16 bytes. This causes problems with the cache
423 * maintenance on CPUs where the cache-line size exceeds the size of these
424 * descriptors. What will happen is that when the driver receives a packet
425 * it will be immediately requeued for the hardware to reuse. The CPU will
426 * therefore need to flush the cache-line containing the descriptor, which
427 * will cause all other descriptors in the same cache-line to be flushed
428 * along with it. If one of those descriptors had been written to by the
429 * device those changes (and the associated packet) will be lost.
431 * To work around this, we make use of non-cached memory if available. If
432 * descriptors are mapped uncached there's no need to manually flush them
433 * or invalidate them.
435 * Note that this only applies to descriptors. The packet data buffers do
436 * not have the same constraints since they are 1536 bytes large, so they
437 * are unlikely to share cache-lines.
439 static void *rtl_alloc_descs(unsigned int num)
441 size_t size = num * RTL8169_DESC_SIZE;
443 #ifdef CONFIG_SYS_NONCACHED_MEMORY
444 return (void *)noncached_alloc(size, RTL8169_ALIGN);
446 return memalign(RTL8169_ALIGN, size);
451 * Cache maintenance functions. These are simple wrappers around the more
452 * general purpose flush_cache() and invalidate_dcache_range() functions.
455 static void rtl_inval_rx_desc(struct RxDesc *desc)
457 #ifndef CONFIG_SYS_NONCACHED_MEMORY
458 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
459 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
461 invalidate_dcache_range(start, end);
465 static void rtl_flush_rx_desc(struct RxDesc *desc)
467 #ifndef CONFIG_SYS_NONCACHED_MEMORY
468 flush_cache((unsigned long)desc, sizeof(*desc));
472 static void rtl_inval_tx_desc(struct TxDesc *desc)
474 #ifndef CONFIG_SYS_NONCACHED_MEMORY
475 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
476 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN);
478 invalidate_dcache_range(start, end);
482 static void rtl_flush_tx_desc(struct TxDesc *desc)
484 #ifndef CONFIG_SYS_NONCACHED_MEMORY
485 flush_cache((unsigned long)desc, sizeof(*desc));
489 static void rtl_inval_buffer(void *buf, size_t size)
491 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
492 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
494 invalidate_dcache_range(start, end);
497 static void rtl_flush_buffer(void *buf, size_t size)
499 flush_cache((unsigned long)buf, size);
502 /**************************************************************************
503 RECV - Receive a frame
504 ***************************************************************************/
505 static int rtl_recv(struct eth_device *dev)
507 /* return true if there's an ethernet packet ready to read */
508 /* nic->packet should contain data on return */
509 /* nic->packetlen should contain length of data */
513 #ifdef DEBUG_RTL8169_RX
514 printf ("%s\n", __FUNCTION__);
516 ioaddr = dev->iobase;
518 cur_rx = tpc->cur_rx;
520 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]);
522 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
523 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
524 unsigned char rxdata[RX_BUF_LEN];
525 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
526 status) & 0x00001FFF) - 4;
528 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length);
529 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
531 if (cur_rx == NUM_RX_DESC - 1)
532 tpc->RxDescArray[cur_rx].status =
533 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
535 tpc->RxDescArray[cur_rx].status =
536 cpu_to_le32(OWNbit + RX_BUF_SIZE);
537 tpc->RxDescArray[cur_rx].buf_addr =
538 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
539 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
541 NetReceive(rxdata, length);
545 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
546 tpc->cur_rx = cur_rx;
550 ushort sts = RTL_R8(IntrStatus);
551 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
552 udelay(100); /* wait */
554 tpc->cur_rx = cur_rx;
555 return (0); /* initially as this is called to flush the input */
559 /**************************************************************************
560 SEND - Transmit a frame
561 ***************************************************************************/
562 static int rtl_send(struct eth_device *dev, void *packet, int length)
564 /* send the packet to destination */
568 int entry = tpc->cur_tx % NUM_TX_DESC;
572 #ifdef DEBUG_RTL8169_TX
573 int stime = currticks();
574 printf ("%s\n", __FUNCTION__);
575 printf("sending %d bytes\n", len);
578 ioaddr = dev->iobase;
580 /* point to the current txb incase multiple tx_rings are used */
581 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
582 memcpy(ptxb, (char *)packet, (int)length);
583 rtl_flush_buffer(ptxb, length);
585 while (len < ETH_ZLEN)
588 tpc->TxDescArray[entry].buf_Haddr = 0;
589 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb));
590 if (entry != (NUM_TX_DESC - 1)) {
591 tpc->TxDescArray[entry].status =
592 cpu_to_le32((OWNbit | FSbit | LSbit) |
593 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
595 tpc->TxDescArray[entry].status =
596 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
597 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
599 rtl_flush_tx_desc(&tpc->TxDescArray[entry]);
600 RTL_W8(TxPoll, 0x40); /* set polling bit */
603 to = currticks() + TX_TIMEOUT;
605 rtl_inval_tx_desc(&tpc->TxDescArray[entry]);
606 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
607 && (currticks() < to)); /* wait */
609 if (currticks() >= to) {
610 #ifdef DEBUG_RTL8169_TX
611 puts("tx timeout/error\n");
612 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
616 #ifdef DEBUG_RTL8169_TX
621 /* Delay to make net console (nc) work properly */
626 static void rtl8169_set_rx_mode(struct eth_device *dev)
628 u32 mc_filter[2]; /* Multicast hash filter */
633 printf ("%s\n", __FUNCTION__);
637 /* Too many to filter perfectly -- accept all multicasts. */
638 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
639 mc_filter[1] = mc_filter[0] = 0xffffffff;
641 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
642 rtl_chip_info[tpc->chipset].RxConfigMask);
644 RTL_W32(RxConfig, tmp);
645 RTL_W32(MAR0 + 0, mc_filter[0]);
646 RTL_W32(MAR0 + 4, mc_filter[1]);
649 static void rtl8169_hw_start(struct eth_device *dev)
654 int stime = currticks();
655 printf ("%s\n", __FUNCTION__);
659 /* Soft reset the chip. */
660 RTL_W8(ChipCmd, CmdReset);
662 /* Check that the chip has finished the reset. */
663 for (i = 1000; i > 0; i--) {
664 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
671 RTL_W8(Cfg9346, Cfg9346_Unlock);
673 /* RTL-8169sb/8110sb or previous version */
674 if (tpc->chipset <= 5)
675 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
677 RTL_W8(EarlyTxThres, EarlyTxThld);
679 /* For gigabit rtl8169 */
680 RTL_W16(RxMaxSize, RxPacketMaxSize);
682 /* Set Rx Config register */
683 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
684 rtl_chip_info[tpc->chipset].RxConfigMask);
685 RTL_W32(RxConfig, i);
687 /* Set DMA burst size and Interframe Gap Time */
688 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
689 (InterFrameGap << TxInterFrameGapShift));
694 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray));
695 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
696 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray));
697 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
699 /* RTL-8169sc/8110sc or later version */
700 if (tpc->chipset > 5)
701 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
703 RTL_W8(Cfg9346, Cfg9346_Lock);
706 RTL_W32(RxMissed, 0);
708 rtl8169_set_rx_mode(dev);
710 /* no early-rx interrupts */
711 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
714 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
718 static void rtl8169_init_ring(struct eth_device *dev)
723 int stime = currticks();
724 printf ("%s\n", __FUNCTION__);
730 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
731 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
733 for (i = 0; i < NUM_TX_DESC; i++) {
734 tpc->Tx_skbuff[i] = &txb[i];
737 for (i = 0; i < NUM_RX_DESC; i++) {
738 if (i == (NUM_RX_DESC - 1))
739 tpc->RxDescArray[i].status =
740 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
742 tpc->RxDescArray[i].status =
743 cpu_to_le32(OWNbit + RX_BUF_SIZE);
745 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
746 tpc->RxDescArray[i].buf_addr =
747 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
748 rtl_flush_rx_desc(&tpc->RxDescArray[i]);
752 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
756 /**************************************************************************
757 RESET - Finish setting up the ethernet interface
758 ***************************************************************************/
759 static int rtl_reset(struct eth_device *dev, bd_t *bis)
764 int stime = currticks();
765 printf ("%s\n", __FUNCTION__);
768 rtl8169_init_ring(dev);
769 rtl8169_hw_start(dev);
770 /* Construct a perfect filter frame with the mac address as first match
771 * and broadcast for all others */
772 for (i = 0; i < 192; i++)
775 txb[0] = dev->enetaddr[0];
776 txb[1] = dev->enetaddr[1];
777 txb[2] = dev->enetaddr[2];
778 txb[3] = dev->enetaddr[3];
779 txb[4] = dev->enetaddr[4];
780 txb[5] = dev->enetaddr[5];
783 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
788 /**************************************************************************
789 HALT - Turn off ethernet interface
790 ***************************************************************************/
791 static void rtl_halt(struct eth_device *dev)
796 printf ("%s\n", __FUNCTION__);
799 ioaddr = dev->iobase;
801 /* Stop the chip's Tx and Rx DMA processes. */
802 RTL_W8(ChipCmd, 0x00);
804 /* Disable interrupts by clearing the interrupt mask. */
805 RTL_W16(IntrMask, 0x0000);
807 RTL_W32(RxMissed, 0);
809 for (i = 0; i < NUM_RX_DESC; i++) {
810 tpc->RxBufferRing[i] = NULL;
814 /**************************************************************************
815 INIT - Look for an adapter, this routine's visible to the outside
816 ***************************************************************************/
818 #define board_found 1
820 static int rtl_init(struct eth_device *dev, bd_t *bis)
822 static int board_idx = -1;
824 int option = -1, Cap10_100 = 0, Cap1000 = 0;
827 printf ("%s\n", __FUNCTION__);
830 ioaddr = dev->iobase;
834 /* point to private storage */
837 rc = rtl8169_init_board(dev);
841 /* Get MAC address. FIXME: read EEPROM */
842 for (i = 0; i < MAC_ADDR_LEN; i++)
843 dev->enetaddr[i] = RTL_R8(MAC0 + i);
846 printf("chipset = %d\n", tpc->chipset);
847 printf("MAC Address");
848 for (i = 0; i < MAC_ADDR_LEN; i++)
849 printf(":%02x", dev->enetaddr[i]);
854 /* Print out some hardware info */
855 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
858 /* if TBI is not endbled */
859 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
860 int val = mdio_read(PHY_AUTO_NEGO_REG);
862 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
863 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
866 printf("%s: Force-mode Enabled.\n", dev->name);
868 Cap10_100 = 0, Cap1000 = 0;
871 Cap10_100 = PHY_Cap_10_Half;
872 Cap1000 = PHY_Cap_Null;
875 Cap10_100 = PHY_Cap_10_Full;
876 Cap1000 = PHY_Cap_Null;
879 Cap10_100 = PHY_Cap_100_Half;
880 Cap1000 = PHY_Cap_Null;
883 Cap10_100 = PHY_Cap_100_Full;
884 Cap1000 = PHY_Cap_Null;
887 Cap10_100 = PHY_Cap_Null;
888 Cap1000 = PHY_Cap_1000_Full;
893 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
894 mdio_write(PHY_1000_CTRL_REG, Cap1000);
897 printf("%s: Auto-negotiation Enabled.\n",
900 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
901 mdio_write(PHY_AUTO_NEGO_REG,
902 PHY_Cap_10_Half | PHY_Cap_10_Full |
903 PHY_Cap_100_Half | PHY_Cap_100_Full |
906 /* enable 1000 Full Mode */
907 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
911 /* Enable auto-negotiation and restart auto-nigotiation */
912 mdio_write(PHY_CTRL_REG,
913 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
916 /* wait for auto-negotiation process */
917 for (i = 10000; i > 0; i--) {
918 /* check if auto-negotiation complete */
919 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
921 option = RTL_R8(PHYstatus);
922 if (option & _1000bpsF) {
924 printf("%s: 1000Mbps Full-duplex operation.\n",
929 printf("%s: %sMbps %s-duplex operation.\n",
931 (option & _100bps) ? "100" :
933 (option & FullDup) ? "Full" :
941 } /* end for-loop to wait for auto-negotiation process */
947 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
949 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
954 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
955 if (!tpc->RxDescArray)
958 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC);
959 if (!tpc->TxDescArray)
965 int rtl8169_initialize(bd_t *bis)
969 struct eth_device *dev;
979 if ((devno = pci_find_devices(supported, idx++)) < 0)
982 pci_read_config_word(devno, PCI_DEVICE_ID, &device);
993 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
996 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
998 dev = (struct eth_device *)malloc(sizeof *dev);
1000 printf("Can not allocate memory of rtl8169\n");
1004 memset(dev, 0, sizeof(*dev));
1005 sprintf (dev->name, "RTL8169#%d", card_number);
1007 dev->priv = (void *) devno;
1008 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
1010 dev->init = rtl_reset;
1011 dev->halt = rtl_halt;
1012 dev->send = rtl_send;
1013 dev->recv = rtl_recv;
1015 err = rtl_init(dev, bis);
1017 printf(pr_fmt("failed to initialize card: %d\n"), err);