2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * Portions of this code based on:
29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
30 * for Linux kernel 2.4.x.
32 * Written 2002 ShuChen <shuchen@realtek.com.tw>
33 * See Linux Driver for full information
35 * Linux Driver Version 1.27a, 10.02.2002
38 * Jean Chen of RealTek Semiconductor Corp. for
39 * providing the evaluation NIC used to develop
40 * this driver. RealTek's support for Etherboot
46 * v1.0 11-26-2003 timlegge Initial port of Linux driver
47 * v1.5 01-17-2004 timlegge Initial driver output cleanup
49 * Indent Options: indent -kr -i8
50 ***************************************************************************/
52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
53 * Modified to use le32_to_cpu and cpu_to_le32 properly
63 #undef DEBUG_RTL8169_TX
64 #undef DEBUG_RTL8169_RX
66 #define drv_version "v1.5"
67 #define drv_date "01-17-2004"
71 /* Condensed operations for readability. */
72 #define currticks() get_timer(0)
76 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
78 /* MAC address length*/
79 #define MAC_ADDR_LEN 6
81 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
82 #define MAX_ETH_FRAME_SIZE 1536
84 #define TX_FIFO_THRESH 256 /* In bytes */
86 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
87 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
88 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
89 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
90 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
91 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
93 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
95 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
96 #define RX_BUF_LEN 8192
98 #define RTL_MIN_IO_SIZE 0x80
99 #define TX_TIMEOUT (6*HZ)
101 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
109 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
110 #define ETH_ALEN MAC_ADDR_LEN
113 enum RTL8169_registers {
114 MAC0 = 0, /* Ethernet hardware address. */
115 MAR0 = 8, /* Multicast filter. */
116 TxDescStartAddrLow = 0x20,
117 TxDescStartAddrHigh = 0x24,
118 TxHDescStartAddrLow = 0x28,
119 TxHDescStartAddrHigh = 0x2c,
144 RxDescStartAddrLow = 0xE4,
145 RxDescStartAddrHigh = 0xE8,
148 FuncEventMask = 0xF4,
149 FuncPresetState = 0xF8,
150 FuncForceEvent = 0xFC,
153 enum RTL8169_register_content {
154 /*InterruptStatusBits */
158 TxDescUnavail = 0x80,
181 Cfg9346_Unlock = 0xC0,
186 AcceptBroadcast = 0x08,
187 AcceptMulticast = 0x04,
189 AcceptAllPhys = 0x01,
196 TxInterFrameGapShift = 24,
197 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
199 /*rtl8169_PHYstatus */
209 /*GIGABIT_PHY_registers */
212 PHY_AUTO_NEGO_REG = 4,
213 PHY_1000_CTRL_REG = 9,
215 /*GIGABIT_PHY_REG_BIT */
216 PHY_Restart_Auto_Nego = 0x0200,
217 PHY_Enable_Auto_Nego = 0x1000,
219 /* PHY_STAT_REG = 1; */
220 PHY_Auto_Nego_Comp = 0x0020,
222 /* PHY_AUTO_NEGO_REG = 4; */
223 PHY_Cap_10_Half = 0x0020,
224 PHY_Cap_10_Full = 0x0040,
225 PHY_Cap_100_Half = 0x0080,
226 PHY_Cap_100_Full = 0x0100,
228 /* PHY_1000_CTRL_REG = 9; */
229 PHY_Cap_1000_Full = 0x0200,
241 TBILinkOK = 0x02000000,
246 u8 version; /* depend on RTL8169 docs */
247 u32 RxConfigMask; /* should clear the bits supported by this chip */
248 } rtl_chip_info[] = {
249 {"RTL-8169", 0x00, 0xff7e1880,},
250 {"RTL-8169", 0x04, 0xff7e1880,},
251 {"RTL-8169", 0x00, 0xff7e1880,},
252 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
253 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
254 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
255 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
256 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
257 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
258 {"RTL-8101e", 0x34, 0xff7e1880,},
259 {"RTL-8100e", 0x32, 0xff7e1880,},
262 enum _DescStatusBit {
283 /* Define the TX Descriptor */
284 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
285 /* __attribute__ ((aligned(256))); */
287 /* Create a static buffer of size RX_BUF_SZ for each
288 TX Descriptor. All descriptors point to a
289 part of this buffer */
290 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
292 /* Define the RX Descriptor */
293 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
294 /* __attribute__ ((aligned(256))); */
296 /* Create a static buffer of size RX_BUF_SZ for each
297 RX Descriptor All descriptors point to a
298 part of this buffer */
299 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
301 struct rtl8169_private {
302 void *mmio_addr; /* memory map physical address */
304 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
305 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
306 unsigned long dirty_tx;
307 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
308 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
309 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
310 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
311 unsigned char *RxBufferRings; /* Index of Rx Buffer */
312 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
313 unsigned char *Tx_skbuff[NUM_TX_DESC];
316 static struct rtl8169_private *tpc;
318 static const u16 rtl8169_intr_mask =
319 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
321 static const unsigned int rtl8169_rx_config =
322 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
324 static struct pci_device_id supported[] = {
325 {PCI_VENDOR_ID_REALTEK, 0x8167},
326 {PCI_VENDOR_ID_REALTEK, 0x8169},
330 void mdio_write(int RegAddr, int value)
334 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
337 for (i = 2000; i > 0; i--) {
338 /* Check if the RTL8169 has completed writing to the specified MII register */
339 if (!(RTL_R32(PHYAR) & 0x80000000)) {
347 int mdio_read(int RegAddr)
351 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
354 for (i = 2000; i > 0; i--) {
355 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
356 if (RTL_R32(PHYAR) & 0x80000000) {
357 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
366 static int rtl8169_init_board(struct eth_device *dev)
372 printf ("%s\n", __FUNCTION__);
374 ioaddr = dev->iobase;
376 /* Soft reset the chip. */
377 RTL_W8(ChipCmd, CmdReset);
379 /* Check that the chip has finished the reset. */
380 for (i = 1000; i > 0; i--)
381 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
386 /* identify chip attached to board */
387 tmp = RTL_R32(TxConfig);
388 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
390 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
391 if (tmp == rtl_chip_info[i].version) {
397 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
398 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
399 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
406 /**************************************************************************
407 RECV - Receive a frame
408 ***************************************************************************/
409 static int rtl_recv(struct eth_device *dev)
411 /* return true if there's an ethernet packet ready to read */
412 /* nic->packet should contain data on return */
413 /* nic->packetlen should contain length of data */
417 #ifdef DEBUG_RTL8169_RX
418 printf ("%s\n", __FUNCTION__);
420 ioaddr = dev->iobase;
422 cur_rx = tpc->cur_rx;
423 flush_cache((unsigned long)&tpc->RxDescArray[cur_rx],
424 sizeof(struct RxDesc));
425 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
426 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
427 unsigned char rxdata[RX_BUF_LEN];
428 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
429 status) & 0x00001FFF) - 4;
431 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
432 NetReceive(rxdata, length);
434 if (cur_rx == NUM_RX_DESC - 1)
435 tpc->RxDescArray[cur_rx].status =
436 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
438 tpc->RxDescArray[cur_rx].status =
439 cpu_to_le32(OWNbit + RX_BUF_SIZE);
440 tpc->RxDescArray[cur_rx].buf_addr =
441 cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]);
442 flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
447 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
448 tpc->cur_rx = cur_rx;
452 ushort sts = RTL_R8(IntrStatus);
453 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
454 udelay(100); /* wait */
456 tpc->cur_rx = cur_rx;
457 return (0); /* initially as this is called to flush the input */
461 /**************************************************************************
462 SEND - Transmit a frame
463 ***************************************************************************/
464 static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
466 /* send the packet to destination */
470 int entry = tpc->cur_tx % NUM_TX_DESC;
474 #ifdef DEBUG_RTL8169_TX
475 int stime = currticks();
476 printf ("%s\n", __FUNCTION__);
477 printf("sending %d bytes\n", len);
480 ioaddr = dev->iobase;
482 /* point to the current txb incase multiple tx_rings are used */
483 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
484 memcpy(ptxb, (char *)packet, (int)length);
485 flush_cache((unsigned long)ptxb, length);
487 while (len < ETH_ZLEN)
490 tpc->TxDescArray[entry].buf_Haddr = 0;
491 tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb);
492 if (entry != (NUM_TX_DESC - 1)) {
493 tpc->TxDescArray[entry].status =
494 cpu_to_le32((OWNbit | FSbit | LSbit) |
495 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
497 tpc->TxDescArray[entry].status =
498 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
499 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
501 RTL_W8(TxPoll, 0x40); /* set polling bit */
504 to = currticks() + TX_TIMEOUT;
506 flush_cache((unsigned long)&tpc->TxDescArray[entry],
507 sizeof(struct TxDesc));
508 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
509 && (currticks() < to)); /* wait */
511 if (currticks() >= to) {
512 #ifdef DEBUG_RTL8169_TX
513 puts ("tx timeout/error\n");
514 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
518 #ifdef DEBUG_RTL8169_TX
523 /* Delay to make net console (nc) work properly */
528 static void rtl8169_set_rx_mode(struct eth_device *dev)
530 u32 mc_filter[2]; /* Multicast hash filter */
535 printf ("%s\n", __FUNCTION__);
539 /* Too many to filter perfectly -- accept all multicasts. */
540 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
541 mc_filter[1] = mc_filter[0] = 0xffffffff;
543 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
544 rtl_chip_info[tpc->chipset].RxConfigMask);
546 RTL_W32(RxConfig, tmp);
547 RTL_W32(MAR0 + 0, mc_filter[0]);
548 RTL_W32(MAR0 + 4, mc_filter[1]);
551 static void rtl8169_hw_start(struct eth_device *dev)
556 int stime = currticks();
557 printf ("%s\n", __FUNCTION__);
561 /* Soft reset the chip. */
562 RTL_W8(ChipCmd, CmdReset);
564 /* Check that the chip has finished the reset. */
565 for (i = 1000; i > 0; i--) {
566 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
573 RTL_W8(Cfg9346, Cfg9346_Unlock);
575 /* RTL-8169sb/8110sb or previous version */
576 if (tpc->chipset <= 5)
577 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
579 RTL_W8(EarlyTxThres, EarlyTxThld);
581 /* For gigabit rtl8169 */
582 RTL_W16(RxMaxSize, RxPacketMaxSize);
584 /* Set Rx Config register */
585 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
586 rtl_chip_info[tpc->chipset].RxConfigMask);
587 RTL_W32(RxConfig, i);
589 /* Set DMA burst size and Interframe Gap Time */
590 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
591 (InterFrameGap << TxInterFrameGapShift));
596 RTL_W32(TxDescStartAddrLow, (unsigned long)tpc->TxDescArray);
597 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
598 RTL_W32(RxDescStartAddrLow, (unsigned long)tpc->RxDescArray);
599 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
601 /* RTL-8169sc/8110sc or later version */
602 if (tpc->chipset > 5)
603 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
605 RTL_W8(Cfg9346, Cfg9346_Lock);
608 RTL_W32(RxMissed, 0);
610 rtl8169_set_rx_mode(dev);
612 /* no early-rx interrupts */
613 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
616 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
620 static void rtl8169_init_ring(struct eth_device *dev)
625 int stime = currticks();
626 printf ("%s\n", __FUNCTION__);
632 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
633 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
635 for (i = 0; i < NUM_TX_DESC; i++) {
636 tpc->Tx_skbuff[i] = &txb[i];
639 for (i = 0; i < NUM_RX_DESC; i++) {
640 if (i == (NUM_RX_DESC - 1))
641 tpc->RxDescArray[i].status =
642 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
644 tpc->RxDescArray[i].status =
645 cpu_to_le32(OWNbit + RX_BUF_SIZE);
647 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
648 tpc->RxDescArray[i].buf_addr =
649 cpu_to_le32((unsigned long)tpc->RxBufferRing[i]);
650 flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
654 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
658 /**************************************************************************
659 RESET - Finish setting up the ethernet interface
660 ***************************************************************************/
661 static int rtl_reset(struct eth_device *dev, bd_t *bis)
666 int stime = currticks();
667 printf ("%s\n", __FUNCTION__);
670 tpc->TxDescArrays = tx_ring;
671 /* Tx Desscriptor needs 256 bytes alignment; */
672 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
675 tpc->RxDescArrays = rx_ring;
676 /* Rx Desscriptor needs 256 bytes alignment; */
677 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
680 rtl8169_init_ring(dev);
681 rtl8169_hw_start(dev);
682 /* Construct a perfect filter frame with the mac address as first match
683 * and broadcast for all others */
684 for (i = 0; i < 192; i++)
687 txb[0] = dev->enetaddr[0];
688 txb[1] = dev->enetaddr[1];
689 txb[2] = dev->enetaddr[2];
690 txb[3] = dev->enetaddr[3];
691 txb[4] = dev->enetaddr[4];
692 txb[5] = dev->enetaddr[5];
695 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
700 /**************************************************************************
701 HALT - Turn off ethernet interface
702 ***************************************************************************/
703 static void rtl_halt(struct eth_device *dev)
708 printf ("%s\n", __FUNCTION__);
711 ioaddr = dev->iobase;
713 /* Stop the chip's Tx and Rx DMA processes. */
714 RTL_W8(ChipCmd, 0x00);
716 /* Disable interrupts by clearing the interrupt mask. */
717 RTL_W16(IntrMask, 0x0000);
719 RTL_W32(RxMissed, 0);
721 tpc->TxDescArrays = NULL;
722 tpc->RxDescArrays = NULL;
723 tpc->TxDescArray = NULL;
724 tpc->RxDescArray = NULL;
725 for (i = 0; i < NUM_RX_DESC; i++) {
726 tpc->RxBufferRing[i] = NULL;
730 /**************************************************************************
731 INIT - Look for an adapter, this routine's visible to the outside
732 ***************************************************************************/
734 #define board_found 1
736 static int rtl_init(struct eth_device *dev, bd_t *bis)
738 static int board_idx = -1;
739 static int printed_version = 0;
741 int option = -1, Cap10_100 = 0, Cap1000 = 0;
744 printf ("%s\n", __FUNCTION__);
747 ioaddr = dev->iobase;
753 /* point to private storage */
756 rc = rtl8169_init_board(dev);
760 /* Get MAC address. FIXME: read EEPROM */
761 for (i = 0; i < MAC_ADDR_LEN; i++)
762 dev->enetaddr[i] = RTL_R8(MAC0 + i);
765 printf("chipset = %d\n", tpc->chipset);
766 printf("MAC Address");
767 for (i = 0; i < MAC_ADDR_LEN; i++)
768 printf(":%02x", dev->enetaddr[i]);
773 /* Print out some hardware info */
774 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
777 /* if TBI is not endbled */
778 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
779 int val = mdio_read(PHY_AUTO_NEGO_REG);
781 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
782 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
785 printf("%s: Force-mode Enabled.\n", dev->name);
787 Cap10_100 = 0, Cap1000 = 0;
790 Cap10_100 = PHY_Cap_10_Half;
791 Cap1000 = PHY_Cap_Null;
794 Cap10_100 = PHY_Cap_10_Full;
795 Cap1000 = PHY_Cap_Null;
798 Cap10_100 = PHY_Cap_100_Half;
799 Cap1000 = PHY_Cap_Null;
802 Cap10_100 = PHY_Cap_100_Full;
803 Cap1000 = PHY_Cap_Null;
806 Cap10_100 = PHY_Cap_Null;
807 Cap1000 = PHY_Cap_1000_Full;
812 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
813 mdio_write(PHY_1000_CTRL_REG, Cap1000);
816 printf("%s: Auto-negotiation Enabled.\n",
819 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
820 mdio_write(PHY_AUTO_NEGO_REG,
821 PHY_Cap_10_Half | PHY_Cap_10_Full |
822 PHY_Cap_100_Half | PHY_Cap_100_Full |
825 /* enable 1000 Full Mode */
826 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
830 /* Enable auto-negotiation and restart auto-nigotiation */
831 mdio_write(PHY_CTRL_REG,
832 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
835 /* wait for auto-negotiation process */
836 for (i = 10000; i > 0; i--) {
837 /* check if auto-negotiation complete */
838 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
840 option = RTL_R8(PHYstatus);
841 if (option & _1000bpsF) {
843 printf("%s: 1000Mbps Full-duplex operation.\n",
848 printf("%s: %sMbps %s-duplex operation.\n",
850 (option & _100bps) ? "100" :
852 (option & FullDup) ? "Full" :
860 } /* end for-loop to wait for auto-negotiation process */
866 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
868 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
875 int rtl8169_initialize(bd_t *bis)
879 struct eth_device *dev;
885 if ((devno = pci_find_devices(supported, idx++)) < 0)
888 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
891 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
893 dev = (struct eth_device *)malloc(sizeof *dev);
895 sprintf (dev->name, "RTL8169#%d", card_number);
897 dev->priv = (void *) devno;
898 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
900 dev->init = rtl_reset;
901 dev->halt = rtl_halt;
902 dev->send = rtl_send;
903 dev->recv = rtl_recv;