2 * rtl8169.c : U-Boot driver for the RealTek RTL8169
4 * Masami Komiya (mkomiya@sonare.it)
6 * Most part is taken from r8169.c of etherboot
10 /**************************************************************************
11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
12 * Written 2003 by Timothy Legge <tlegge@rogers.com>
14 * SPDX-License-Identifier: GPL-2.0+
16 * Portions of this code based on:
17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
18 * for Linux kernel 2.4.x.
20 * Written 2002 ShuChen <shuchen@realtek.com.tw>
21 * See Linux Driver for full information
23 * Linux Driver Version 1.27a, 10.02.2002
26 * Jean Chen of RealTek Semiconductor Corp. for
27 * providing the evaluation NIC used to develop
28 * this driver. RealTek's support for Etherboot
34 * v1.0 11-26-2003 timlegge Initial port of Linux driver
35 * v1.5 01-17-2004 timlegge Initial driver output cleanup
37 * Indent Options: indent -kr -i8
38 ***************************************************************************/
40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
41 * Modified to use le32_to_cpu and cpu_to_le32 properly
51 #undef DEBUG_RTL8169_TX
52 #undef DEBUG_RTL8169_RX
54 #define drv_version "v1.5"
55 #define drv_date "01-17-2004"
59 /* Condensed operations for readability. */
60 #define currticks() get_timer(0)
64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
66 /* MAC address length*/
67 #define MAC_ADDR_LEN 6
69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
70 #define MAX_ETH_FRAME_SIZE 1536
72 #define TX_FIFO_THRESH 256 /* In bytes */
74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
82 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
83 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
84 #define RX_BUF_LEN 8192
86 #define RTL_MIN_IO_SIZE 0x80
87 #define TX_TIMEOUT (6*HZ)
89 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
90 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
91 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
92 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
93 #define RTL_R8(reg) readb (ioaddr + (reg))
94 #define RTL_R16(reg) readw (ioaddr + (reg))
95 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
97 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
98 #define ETH_ALEN MAC_ADDR_LEN
101 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
102 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
104 enum RTL8169_registers {
105 MAC0 = 0, /* Ethernet hardware address. */
106 MAR0 = 8, /* Multicast filter. */
107 TxDescStartAddrLow = 0x20,
108 TxDescStartAddrHigh = 0x24,
109 TxHDescStartAddrLow = 0x28,
110 TxHDescStartAddrHigh = 0x2c,
135 RxDescStartAddrLow = 0xE4,
136 RxDescStartAddrHigh = 0xE8,
139 FuncEventMask = 0xF4,
140 FuncPresetState = 0xF8,
141 FuncForceEvent = 0xFC,
144 enum RTL8169_register_content {
145 /*InterruptStatusBits */
149 TxDescUnavail = 0x80,
172 Cfg9346_Unlock = 0xC0,
177 AcceptBroadcast = 0x08,
178 AcceptMulticast = 0x04,
180 AcceptAllPhys = 0x01,
187 TxInterFrameGapShift = 24,
188 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
190 /*rtl8169_PHYstatus */
200 /*GIGABIT_PHY_registers */
203 PHY_AUTO_NEGO_REG = 4,
204 PHY_1000_CTRL_REG = 9,
206 /*GIGABIT_PHY_REG_BIT */
207 PHY_Restart_Auto_Nego = 0x0200,
208 PHY_Enable_Auto_Nego = 0x1000,
210 /* PHY_STAT_REG = 1; */
211 PHY_Auto_Nego_Comp = 0x0020,
213 /* PHY_AUTO_NEGO_REG = 4; */
214 PHY_Cap_10_Half = 0x0020,
215 PHY_Cap_10_Full = 0x0040,
216 PHY_Cap_100_Half = 0x0080,
217 PHY_Cap_100_Full = 0x0100,
219 /* PHY_1000_CTRL_REG = 9; */
220 PHY_Cap_1000_Full = 0x0200,
232 TBILinkOK = 0x02000000,
237 u8 version; /* depend on RTL8169 docs */
238 u32 RxConfigMask; /* should clear the bits supported by this chip */
239 } rtl_chip_info[] = {
240 {"RTL-8169", 0x00, 0xff7e1880,},
241 {"RTL-8169", 0x04, 0xff7e1880,},
242 {"RTL-8169", 0x00, 0xff7e1880,},
243 {"RTL-8169s/8110s", 0x02, 0xff7e1880,},
244 {"RTL-8169s/8110s", 0x04, 0xff7e1880,},
245 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
246 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
247 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
248 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
249 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,},
250 {"RTL-8101e", 0x34, 0xff7e1880,},
251 {"RTL-8100e", 0x32, 0xff7e1880,},
254 enum _DescStatusBit {
275 /* Define the TX Descriptor */
276 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
277 /* __attribute__ ((aligned(256))); */
279 /* Create a static buffer of size RX_BUF_SZ for each
280 TX Descriptor. All descriptors point to a
281 part of this buffer */
282 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
284 /* Define the RX Descriptor */
285 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
286 /* __attribute__ ((aligned(256))); */
288 /* Create a static buffer of size RX_BUF_SZ for each
289 RX Descriptor All descriptors point to a
290 part of this buffer */
291 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
293 struct rtl8169_private {
294 void *mmio_addr; /* memory map physical address */
296 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
297 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
298 unsigned long dirty_tx;
299 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
300 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
301 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
302 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
303 unsigned char *RxBufferRings; /* Index of Rx Buffer */
304 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
305 unsigned char *Tx_skbuff[NUM_TX_DESC];
308 static struct rtl8169_private *tpc;
310 static const u16 rtl8169_intr_mask =
311 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
313 static const unsigned int rtl8169_rx_config =
314 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
316 static struct pci_device_id supported[] = {
317 {PCI_VENDOR_ID_REALTEK, 0x8167},
318 {PCI_VENDOR_ID_REALTEK, 0x8169},
322 void mdio_write(int RegAddr, int value)
326 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
329 for (i = 2000; i > 0; i--) {
330 /* Check if the RTL8169 has completed writing to the specified MII register */
331 if (!(RTL_R32(PHYAR) & 0x80000000)) {
339 int mdio_read(int RegAddr)
343 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
346 for (i = 2000; i > 0; i--) {
347 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
348 if (RTL_R32(PHYAR) & 0x80000000) {
349 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
358 static int rtl8169_init_board(struct eth_device *dev)
364 printf ("%s\n", __FUNCTION__);
366 ioaddr = dev->iobase;
368 /* Soft reset the chip. */
369 RTL_W8(ChipCmd, CmdReset);
371 /* Check that the chip has finished the reset. */
372 for (i = 1000; i > 0; i--)
373 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
378 /* identify chip attached to board */
379 tmp = RTL_R32(TxConfig);
380 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
382 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
383 if (tmp == rtl_chip_info[i].version) {
389 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
390 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
391 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
398 /**************************************************************************
399 RECV - Receive a frame
400 ***************************************************************************/
401 static int rtl_recv(struct eth_device *dev)
403 /* return true if there's an ethernet packet ready to read */
404 /* nic->packet should contain data on return */
405 /* nic->packetlen should contain length of data */
409 #ifdef DEBUG_RTL8169_RX
410 printf ("%s\n", __FUNCTION__);
412 ioaddr = dev->iobase;
414 cur_rx = tpc->cur_rx;
415 flush_cache((unsigned long)&tpc->RxDescArray[cur_rx],
416 sizeof(struct RxDesc));
417 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
418 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
419 unsigned char rxdata[RX_BUF_LEN];
420 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
421 status) & 0x00001FFF) - 4;
423 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
424 NetReceive(rxdata, length);
426 if (cur_rx == NUM_RX_DESC - 1)
427 tpc->RxDescArray[cur_rx].status =
428 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
430 tpc->RxDescArray[cur_rx].status =
431 cpu_to_le32(OWNbit + RX_BUF_SIZE);
432 tpc->RxDescArray[cur_rx].buf_addr =
433 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
434 flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
439 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
440 tpc->cur_rx = cur_rx;
444 ushort sts = RTL_R8(IntrStatus);
445 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
446 udelay(100); /* wait */
448 tpc->cur_rx = cur_rx;
449 return (0); /* initially as this is called to flush the input */
453 /**************************************************************************
454 SEND - Transmit a frame
455 ***************************************************************************/
456 static int rtl_send(struct eth_device *dev, void *packet, int length)
458 /* send the packet to destination */
462 int entry = tpc->cur_tx % NUM_TX_DESC;
466 #ifdef DEBUG_RTL8169_TX
467 int stime = currticks();
468 printf ("%s\n", __FUNCTION__);
469 printf("sending %d bytes\n", len);
472 ioaddr = dev->iobase;
474 /* point to the current txb incase multiple tx_rings are used */
475 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
476 memcpy(ptxb, (char *)packet, (int)length);
477 flush_cache((unsigned long)ptxb, length);
479 while (len < ETH_ZLEN)
482 tpc->TxDescArray[entry].buf_Haddr = 0;
483 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb));
484 if (entry != (NUM_TX_DESC - 1)) {
485 tpc->TxDescArray[entry].status =
486 cpu_to_le32((OWNbit | FSbit | LSbit) |
487 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
489 tpc->TxDescArray[entry].status =
490 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
491 ((len > ETH_ZLEN) ? len : ETH_ZLEN));
493 RTL_W8(TxPoll, 0x40); /* set polling bit */
496 to = currticks() + TX_TIMEOUT;
498 flush_cache((unsigned long)&tpc->TxDescArray[entry],
499 sizeof(struct TxDesc));
500 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
501 && (currticks() < to)); /* wait */
503 if (currticks() >= to) {
504 #ifdef DEBUG_RTL8169_TX
505 puts("tx timeout/error\n");
506 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
510 #ifdef DEBUG_RTL8169_TX
515 /* Delay to make net console (nc) work properly */
520 static void rtl8169_set_rx_mode(struct eth_device *dev)
522 u32 mc_filter[2]; /* Multicast hash filter */
527 printf ("%s\n", __FUNCTION__);
531 /* Too many to filter perfectly -- accept all multicasts. */
532 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
533 mc_filter[1] = mc_filter[0] = 0xffffffff;
535 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
536 rtl_chip_info[tpc->chipset].RxConfigMask);
538 RTL_W32(RxConfig, tmp);
539 RTL_W32(MAR0 + 0, mc_filter[0]);
540 RTL_W32(MAR0 + 4, mc_filter[1]);
543 static void rtl8169_hw_start(struct eth_device *dev)
548 int stime = currticks();
549 printf ("%s\n", __FUNCTION__);
553 /* Soft reset the chip. */
554 RTL_W8(ChipCmd, CmdReset);
556 /* Check that the chip has finished the reset. */
557 for (i = 1000; i > 0; i--) {
558 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
565 RTL_W8(Cfg9346, Cfg9346_Unlock);
567 /* RTL-8169sb/8110sb or previous version */
568 if (tpc->chipset <= 5)
569 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
571 RTL_W8(EarlyTxThres, EarlyTxThld);
573 /* For gigabit rtl8169 */
574 RTL_W16(RxMaxSize, RxPacketMaxSize);
576 /* Set Rx Config register */
577 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
578 rtl_chip_info[tpc->chipset].RxConfigMask);
579 RTL_W32(RxConfig, i);
581 /* Set DMA burst size and Interframe Gap Time */
582 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
583 (InterFrameGap << TxInterFrameGapShift));
588 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray));
589 RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
590 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray));
591 RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
593 /* RTL-8169sc/8110sc or later version */
594 if (tpc->chipset > 5)
595 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
597 RTL_W8(Cfg9346, Cfg9346_Lock);
600 RTL_W32(RxMissed, 0);
602 rtl8169_set_rx_mode(dev);
604 /* no early-rx interrupts */
605 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
608 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
612 static void rtl8169_init_ring(struct eth_device *dev)
617 int stime = currticks();
618 printf ("%s\n", __FUNCTION__);
624 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
625 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
627 for (i = 0; i < NUM_TX_DESC; i++) {
628 tpc->Tx_skbuff[i] = &txb[i];
631 for (i = 0; i < NUM_RX_DESC; i++) {
632 if (i == (NUM_RX_DESC - 1))
633 tpc->RxDescArray[i].status =
634 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
636 tpc->RxDescArray[i].status =
637 cpu_to_le32(OWNbit + RX_BUF_SIZE);
639 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
640 tpc->RxDescArray[i].buf_addr =
641 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
642 flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
646 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
650 /**************************************************************************
651 RESET - Finish setting up the ethernet interface
652 ***************************************************************************/
653 static int rtl_reset(struct eth_device *dev, bd_t *bis)
658 int stime = currticks();
659 printf ("%s\n", __FUNCTION__);
662 tpc->TxDescArrays = tx_ring;
663 /* Tx Desscriptor needs 256 bytes alignment; */
664 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
667 tpc->RxDescArrays = rx_ring;
668 /* Rx Desscriptor needs 256 bytes alignment; */
669 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
672 rtl8169_init_ring(dev);
673 rtl8169_hw_start(dev);
674 /* Construct a perfect filter frame with the mac address as first match
675 * and broadcast for all others */
676 for (i = 0; i < 192; i++)
679 txb[0] = dev->enetaddr[0];
680 txb[1] = dev->enetaddr[1];
681 txb[2] = dev->enetaddr[2];
682 txb[3] = dev->enetaddr[3];
683 txb[4] = dev->enetaddr[4];
684 txb[5] = dev->enetaddr[5];
687 printf("%s elapsed time : %lu\n", __func__, currticks()-stime);
692 /**************************************************************************
693 HALT - Turn off ethernet interface
694 ***************************************************************************/
695 static void rtl_halt(struct eth_device *dev)
700 printf ("%s\n", __FUNCTION__);
703 ioaddr = dev->iobase;
705 /* Stop the chip's Tx and Rx DMA processes. */
706 RTL_W8(ChipCmd, 0x00);
708 /* Disable interrupts by clearing the interrupt mask. */
709 RTL_W16(IntrMask, 0x0000);
711 RTL_W32(RxMissed, 0);
713 tpc->TxDescArrays = NULL;
714 tpc->RxDescArrays = NULL;
715 tpc->TxDescArray = NULL;
716 tpc->RxDescArray = NULL;
717 for (i = 0; i < NUM_RX_DESC; i++) {
718 tpc->RxBufferRing[i] = NULL;
722 /**************************************************************************
723 INIT - Look for an adapter, this routine's visible to the outside
724 ***************************************************************************/
726 #define board_found 1
728 static int rtl_init(struct eth_device *dev, bd_t *bis)
730 static int board_idx = -1;
732 int option = -1, Cap10_100 = 0, Cap1000 = 0;
735 printf ("%s\n", __FUNCTION__);
738 ioaddr = dev->iobase;
742 /* point to private storage */
745 rc = rtl8169_init_board(dev);
749 /* Get MAC address. FIXME: read EEPROM */
750 for (i = 0; i < MAC_ADDR_LEN; i++)
751 dev->enetaddr[i] = RTL_R8(MAC0 + i);
754 printf("chipset = %d\n", tpc->chipset);
755 printf("MAC Address");
756 for (i = 0; i < MAC_ADDR_LEN; i++)
757 printf(":%02x", dev->enetaddr[i]);
762 /* Print out some hardware info */
763 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
766 /* if TBI is not endbled */
767 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
768 int val = mdio_read(PHY_AUTO_NEGO_REG);
770 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
771 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
774 printf("%s: Force-mode Enabled.\n", dev->name);
776 Cap10_100 = 0, Cap1000 = 0;
779 Cap10_100 = PHY_Cap_10_Half;
780 Cap1000 = PHY_Cap_Null;
783 Cap10_100 = PHY_Cap_10_Full;
784 Cap1000 = PHY_Cap_Null;
787 Cap10_100 = PHY_Cap_100_Half;
788 Cap1000 = PHY_Cap_Null;
791 Cap10_100 = PHY_Cap_100_Full;
792 Cap1000 = PHY_Cap_Null;
795 Cap10_100 = PHY_Cap_Null;
796 Cap1000 = PHY_Cap_1000_Full;
801 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
802 mdio_write(PHY_1000_CTRL_REG, Cap1000);
805 printf("%s: Auto-negotiation Enabled.\n",
808 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
809 mdio_write(PHY_AUTO_NEGO_REG,
810 PHY_Cap_10_Half | PHY_Cap_10_Full |
811 PHY_Cap_100_Half | PHY_Cap_100_Full |
814 /* enable 1000 Full Mode */
815 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
819 /* Enable auto-negotiation and restart auto-nigotiation */
820 mdio_write(PHY_CTRL_REG,
821 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
824 /* wait for auto-negotiation process */
825 for (i = 10000; i > 0; i--) {
826 /* check if auto-negotiation complete */
827 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
829 option = RTL_R8(PHYstatus);
830 if (option & _1000bpsF) {
832 printf("%s: 1000Mbps Full-duplex operation.\n",
837 printf("%s: %sMbps %s-duplex operation.\n",
839 (option & _100bps) ? "100" :
841 (option & FullDup) ? "Full" :
849 } /* end for-loop to wait for auto-negotiation process */
855 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
857 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
864 int rtl8169_initialize(bd_t *bis)
868 struct eth_device *dev;
874 if ((devno = pci_find_devices(supported, idx++)) < 0)
877 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
880 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
882 dev = (struct eth_device *)malloc(sizeof *dev);
884 printf("Can not allocate memory of rtl8169\n");
888 memset(dev, 0, sizeof(*dev));
889 sprintf (dev->name, "RTL8169#%d", card_number);
891 dev->priv = (void *) devno;
892 dev->iobase = (int)pci_mem_to_phys(devno, iobase);
894 dev->init = rtl_reset;
895 dev->halt = rtl_halt;
896 dev->send = rtl_send;
897 dev->recv = rtl_recv;