3 * This file is driver for Renesas Ethernet AVB.
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
7 * Based on the SuperH Ethernet driver.
9 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mii.h>
22 #define RAVB_REG_CCC 0x000
23 #define RAVB_REG_DBAT 0x004
24 #define RAVB_REG_CSR 0x00C
25 #define RAVB_REG_APSR 0x08C
26 #define RAVB_REG_RCR 0x090
27 #define RAVB_REG_TGC 0x300
28 #define RAVB_REG_TCCR 0x304
29 #define RAVB_REG_RIC0 0x360
30 #define RAVB_REG_RIC1 0x368
31 #define RAVB_REG_RIC2 0x370
32 #define RAVB_REG_TIC 0x378
33 #define RAVB_REG_ECMR 0x500
34 #define RAVB_REG_RFLR 0x508
35 #define RAVB_REG_ECSIPR 0x518
36 #define RAVB_REG_PIR 0x520
37 #define RAVB_REG_GECMR 0x5b0
38 #define RAVB_REG_MAHR 0x5c0
39 #define RAVB_REG_MALR 0x5c8
41 #define CCC_OPC_CONFIG BIT(0)
42 #define CCC_OPC_OPERATION BIT(1)
43 #define CCC_BOC BIT(20)
45 #define CSR_OPS 0x0000000F
46 #define CSR_OPS_CONFIG BIT(1)
48 #define TCCR_TSRQ0 BIT(0)
50 #define RFLR_RFL_MIN 0x05EE
52 #define PIR_MDI BIT(3)
53 #define PIR_MDO BIT(2)
54 #define PIR_MMD BIT(1)
55 #define PIR_MDC BIT(0)
57 #define ECMR_TRCCM BIT(26)
58 #define ECMR_RZPF BIT(20)
59 #define ECMR_PFR BIT(18)
60 #define ECMR_RXF BIT(17)
61 #define ECMR_RE BIT(6)
62 #define ECMR_TE BIT(5)
63 #define ECMR_DM BIT(1)
64 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
67 #define RAVB_NUM_BASE_DESC 16
68 #define RAVB_NUM_TX_DESC 8
69 #define RAVB_NUM_RX_DESC 8
71 #define RAVB_TX_QUEUE_OFFSET 0
72 #define RAVB_RX_QUEUE_OFFSET 4
74 #define RAVB_DESC_DT(n) ((n) << 28)
75 #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
76 #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
77 #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
78 #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
79 #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
80 #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
82 #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
83 #define RAVB_DESC_DS_MASK 0xfff
85 #define RAVB_RX_DESC_MSC_MC BIT(23)
86 #define RAVB_RX_DESC_MSC_CEEF BIT(22)
87 #define RAVB_RX_DESC_MSC_CRL BIT(21)
88 #define RAVB_RX_DESC_MSC_FRE BIT(20)
89 #define RAVB_RX_DESC_MSC_RTLF BIT(19)
90 #define RAVB_RX_DESC_MSC_RTSF BIT(18)
91 #define RAVB_RX_DESC_MSC_RFE BIT(17)
92 #define RAVB_RX_DESC_MSC_CRC BIT(16)
93 #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
95 #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
96 (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
97 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
99 #define RAVB_TX_TIMEOUT_MS 1000
107 struct ravb_desc data;
108 struct ravb_desc link;
110 u8 packet[PKTSIZE_ALIGN];
114 struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
115 struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
116 struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
120 struct phy_device *phydev;
122 void __iomem *iobase;
125 static inline void ravb_flush_dcache(u32 addr, u32 len)
127 flush_dcache_range(addr, addr + len);
130 static inline void ravb_invalidate_dcache(u32 addr, u32 len)
132 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
133 u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
134 invalidate_dcache_range(start, end);
137 static int ravb_send(struct udevice *dev, void *packet, int len)
139 struct ravb_priv *eth = dev_get_priv(dev);
140 struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx];
143 /* Update TX descriptor */
144 ravb_flush_dcache((uintptr_t)packet, len);
145 memset(desc, 0x0, sizeof(*desc));
146 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
147 desc->dptr = (uintptr_t)packet;
148 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
150 /* Restart the transmitter if disabled */
151 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
152 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
154 /* Wait until packet is transmitted */
155 start = get_timer(0);
156 while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
157 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
158 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
163 if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
166 eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
170 static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
172 struct ravb_priv *eth = dev_get_priv(dev);
173 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
177 /* Check if the rx descriptor is ready */
178 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
179 if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
182 /* Check for errors */
183 if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
184 desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
188 len = desc->data.ctrl & RAVB_DESC_DS_MASK;
189 packet = (u8 *)(uintptr_t)desc->data.dptr;
190 ravb_invalidate_dcache((uintptr_t)packet, len);
196 static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
198 struct ravb_priv *eth = dev_get_priv(dev);
199 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
201 /* Make current descriptor available again */
202 desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
203 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
205 /* Point to the next descriptor */
206 eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
207 desc = ð->rx_desc[eth->rx_desc_idx];
208 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
213 static int ravb_reset(struct udevice *dev)
215 struct ravb_priv *eth = dev_get_priv(dev);
217 /* Set config mode */
218 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
220 /* Check the operating mode is changed to the config mode. */
221 return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
222 CSR_OPS_CONFIG, true, 100, true);
225 static void ravb_base_desc_init(struct ravb_priv *eth)
227 const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
230 /* Initialize all descriptors */
231 memset(eth->base_desc, 0x0, desc_size);
233 for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
234 eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
236 ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
238 /* Register the descriptor base address table */
239 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
242 static void ravb_tx_desc_init(struct ravb_priv *eth)
244 const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
247 /* Initialize all descriptors */
248 memset(eth->tx_desc, 0x0, desc_size);
249 eth->tx_desc_idx = 0;
251 for (i = 0; i < RAVB_NUM_TX_DESC; i++)
252 eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
254 /* Mark the end of the descriptors */
255 eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
256 eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
257 ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
259 /* Point the controller to the TX descriptor list. */
260 eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
261 eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
262 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET],
263 sizeof(struct ravb_desc));
266 static void ravb_rx_desc_init(struct ravb_priv *eth)
268 const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
271 /* Initialize all descriptors */
272 memset(eth->rx_desc, 0x0, desc_size);
273 eth->rx_desc_idx = 0;
275 for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
276 eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
277 RAVB_DESC_DS(PKTSIZE_ALIGN);
278 eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
280 eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
281 eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1];
284 /* Mark the end of the descriptors */
285 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
286 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
287 ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
289 /* Point the controller to the rx descriptor list */
290 eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
291 eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
292 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET],
293 sizeof(struct ravb_desc));
296 static int ravb_phy_config(struct udevice *dev)
298 struct ravb_priv *eth = dev_get_priv(dev);
299 struct eth_pdata *pdata = dev_get_platdata(dev);
300 struct phy_device *phydev;
303 phydev = phy_connect(eth->bus, pdata->phy_interface,
304 dev, PHY_INTERFACE_MODE_RGMII_ID);
308 eth->phydev = phydev;
310 /* 10BASE is not supported for Ethernet AVB MAC */
311 phydev->supported &= ~(SUPPORTED_10baseT_Full
312 | SUPPORTED_10baseT_Half);
313 if (pdata->max_speed != 1000) {
314 phydev->supported &= ~(SUPPORTED_1000baseT_Half
315 | SUPPORTED_1000baseT_Full);
316 reg = phy_read(phydev, -1, MII_CTRL1000);
317 reg &= ~(BIT(9) | BIT(8));
318 phy_write(phydev, -1, MII_CTRL1000, reg);
326 /* Set Mac address */
327 static int ravb_write_hwaddr(struct udevice *dev)
329 struct ravb_priv *eth = dev_get_priv(dev);
330 struct eth_pdata *pdata = dev_get_platdata(dev);
331 unsigned char *mac = pdata->enetaddr;
333 writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
334 eth->iobase + RAVB_REG_MAHR);
336 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
341 /* E-MAC init function */
342 static int ravb_mac_init(struct ravb_priv *eth)
344 /* Disable MAC Interrupt */
345 writel(0, eth->iobase + RAVB_REG_ECSIPR);
347 /* Recv frame limit set register */
348 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
353 /* AVB-DMAC init function */
354 static int ravb_dmac_init(struct udevice *dev)
356 struct ravb_priv *eth = dev_get_priv(dev);
357 struct eth_pdata *pdata = dev_get_platdata(dev);
360 /* Set CONFIG mode */
361 ret = ravb_reset(dev);
365 /* Disable all interrupts */
366 writel(0, eth->iobase + RAVB_REG_RIC0);
367 writel(0, eth->iobase + RAVB_REG_RIC1);
368 writel(0, eth->iobase + RAVB_REG_RIC2);
369 writel(0, eth->iobase + RAVB_REG_TIC);
371 /* Set little endian */
372 clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
375 writel(0x18000001, eth->iobase + RAVB_REG_RCR);
378 writel(0x00222210, eth->iobase + RAVB_REG_TGC);
381 if (pdata->max_speed == 1000)
382 writel(BIT(14), eth->iobase + RAVB_REG_APSR);
387 static int ravb_config(struct udevice *dev)
389 struct ravb_priv *eth = dev_get_priv(dev);
390 struct phy_device *phy;
391 u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
394 /* Configure AVB-DMAC register */
397 /* Configure E-MAC registers */
399 ravb_write_hwaddr(dev);
402 ret = ravb_phy_config(dev);
408 ret = phy_startup(phy);
412 /* Set the transfer speed */
413 if (phy->speed == 100)
414 writel(0, eth->iobase + RAVB_REG_GECMR);
415 else if (phy->speed == 1000)
416 writel(1, eth->iobase + RAVB_REG_GECMR);
418 /* Check if full duplex mode is supported by the phy */
422 writel(mask, eth->iobase + RAVB_REG_ECMR);
424 phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
429 int ravb_start(struct udevice *dev)
431 struct ravb_priv *eth = dev_get_priv(dev);
434 ret = ravb_reset(dev);
438 ravb_base_desc_init(eth);
439 ravb_tx_desc_init(eth);
440 ravb_rx_desc_init(eth);
442 ret = ravb_config(dev);
446 /* Setting the control will start the AVB-DMAC process. */
447 writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
452 static void ravb_stop(struct udevice *dev)
457 static int ravb_probe(struct udevice *dev)
459 struct eth_pdata *pdata = dev_get_platdata(dev);
460 struct ravb_priv *eth = dev_get_priv(dev);
461 struct mii_dev *mdiodev;
462 void __iomem *iobase;
465 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
466 eth->iobase = iobase;
468 mdiodev = mdio_alloc();
474 mdiodev->read = bb_miiphy_read;
475 mdiodev->write = bb_miiphy_write;
476 bb_miiphy_buses[0].priv = eth;
477 snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
479 ret = mdio_register(mdiodev);
481 goto err_mdio_register;
483 eth->bus = miiphy_get_dev_by_name(dev->name);
490 unmap_physmem(eth->iobase, MAP_NOCACHE);
494 static int ravb_remove(struct udevice *dev)
496 struct ravb_priv *eth = dev_get_priv(dev);
499 mdio_unregister(eth->bus);
501 unmap_physmem(eth->iobase, MAP_NOCACHE);
506 int ravb_bb_init(struct bb_miiphy_bus *bus)
511 int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
513 struct ravb_priv *eth = bus->priv;
515 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
520 int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
522 struct ravb_priv *eth = bus->priv;
524 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
529 int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
531 struct ravb_priv *eth = bus->priv;
534 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
536 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
541 int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
543 struct ravb_priv *eth = bus->priv;
545 *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
550 int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
552 struct ravb_priv *eth = bus->priv;
555 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
557 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
562 int ravb_bb_delay(struct bb_miiphy_bus *bus)
569 struct bb_miiphy_bus bb_miiphy_buses[] = {
572 .init = ravb_bb_init,
573 .mdio_active = ravb_bb_mdio_active,
574 .mdio_tristate = ravb_bb_mdio_tristate,
575 .set_mdio = ravb_bb_set_mdio,
576 .get_mdio = ravb_bb_get_mdio,
577 .set_mdc = ravb_bb_set_mdc,
578 .delay = ravb_bb_delay,
581 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
583 static const struct eth_ops ravb_ops = {
587 .free_pkt = ravb_free_pkt,
589 .write_hwaddr = ravb_write_hwaddr,
592 U_BOOT_DRIVER(eth_ravb) = {
596 .remove = ravb_remove,
598 .priv_auto_alloc_size = sizeof(struct ravb_priv),
599 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
600 .flags = DM_FLAG_ALLOC_PRIV_DMA,