3 * This file is driver for Renesas Ethernet AVB.
5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
7 * Based on the SuperH Ethernet driver.
9 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mii.h>
23 #define RAVB_REG_CCC 0x000
24 #define RAVB_REG_DBAT 0x004
25 #define RAVB_REG_CSR 0x00C
26 #define RAVB_REG_APSR 0x08C
27 #define RAVB_REG_RCR 0x090
28 #define RAVB_REG_TGC 0x300
29 #define RAVB_REG_TCCR 0x304
30 #define RAVB_REG_RIC0 0x360
31 #define RAVB_REG_RIC1 0x368
32 #define RAVB_REG_RIC2 0x370
33 #define RAVB_REG_TIC 0x378
34 #define RAVB_REG_ECMR 0x500
35 #define RAVB_REG_RFLR 0x508
36 #define RAVB_REG_ECSIPR 0x518
37 #define RAVB_REG_PIR 0x520
38 #define RAVB_REG_GECMR 0x5b0
39 #define RAVB_REG_MAHR 0x5c0
40 #define RAVB_REG_MALR 0x5c8
42 #define CCC_OPC_CONFIG BIT(0)
43 #define CCC_OPC_OPERATION BIT(1)
44 #define CCC_BOC BIT(20)
46 #define CSR_OPS 0x0000000F
47 #define CSR_OPS_CONFIG BIT(1)
49 #define TCCR_TSRQ0 BIT(0)
51 #define RFLR_RFL_MIN 0x05EE
53 #define PIR_MDI BIT(3)
54 #define PIR_MDO BIT(2)
55 #define PIR_MMD BIT(1)
56 #define PIR_MDC BIT(0)
58 #define ECMR_TRCCM BIT(26)
59 #define ECMR_RZPF BIT(20)
60 #define ECMR_PFR BIT(18)
61 #define ECMR_RXF BIT(17)
62 #define ECMR_RE BIT(6)
63 #define ECMR_TE BIT(5)
64 #define ECMR_DM BIT(1)
65 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
68 #define RAVB_NUM_BASE_DESC 16
69 #define RAVB_NUM_TX_DESC 8
70 #define RAVB_NUM_RX_DESC 8
72 #define RAVB_TX_QUEUE_OFFSET 0
73 #define RAVB_RX_QUEUE_OFFSET 4
75 #define RAVB_DESC_DT(n) ((n) << 28)
76 #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
77 #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
78 #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
79 #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
80 #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
81 #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
83 #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
84 #define RAVB_DESC_DS_MASK 0xfff
86 #define RAVB_RX_DESC_MSC_MC BIT(23)
87 #define RAVB_RX_DESC_MSC_CEEF BIT(22)
88 #define RAVB_RX_DESC_MSC_CRL BIT(21)
89 #define RAVB_RX_DESC_MSC_FRE BIT(20)
90 #define RAVB_RX_DESC_MSC_RTLF BIT(19)
91 #define RAVB_RX_DESC_MSC_RTSF BIT(18)
92 #define RAVB_RX_DESC_MSC_RFE BIT(17)
93 #define RAVB_RX_DESC_MSC_CRC BIT(16)
94 #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
96 #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
97 (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
98 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
100 #define RAVB_TX_TIMEOUT_MS 1000
108 struct ravb_desc data;
109 struct ravb_desc link;
111 u8 packet[PKTSIZE_ALIGN];
115 struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
116 struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
117 struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
121 struct phy_device *phydev;
123 void __iomem *iobase;
127 static inline void ravb_flush_dcache(u32 addr, u32 len)
129 flush_dcache_range(addr, addr + len);
132 static inline void ravb_invalidate_dcache(u32 addr, u32 len)
134 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
135 u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
136 invalidate_dcache_range(start, end);
139 static int ravb_send(struct udevice *dev, void *packet, int len)
141 struct ravb_priv *eth = dev_get_priv(dev);
142 struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx];
145 /* Update TX descriptor */
146 ravb_flush_dcache((uintptr_t)packet, len);
147 memset(desc, 0x0, sizeof(*desc));
148 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
149 desc->dptr = (uintptr_t)packet;
150 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
152 /* Restart the transmitter if disabled */
153 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
154 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
156 /* Wait until packet is transmitted */
157 start = get_timer(0);
158 while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
159 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
160 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
165 if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
168 eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
172 static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
174 struct ravb_priv *eth = dev_get_priv(dev);
175 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
179 /* Check if the rx descriptor is ready */
180 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
181 if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
184 /* Check for errors */
185 if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
186 desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
190 len = desc->data.ctrl & RAVB_DESC_DS_MASK;
191 packet = (u8 *)(uintptr_t)desc->data.dptr;
192 ravb_invalidate_dcache((uintptr_t)packet, len);
198 static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
200 struct ravb_priv *eth = dev_get_priv(dev);
201 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
203 /* Make current descriptor available again */
204 desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
205 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
207 /* Point to the next descriptor */
208 eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
209 desc = ð->rx_desc[eth->rx_desc_idx];
210 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
215 static int ravb_reset(struct udevice *dev)
217 struct ravb_priv *eth = dev_get_priv(dev);
219 /* Set config mode */
220 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
222 /* Check the operating mode is changed to the config mode. */
223 return wait_for_bit(dev->name, (void *)eth->iobase + RAVB_REG_CSR,
224 CSR_OPS_CONFIG, true, 100, true);
227 static void ravb_base_desc_init(struct ravb_priv *eth)
229 const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
232 /* Initialize all descriptors */
233 memset(eth->base_desc, 0x0, desc_size);
235 for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
236 eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
238 ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
240 /* Register the descriptor base address table */
241 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
244 static void ravb_tx_desc_init(struct ravb_priv *eth)
246 const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
249 /* Initialize all descriptors */
250 memset(eth->tx_desc, 0x0, desc_size);
251 eth->tx_desc_idx = 0;
253 for (i = 0; i < RAVB_NUM_TX_DESC; i++)
254 eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
256 /* Mark the end of the descriptors */
257 eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
258 eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
259 ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
261 /* Point the controller to the TX descriptor list. */
262 eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
263 eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
264 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET],
265 sizeof(struct ravb_desc));
268 static void ravb_rx_desc_init(struct ravb_priv *eth)
270 const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
273 /* Initialize all descriptors */
274 memset(eth->rx_desc, 0x0, desc_size);
275 eth->rx_desc_idx = 0;
277 for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
278 eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
279 RAVB_DESC_DS(PKTSIZE_ALIGN);
280 eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
282 eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
283 eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1];
286 /* Mark the end of the descriptors */
287 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
288 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
289 ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
291 /* Point the controller to the rx descriptor list */
292 eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
293 eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
294 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET],
295 sizeof(struct ravb_desc));
298 static int ravb_phy_config(struct udevice *dev)
300 struct ravb_priv *eth = dev_get_priv(dev);
301 struct eth_pdata *pdata = dev_get_platdata(dev);
302 struct phy_device *phydev;
303 int mask = 0xffffffff, reg;
305 phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
309 phy_connect_dev(phydev, dev);
311 eth->phydev = phydev;
313 /* 10BASE is not supported for Ethernet AVB MAC */
314 phydev->supported &= ~(SUPPORTED_10baseT_Full
315 | SUPPORTED_10baseT_Half);
316 if (pdata->max_speed != 1000) {
317 phydev->supported &= ~(SUPPORTED_1000baseT_Half
318 | SUPPORTED_1000baseT_Full);
319 reg = phy_read(phydev, -1, MII_CTRL1000);
320 reg &= ~(BIT(9) | BIT(8));
321 phy_write(phydev, -1, MII_CTRL1000, reg);
329 /* Set Mac address */
330 static int ravb_write_hwaddr(struct udevice *dev)
332 struct ravb_priv *eth = dev_get_priv(dev);
333 struct eth_pdata *pdata = dev_get_platdata(dev);
334 unsigned char *mac = pdata->enetaddr;
336 writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
337 eth->iobase + RAVB_REG_MAHR);
339 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
344 /* E-MAC init function */
345 static int ravb_mac_init(struct ravb_priv *eth)
347 /* Disable MAC Interrupt */
348 writel(0, eth->iobase + RAVB_REG_ECSIPR);
350 /* Recv frame limit set register */
351 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
356 /* AVB-DMAC init function */
357 static int ravb_dmac_init(struct udevice *dev)
359 struct ravb_priv *eth = dev_get_priv(dev);
360 struct eth_pdata *pdata = dev_get_platdata(dev);
363 /* Set CONFIG mode */
364 ret = ravb_reset(dev);
368 /* Disable all interrupts */
369 writel(0, eth->iobase + RAVB_REG_RIC0);
370 writel(0, eth->iobase + RAVB_REG_RIC1);
371 writel(0, eth->iobase + RAVB_REG_RIC2);
372 writel(0, eth->iobase + RAVB_REG_TIC);
374 /* Set little endian */
375 clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
378 writel(0x18000001, eth->iobase + RAVB_REG_RCR);
381 writel(0x00222210, eth->iobase + RAVB_REG_TGC);
384 if (pdata->max_speed == 1000)
385 writel(BIT(14), eth->iobase + RAVB_REG_APSR);
390 static int ravb_config(struct udevice *dev)
392 struct ravb_priv *eth = dev_get_priv(dev);
393 struct phy_device *phy;
394 u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
397 /* Configure AVB-DMAC register */
400 /* Configure E-MAC registers */
402 ravb_write_hwaddr(dev);
405 ret = ravb_phy_config(dev);
411 ret = phy_startup(phy);
415 /* Set the transfer speed */
416 if (phy->speed == 100)
417 writel(0, eth->iobase + RAVB_REG_GECMR);
418 else if (phy->speed == 1000)
419 writel(1, eth->iobase + RAVB_REG_GECMR);
421 /* Check if full duplex mode is supported by the phy */
425 writel(mask, eth->iobase + RAVB_REG_ECMR);
427 phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);
432 int ravb_start(struct udevice *dev)
434 struct ravb_priv *eth = dev_get_priv(dev);
437 ret = clk_enable(ð->clk);
441 ret = ravb_reset(dev);
445 ravb_base_desc_init(eth);
446 ravb_tx_desc_init(eth);
447 ravb_rx_desc_init(eth);
449 ret = ravb_config(dev);
453 /* Setting the control will start the AVB-DMAC process. */
454 writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
459 clk_disable(ð->clk);
463 static void ravb_stop(struct udevice *dev)
465 struct ravb_priv *eth = dev_get_priv(dev);
468 clk_disable(ð->clk);
471 static int ravb_probe(struct udevice *dev)
473 struct eth_pdata *pdata = dev_get_platdata(dev);
474 struct ravb_priv *eth = dev_get_priv(dev);
475 struct mii_dev *mdiodev;
476 void __iomem *iobase;
479 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
480 eth->iobase = iobase;
482 ret = clk_get_by_index(dev, 0, ð->clk);
486 mdiodev = mdio_alloc();
492 mdiodev->read = bb_miiphy_read;
493 mdiodev->write = bb_miiphy_write;
494 bb_miiphy_buses[0].priv = eth;
495 snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
497 ret = mdio_register(mdiodev);
499 goto err_mdio_register;
501 eth->bus = miiphy_get_dev_by_name(dev->name);
508 unmap_physmem(eth->iobase, MAP_NOCACHE);
512 static int ravb_remove(struct udevice *dev)
514 struct ravb_priv *eth = dev_get_priv(dev);
517 mdio_unregister(eth->bus);
519 unmap_physmem(eth->iobase, MAP_NOCACHE);
524 int ravb_bb_init(struct bb_miiphy_bus *bus)
529 int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
531 struct ravb_priv *eth = bus->priv;
533 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
538 int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
540 struct ravb_priv *eth = bus->priv;
542 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
547 int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
549 struct ravb_priv *eth = bus->priv;
552 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
554 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
559 int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
561 struct ravb_priv *eth = bus->priv;
563 *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
568 int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
570 struct ravb_priv *eth = bus->priv;
573 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
575 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
580 int ravb_bb_delay(struct bb_miiphy_bus *bus)
587 struct bb_miiphy_bus bb_miiphy_buses[] = {
590 .init = ravb_bb_init,
591 .mdio_active = ravb_bb_mdio_active,
592 .mdio_tristate = ravb_bb_mdio_tristate,
593 .set_mdio = ravb_bb_set_mdio,
594 .get_mdio = ravb_bb_get_mdio,
595 .set_mdc = ravb_bb_set_mdc,
596 .delay = ravb_bb_delay,
599 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
601 static const struct eth_ops ravb_ops = {
605 .free_pkt = ravb_free_pkt,
607 .write_hwaddr = ravb_write_hwaddr,
610 int ravb_ofdata_to_platdata(struct udevice *dev)
612 struct eth_pdata *pdata = dev_get_platdata(dev);
613 const char *phy_mode;
617 pdata->iobase = devfdt_get_addr(dev);
618 pdata->phy_interface = -1;
619 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
622 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
623 if (pdata->phy_interface == -1) {
624 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
628 pdata->max_speed = 1000;
629 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
631 pdata->max_speed = fdt32_to_cpu(*cell);
633 sprintf(bb_miiphy_buses[0].name, dev->name);
638 static const struct udevice_id ravb_ids[] = {
639 { .compatible = "renesas,etheravb-r8a7795" },
640 { .compatible = "renesas,etheravb-r8a7796" },
641 { .compatible = "renesas,etheravb-rcar-gen3" },
645 U_BOOT_DRIVER(eth_ravb) = {
648 .of_match = ravb_ids,
649 .ofdata_to_platdata = ravb_ofdata_to_platdata,
651 .remove = ravb_remove,
653 .priv_auto_alloc_size = sizeof(struct ravb_priv),
654 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
655 .flags = DM_FLAG_ALLOC_PRIV_DMA,