drivers/net/pic32_eth.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
   4  *
   5  */
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <errno.h>
   9 #include <dm.h>
  10 #include <net.h>
  11 #include <miiphy.h>
  12 #include <console.h>
  13 #include <time.h>
  14 #include <wait_bit.h>
  15 #include <asm/gpio.h>
  16 #include <linux/mii.h>
  17
  18 #include "pic32_eth.h"
  19
  20 #define MAX_RX_BUF_SIZE         1536
  21 #define MAX_RX_DESCR            PKTBUFSRX
  22 #define MAX_TX_DESCR            2
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 struct pic32eth_dev {
  27         struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
  28         struct eth_dma_desc txd_ring[MAX_TX_DESCR];
  29         u32 rxd_idx; /* index of RX desc to read */
  30         /* regs */
  31         struct pic32_ectl_regs *ectl_regs;
  32         struct pic32_emac_regs *emac_regs;
  33         /* Phy */
  34         struct phy_device *phydev;
  35         phy_interface_t phyif;
  36         u32 phy_addr;
  37         struct gpio_desc rst_gpio;
  38 };
  39
  40 void __weak board_netphy_reset(void *dev)
  41 {
  42         struct pic32eth_dev *priv = dev;
  43
  44         if (!dm_gpio_is_valid(&priv->rst_gpio))
  45                 return;
  46
  47         /* phy reset */
  48         dm_gpio_set_value(&priv->rst_gpio, 0);
  49         udelay(300);
  50         dm_gpio_set_value(&priv->rst_gpio, 1);
  51         udelay(300);
  52 }
  53
  54 /* Initialize mii(MDIO) interface, discover which PHY is
  55  * attached to the device, and configure it properly.
  56  */
  57 static int pic32_mii_init(struct pic32eth_dev *priv)
  58 {
  59         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  60         struct pic32_emac_regs *emac_p = priv->emac_regs;
  61
  62         /* board phy reset */
  63         board_netphy_reset(priv);
  64
  65         /* disable RX, TX & all transactions */
  66         writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  67
  68         /* wait till busy */
  69         wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  70                           CONFIG_SYS_HZ, false);
  71
  72         /* turn controller ON to access PHY over MII */
  73         writel(ETHCON_ON, &ectl_p->con1.set);
  74
  75         mdelay(10);
  76
  77         /* reset MAC */
  78         writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
  79         mdelay(10);
  80         writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
  81
  82         /* initialize MDIO/MII */
  83         if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
  84                 writel(EMAC_RMII_RESET, &emac_p->supp.set);
  85                 mdelay(10);
  86                 writel(EMAC_RMII_RESET, &emac_p->supp.clr);
  87         }
  88
  89         return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
  90 }
  91
  92 static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
  93 {
  94         struct mii_dev *mii;
  95
  96         mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  97
  98         /* find & connect PHY */
  99         priv->phydev = phy_connect(mii, priv->phy_addr,
 100                                    dev, priv->phyif);
 101         if (!priv->phydev) {
 102                 printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
 103                 return 0;
 104         }
 105
 106         /* Wait for phy to complete reset */
 107         mdelay(10);
 108
 109         /* configure supported modes */
 110         priv->phydev->supported = SUPPORTED_10baseT_Half |
 111                                   SUPPORTED_10baseT_Full |
 112                                   SUPPORTED_100baseT_Half |
 113                                   SUPPORTED_100baseT_Full |
 114                                   SUPPORTED_Autoneg;
 115
 116         priv->phydev->advertising = ADVERTISED_10baseT_Half |
 117                                     ADVERTISED_10baseT_Full |
 118                                     ADVERTISED_100baseT_Half |
 119                                     ADVERTISED_100baseT_Full |
 120                                     ADVERTISED_Autoneg;
 121
 122         priv->phydev->autoneg = AUTONEG_ENABLE;
 123
 124         return 0;
 125 }
 126
 127 /* Configure MAC based on negotiated speed and duplex
 128  * reported by PHY.
 129  */
 130 static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
 131 {
 132         struct phy_device *phydev = priv->phydev;
 133         struct pic32_emac_regs *emac_p = priv->emac_regs;
 134
 135         if (!phydev->link) {
 136                 printf("%s: No link.\n", phydev->dev->name);
 137                 return -EINVAL;
 138         }
 139
 140         if (phydev->duplex) {
 141                 writel(EMAC_FULLDUP, &emac_p->cfg2.set);
 142                 writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
 143         } else {
 144                 writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
 145                 writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
 146         }
 147
 148         switch (phydev->speed) {
 149         case SPEED_100:
 150                 writel(EMAC_RMII_SPD100, &emac_p->supp.set);
 151                 break;
 152         case SPEED_10:
 153                 writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
 154                 break;
 155         default:
 156                 printf("%s: Speed was bad\n", phydev->dev->name);
 157                 return -EINVAL;
 158         }
 159
 160         printf("pic32eth: PHY is %s with %dbase%s, %s\n",
 161                phydev->drv->name, phydev->speed,
 162                (phydev->port == PORT_TP) ? "T" : "X",
 163                (phydev->duplex) ? "full" : "half");
 164
 165         return 0;
 166 }
 167
 168 static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
 169 {
 170         struct pic32_emac_regs *emac_p = priv->emac_regs;
 171         u32 stat = 0, v;
 172         u64 expire;
 173
 174         v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
 175         writel(v, &emac_p->cfg1.raw);
 176
 177         v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
 178             EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
 179         writel(v, &emac_p->cfg2.raw);
 180
 181         /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
 182         writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
 183
 184         /* recommended non-back-to-back interpacket gap is 0xc12 */
 185         writel(0xc12, &emac_p->ipgr.raw);
 186
 187         /* recommended collision window retry limit is 0x370F */
 188         writel(0x370f, &emac_p->clrt.raw);
 189
 190         /* set maximum frame length: allow VLAN tagged frame */
 191         writel(0x600, &emac_p->maxf.raw);
 192
 193         /* set the mac address */
 194         writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
 195         writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
 196         writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
 197
 198         /* default, enable 10 Mbps operation */
 199         writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
 200
 201         /* wait until link status UP or deadline elapsed */
 202         expire = get_ticks() + get_tbclk() * 2;
 203         for (; get_ticks() < expire;) {
 204                 stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
 205                 if (stat & BMSR_LSTATUS)
 206                         break;
 207         }
 208
 209         if (!(stat & BMSR_LSTATUS))
 210                 printf("MAC: Link is DOWN!\n");
 211
 212         /* delay to stabilize before any tx/rx */
 213         mdelay(10);
 214 }
 215
 216 static void pic32_mac_reset(struct pic32eth_dev *priv)
 217 {
 218         struct pic32_emac_regs *emac_p = priv->emac_regs;
 219         struct mii_dev *mii;
 220
 221         /* Reset MAC */
 222         writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
 223         mdelay(10);
 224
 225         /* clear reset */
 226         writel(0, &emac_p->cfg1.raw);
 227
 228         /* Reset MII */
 229         mii = priv->phydev->bus;
 230         if (mii && mii->reset)
 231                 mii->reset(mii);
 232 }
 233
 234 /* initializes the MAC and PHY, then establishes a link */
 235 static void pic32_ctrl_reset(struct pic32eth_dev *priv)
 236 {
 237         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 238         u32 v;
 239
 240         /* disable RX, TX & any other transactions */
 241         writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 242
 243         /* wait till busy */
 244         wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
 245                           CONFIG_SYS_HZ, false);
 246         /* decrement received buffcnt to zero. */
 247         while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
 248                 writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
 249
 250         /* clear any existing interrupt event */
 251         writel(0xffffffff, &ectl_p->irq.clr);
 252
 253         /* clear RX/TX start address */
 254         writel(0xffffffff, &ectl_p->txst.clr);
 255         writel(0xffffffff, &ectl_p->rxst.clr);
 256
 257         /* clear the receive filters */
 258         writel(0x00ff, &ectl_p->rxfc.clr);
 259
 260         /* set the receive filters
 261          * ETH_FILT_CRC_ERR_REJECT
 262          * ETH_FILT_RUNT_REJECT
 263          * ETH_FILT_UCAST_ACCEPT
 264          * ETH_FILT_MCAST_ACCEPT
 265          * ETH_FILT_BCAST_ACCEPT
 266          */
 267         v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
 268             ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
 269         writel(v, &ectl_p->rxfc.set);
 270
 271         /* turn controller ON to access PHY over MII */
 272         writel(ETHCON_ON, &ectl_p->con1.set);
 273 }
 274
 275 static void pic32_rx_desc_init(struct pic32eth_dev *priv)
 276 {
 277         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 278         struct eth_dma_desc *rxd;
 279         u32 idx, bufsz;
 280
 281         priv->rxd_idx = 0;
 282         for (idx = 0; idx < MAX_RX_DESCR; idx++) {
 283                 rxd = &priv->rxd_ring[idx];
 284
 285                 /* hw owned */
 286                 rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
 287
 288                 /* packet buffer address */
 289                 rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
 290
 291                 /* link to next desc */
 292                 rxd->next_ed = virt_to_phys(rxd + 1);
 293
 294                 /* reset status */
 295                 rxd->stat1 = 0;
 296                 rxd->stat2 = 0;
 297
 298                 /* decrement bufcnt */
 299                 writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
 300         }
 301
 302         /* link last descr to beginning of list */
 303         rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
 304
 305         /* flush rx ring */
 306         flush_dcache_range((ulong)priv->rxd_ring,
 307                            (ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
 308
 309         /* set rx desc-ring start address */
 310         writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
 311
 312         /* RX Buffer size */
 313         bufsz = readl(&ectl_p->con2.raw);
 314         bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
 315         bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
 316         writel(bufsz, &ectl_p->con2.raw);
 317
 318         /* enable the receiver in hardware which allows hardware
 319          * to DMA received pkts to the descriptor pointer address.
 320          */
 321         writel(ETHCON_RXEN, &ectl_p->con1.set);
 322 }
 323
 324 static int pic32_eth_start(struct udevice *dev)
 325 {
 326         struct eth_pdata *pdata = dev_get_platdata(dev);
 327         struct pic32eth_dev *priv = dev_get_priv(dev);
 328
 329         /* controller */
 330         pic32_ctrl_reset(priv);
 331
 332         /* reset MAC */
 333         pic32_mac_reset(priv);
 334
 335         /* configure PHY */
 336         phy_config(priv->phydev);
 337
 338         /* initialize MAC */
 339         pic32_mac_init(priv, &pdata->enetaddr[0]);
 340
 341         /* init RX descriptor; TX descriptors are handled in xmit */
 342         pic32_rx_desc_init(priv);
 343
 344         /* Start up & update link status of PHY */
 345         phy_startup(priv->phydev);
 346
 347         /* adjust mac with phy link status */
 348         return pic32_mac_adjust_link(priv);
 349 }
 350
 351 static void pic32_eth_stop(struct udevice *dev)
 352 {
 353         struct pic32eth_dev *priv = dev_get_priv(dev);
 354         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 355         struct pic32_emac_regs *emac_p = priv->emac_regs;
 356
 357         /* Reset the phy if the controller is enabled */
 358         if (readl(&ectl_p->con1.raw) & ETHCON_ON)
 359                 phy_reset(priv->phydev);
 360
 361         /* Shut down the PHY */
 362         phy_shutdown(priv->phydev);
 363
 364         /* Stop rx/tx */
 365         writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
 366         mdelay(10);
 367
 368         /* reset MAC */
 369         writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
 370
 371         /* clear reset */
 372         writel(0, &emac_p->cfg1.raw);
 373         mdelay(10);
 374
 375         /* disable controller */
 376         writel(ETHCON_ON, &ectl_p->con1.clr);
 377         mdelay(10);
 378
 379         /* wait until everything is down */
 380         wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
 381                           2 * CONFIG_SYS_HZ, false);
 382
 383         /* clear any existing interrupt event */
 384         writel(0xffffffff, &ectl_p->irq.clr);
 385 }
 386
 387 static int pic32_eth_send(struct udevice *dev, void *packet, int length)
 388 {
 389         struct pic32eth_dev *priv = dev_get_priv(dev);
 390         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 391         struct eth_dma_desc *txd;
 392         u64 deadline;
 393
 394         txd = &priv->txd_ring[0];
 395
 396         /* set proper flags & length in descriptor header */
 397         txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
 398
 399         /* pass buffer address to hardware */
 400         txd->data_buff = virt_to_phys(packet);
 401
 402         debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
 403               __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
 404               txd->next_ed);
 405
 406         /* cache flush (packet) */
 407         flush_dcache_range((ulong)packet, (ulong)packet + length);
 408
 409         /* cache flush (txd) */
 410         flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
 411
 412         /* pass descriptor table base to h/w */
 413         writel(virt_to_phys(txd), &ectl_p->txst.raw);
 414
 415         /* ready to send enabled, hardware can now send the packet(s) */
 416         writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
 417
 418         /* wait until tx has completed and h/w has released ownership
 419          * of the tx descriptor or timeout elapsed.
 420          */
 421         deadline = get_ticks() + get_tbclk();
 422         for (;;) {
 423                 /* check timeout */
 424                 if (get_ticks() > deadline)
 425                         return -ETIMEDOUT;
 426
 427                 if (ctrlc())
 428                         return -EINTR;
 429
 430                 /* tx completed ? */
 431                 if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
 432                         udelay(1);
 433                         continue;
 434                 }
 435
 436                 /* h/w not released ownership yet? */
 437                 invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
 438                 if (!(txd->hdr & EDH_EOWN))
 439                         break;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 446 {
 447         struct pic32eth_dev *priv = dev_get_priv(dev);
 448         struct eth_dma_desc *rxd;
 449         u32 idx = priv->rxd_idx;
 450         u32 rx_count;
 451
 452         /* find the next ready to receive */
 453         rxd = &priv->rxd_ring[idx];
 454
 455         invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
 456         /* check if owned by MAC */
 457         if (rxd->hdr & EDH_EOWN)
 458                 return -EAGAIN;
 459
 460         /* Sanity check on header: SOP and EOP  */
 461         if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
 462                 printf("%s: %s, rx pkt across multiple descr\n",
 463                        __FILE__, __func__);
 464                 return 0;
 465         }
 466
 467         debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
 468               __func__, __LINE__, idx, rxd->hdr,
 469               rxd->data_buff, rxd->stat2, rxd->next_ed);
 470
 471         /* Sanity check on rx_stat: OK, CRC */
 472         if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
 473                 debug("%s: %s: Error, rx problem detected\n",
 474                       __FILE__, __func__);
 475                 return 0;
 476         }
 477
 478         /* invalidate dcache */
 479         rx_count = RSV_RX_COUNT(rxd->stat2);
 480         invalidate_dcache_range((ulong)net_rx_packets[idx],
 481                                 (ulong)net_rx_packets[idx] + rx_count);
 482
 483         /* Pass the packet to protocol layer */
 484         *packetp = net_rx_packets[idx];
 485
 486         /* increment number of bytes rcvd (ignore CRC) */
 487         return rx_count - 4;
 488 }
 489
 490 static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
 491 {
 492         struct pic32eth_dev *priv = dev_get_priv(dev);
 493         struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
 494         struct eth_dma_desc *rxd;
 495         int idx = priv->rxd_idx;
 496
 497         /* sanity check */
 498         if (packet != net_rx_packets[idx]) {
 499                 printf("rxd_id %d: packet is not matched,\n", idx);
 500                 return -EAGAIN;
 501         }
 502
 503         /* prepare for receive */
 504         rxd = &priv->rxd_ring[idx];
 505         rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
 506
 507         flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
 508
 509         /* decrement rx pkt count */
 510         writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
 511
 512         debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
 513               __func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
 514               rxd->stat2, rxd->next_ed);
 515
 516         priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
 517
 518         return 0;
 519 }
 520
 521 static const struct eth_ops pic32_eth_ops = {
 522         .start          = pic32_eth_start,
 523         .send           = pic32_eth_send,
 524         .recv           = pic32_eth_recv,
 525         .free_pkt       = pic32_eth_free_pkt,
 526         .stop           = pic32_eth_stop,
 527 };
 528
 529 static int pic32_eth_probe(struct udevice *dev)
 530 {
 531         struct eth_pdata *pdata = dev_get_platdata(dev);
 532         struct pic32eth_dev *priv = dev_get_priv(dev);
 533         const char *phy_mode;
 534         void __iomem *iobase;
 535         fdt_addr_t addr;
 536         fdt_size_t size;
 537         int offset = 0;
 538         int phy_addr = -1;
 539
 540         addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
 541                                     &size);
 542         if (addr == FDT_ADDR_T_NONE)
 543                 return -EINVAL;
 544
 545         iobase = ioremap(addr, size);
 546         pdata->iobase = (phys_addr_t)addr;
 547
 548         /* get phy mode */
 549         pdata->phy_interface = -1;
 550         phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
 551                                NULL);
 552         if (phy_mode)
 553                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 554         if (pdata->phy_interface == -1) {
 555                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 556                 return -EINVAL;
 557         }
 558
 559         /* get phy addr */
 560         offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
 561                                        "phy-handle");
 562         if (offset > 0)
 563                 phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
 564
 565         /* phy reset gpio */
 566         gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
 567                                    &priv->rst_gpio, GPIOD_IS_OUT);
 568
 569         priv->phyif     = pdata->phy_interface;
 570         priv->phy_addr  = phy_addr;
 571         priv->ectl_regs = iobase;
 572         priv->emac_regs = iobase + PIC32_EMAC1CFG1;
 573
 574         pic32_mii_init(priv);
 575
 576         return pic32_phy_init(priv, dev);
 577 }
 578
 579 static int pic32_eth_remove(struct udevice *dev)
 580 {
 581         struct pic32eth_dev *priv = dev_get_priv(dev);
 582         struct mii_dev *bus;
 583
 584         dm_gpio_free(dev, &priv->rst_gpio);
 585         phy_shutdown(priv->phydev);
 586         free(priv->phydev);
 587         bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
 588         mdio_unregister(bus);
 589         mdio_free(bus);
 590         iounmap(priv->ectl_regs);
 591         return 0;
 592 }
 593
 594 static const struct udevice_id pic32_eth_ids[] = {
 595         { .compatible = "microchip,pic32mzda-eth" },
 596         { }
 597 };
 598
 599 U_BOOT_DRIVER(pic32_ethernet) = {
 600         .name                   = "pic32_ethernet",
 601         .id                     = UCLASS_ETH,
 602         .of_match               = pic32_eth_ids,
 603         .probe                  = pic32_eth_probe,
 604         .remove                 = pic32_eth_remove,
 605         .ops                    = &pic32_eth_ops,
 606         .priv_auto_alloc_size   = sizeof(struct pic32eth_dev),
 607         .platdata_auto_alloc_size       = sizeof(struct eth_pdata),
 608 };