1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx PCS/PMA Core phy driver
5 * Copyright (C) 2015 - 2016 Xilinx, Inc.
13 #define MII_PHY_STATUS_SPD_MASK 0x0C00
14 #define MII_PHY_STATUS_FULLDUPLEX 0x1000
15 #define MII_PHY_STATUS_1000 0x0800
16 #define MII_PHY_STATUS_100 0x0400
17 #define XPCSPMA_PHY_CTRL_ISOLATE_DISABLE 0xFBFF
19 /* Mask used for ID comparisons */
20 #define XILINX_PHY_ID_MASK 0xfffffff0
23 #define XILINX_PHY_ID 0x01740c00
25 /* struct phy_device dev_flags definitions */
26 #define XAE_PHY_TYPE_MII 0
27 #define XAE_PHY_TYPE_GMII 1
28 #define XAE_PHY_TYPE_RGMII_1_3 2
29 #define XAE_PHY_TYPE_RGMII_2_0 3
30 #define XAE_PHY_TYPE_SGMII 4
31 #define XAE_PHY_TYPE_1000BASE_X 5
33 static int xilinxphy_startup(struct phy_device *phydev)
38 debug("%s\n", __func__);
39 /* Update the link, but return if there
42 err = genphy_update_link(phydev);
46 if (AUTONEG_ENABLE == phydev->autoneg) {
47 status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
48 status = status & MII_PHY_STATUS_SPD_MASK;
50 if (status & MII_PHY_STATUS_FULLDUPLEX)
51 phydev->duplex = DUPLEX_FULL;
53 phydev->duplex = DUPLEX_HALF;
56 case MII_PHY_STATUS_1000:
57 phydev->speed = SPEED_1000;
60 case MII_PHY_STATUS_100:
61 phydev->speed = SPEED_100;
65 phydev->speed = SPEED_10;
69 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
74 if (bmcr & BMCR_FULLDPLX)
75 phydev->duplex = DUPLEX_FULL;
77 phydev->duplex = DUPLEX_HALF;
79 if (bmcr & BMCR_SPEED1000)
80 phydev->speed = SPEED_1000;
81 else if (bmcr & BMCR_SPEED100)
82 phydev->speed = SPEED_100;
84 phydev->speed = SPEED_10;
88 * For 1000BASE-X Phy Mode the speed/duplex will always be
91 if (phydev->flags == XAE_PHY_TYPE_1000BASE_X) {
92 phydev->duplex = DUPLEX_FULL;
93 phydev->speed = SPEED_1000;
99 static int xilinxphy_of_init(struct phy_device *phydev)
104 debug("%s\n", __func__);
105 node = phy_get_ofnode(phydev);
106 if (!ofnode_valid(node))
109 phytype = ofnode_read_u32_default(node, "xlnx,phy-type", -1);
110 if (phytype == XAE_PHY_TYPE_1000BASE_X)
111 phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
116 static int xilinxphy_config(struct phy_device *phydev)
120 debug("%s\n", __func__);
121 xilinxphy_of_init(phydev);
122 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
123 temp &= XPCSPMA_PHY_CTRL_ISOLATE_DISABLE;
124 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp);
129 static struct phy_driver xilinxphy_driver = {
130 .uid = XILINX_PHY_ID,
131 .mask = XILINX_PHY_ID_MASK,
132 .name = "Xilinx PCS/PMA PHY",
133 .features = PHY_GBIT_FEATURES,
134 .config = &xilinxphy_config,
135 .startup = &xilinxphy_startup,
136 .shutdown = &genphy_shutdown,
139 int phy_xilinx_init(void)
141 debug("%s\n", __func__);
142 phy_register(&xilinxphy_driver);