4 * Copyright 2010-2014 Freescale Semiconductor, Inc.
5 * Original Author: Andy Fleming
6 * Add vsc8662 phy support - Priyanka Jain
7 * SPDX-License-Identifier: GPL-2.0+
11 /* Cicada Auxiliary Control/Status Register */
12 #define MIIM_CIS82xx_AUX_CONSTAT 0x1c
13 #define MIIM_CIS82xx_AUXCONSTAT_INIT 0x0004
14 #define MIIM_CIS82xx_AUXCONSTAT_DUPLEX 0x0020
15 #define MIIM_CIS82xx_AUXCONSTAT_SPEED 0x0018
16 #define MIIM_CIS82xx_AUXCONSTAT_GBIT 0x0010
17 #define MIIM_CIS82xx_AUXCONSTAT_100 0x0008
19 /* Cicada Extended Control Register 1 */
20 #define MIIM_CIS82xx_EXT_CON1 0x17
21 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
23 /* Cicada 8204 Extended PHY Control Register 1 */
24 #define MIIM_CIS8204_EPHY_CON 0x17
25 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
26 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
28 /* Cicada 8204 Serial LED Control Register */
29 #define MIIM_CIS8204_SLED_CON 0x1b
30 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
32 /* Vitesse VSC8601 Extended PHY Control Register 1 */
33 #define MIIM_VSC8601_EPHY_CON 0x17
34 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
35 #define MIIM_VSC8601_SKEW_CTRL 0x1c
37 #define PHY_EXT_PAGE_ACCESS 0x1f
38 #define PHY_EXT_PAGE_ACCESS_GENERAL 0x10
39 #define PHY_EXT_PAGE_ACCESS_EXTENDED3 0x3
41 /* Vitesse VSC8574 control register */
42 #define MIIM_VSC8574_MAC_SERDES_CON 0x10
43 #define MIIM_VSC8574_MAC_SERDES_ANEG 0x80
44 #define MIIM_VSC8574_GENERAL18 0x12
45 #define MIIM_VSC8574_GENERAL19 0x13
47 /* Vitesse VSC8574 gerenal purpose register 18 */
48 #define MIIM_VSC8574_18G_SGMII 0x80f0
49 #define MIIM_VSC8574_18G_QSGMII 0x80e0
50 #define MIIM_VSC8574_18G_CMDSTAT 0x8000
52 /* Vitesse VSC8514 control register */
53 #define MIIM_VSC8514_MAC_SERDES_CON 0x10
54 #define MIIM_VSC8514_GENERAL18 0x12
55 #define MIIM_VSC8514_GENERAL19 0x13
56 #define MIIM_VSC8514_GENERAL23 0x17
58 /* Vitesse VSC8514 gerenal purpose register 18 */
59 #define MIIM_VSC8514_18G_QSGMII 0x80e0
60 #define MIIM_VSC8514_18G_CMDSTAT 0x8000
62 /* Vitesse VSC8664 Control/Status Register */
63 #define MIIM_VSC8664_SERDES_AND_SIGDET 0x13
64 #define MIIM_VSC8664_ADDITIONAL_DEV 0x16
65 #define MIIM_VSC8664_EPHY_CON 0x17
66 #define MIIM_VSC8664_LED_CON 0x1E
68 #define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001
71 static int vitesse_config(struct phy_device *phydev)
73 /* Override PHY config settings */
74 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
75 MIIM_CIS82xx_AUXCONSTAT_INIT);
76 /* Set up the interface mode */
77 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1,
78 MIIM_CIS8201_EXTCON1_INIT);
80 genphy_config_aneg(phydev);
85 static int vitesse_parse_status(struct phy_device *phydev)
90 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT);
92 if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX)
93 phydev->duplex = DUPLEX_FULL;
95 phydev->duplex = DUPLEX_HALF;
97 speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED;
99 case MIIM_CIS82xx_AUXCONSTAT_GBIT:
100 phydev->speed = SPEED_1000;
102 case MIIM_CIS82xx_AUXCONSTAT_100:
103 phydev->speed = SPEED_100;
106 phydev->speed = SPEED_10;
113 static int vitesse_startup(struct phy_device *phydev)
117 ret = genphy_update_link(phydev);
120 return vitesse_parse_status(phydev);
123 static int cis8204_config(struct phy_device *phydev)
125 /* Override PHY config settings */
126 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
127 MIIM_CIS82xx_AUXCONSTAT_INIT);
129 genphy_config_aneg(phydev);
131 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
132 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
133 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
134 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
135 MIIM_CIS8204_EPHYCON_INIT |
136 MIIM_CIS8204_EPHYCON_RGMII);
138 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
139 MIIM_CIS8204_EPHYCON_INIT);
144 /* Vitesse VSC8601 */
145 static int vsc8601_config(struct phy_device *phydev)
147 /* Configure some basic stuff */
148 #ifdef CONFIG_SYS_VSC8601_SKEWFIX
149 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON,
150 MIIM_VSC8601_EPHY_CON_INIT_SKEW);
151 #if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
152 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1);
153 #define VSC8101_SKEW \
154 ((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
155 | (CONFIG_SYS_VSC8601_SKEW_RX << 12))
156 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL,
158 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
162 genphy_config_aneg(phydev);
167 static int vsc8574_config(struct phy_device *phydev)
170 /* configure register 19G for MAC */
171 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
172 PHY_EXT_PAGE_ACCESS_GENERAL);
174 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19);
175 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
176 /* set bit 15:14 to '01' for QSGMII mode */
177 val = (val & 0x3fff) | (1 << 14);
178 phy_write(phydev, MDIO_DEVAD_NONE,
179 MIIM_VSC8574_GENERAL19, val);
180 /* Enable 4 ports MAC QSGMII */
181 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
182 MIIM_VSC8574_18G_QSGMII);
184 /* set bit 15:14 to '00' for SGMII mode */
186 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val);
187 /* Enable 4 ports MAC SGMII */
188 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
189 MIIM_VSC8574_18G_SGMII);
191 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
192 /* When bit 15 is cleared the command has completed */
193 while (val & MIIM_VSC8574_18G_CMDSTAT)
194 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
196 /* Enable Serdes Auto-negotiation */
197 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
198 PHY_EXT_PAGE_ACCESS_EXTENDED3);
199 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON);
200 val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
201 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val);
203 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
205 genphy_config_aneg(phydev);
210 static int vsc8514_config(struct phy_device *phydev)
213 int timeout = 1000000;
215 /* configure register to access 19G */
216 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
217 PHY_EXT_PAGE_ACCESS_GENERAL);
219 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19);
220 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
221 /* set bit 15:14 to '01' for QSGMII mode */
222 val = (val & 0x3fff) | (1 << 14);
223 phy_write(phydev, MDIO_DEVAD_NONE,
224 MIIM_VSC8514_GENERAL19, val);
225 /* Enable 4 ports MAC QSGMII */
226 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18,
227 MIIM_VSC8514_18G_QSGMII);
229 /*TODO Add SGMII functionality once spec sheet
230 * for VSC8514 defines complete functionality
234 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
235 /* When bit 15 is cleared the command has completed */
236 while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--)
237 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18);
240 printf("PHY 8514 config failed\n");
244 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
246 /* configure register to access 23 */
247 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23);
248 /* set bits 10:8 to '000' */
249 val = (val & 0xf8ff);
250 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
252 /* Enable Serdes Auto-negotiation */
253 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
254 PHY_EXT_PAGE_ACCESS_EXTENDED3);
255 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON);
256 val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
257 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val);
258 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
260 genphy_config_aneg(phydev);
265 static int vsc8664_config(struct phy_device *phydev)
269 /* Enable MAC interface auto-negotiation */
270 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
271 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
273 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
275 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
276 PHY_EXT_PAGE_ACCESS_EXTENDED);
277 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
279 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
280 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
282 /* Enable LED blink */
283 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
285 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
287 genphy_config_aneg(phydev);
292 static struct phy_driver VSC8211_driver = {
293 .name = "Vitesse VSC8211",
296 .features = PHY_GBIT_FEATURES,
297 .config = &vitesse_config,
298 .startup = &vitesse_startup,
299 .shutdown = &genphy_shutdown,
302 static struct phy_driver VSC8221_driver = {
303 .name = "Vitesse VSC8221",
306 .features = PHY_GBIT_FEATURES,
307 .config = &genphy_config_aneg,
308 .startup = &vitesse_startup,
309 .shutdown = &genphy_shutdown,
312 static struct phy_driver VSC8244_driver = {
313 .name = "Vitesse VSC8244",
316 .features = PHY_GBIT_FEATURES,
317 .config = &genphy_config_aneg,
318 .startup = &vitesse_startup,
319 .shutdown = &genphy_shutdown,
322 static struct phy_driver VSC8234_driver = {
323 .name = "Vitesse VSC8234",
326 .features = PHY_GBIT_FEATURES,
327 .config = &genphy_config_aneg,
328 .startup = &vitesse_startup,
329 .shutdown = &genphy_shutdown,
332 static struct phy_driver VSC8574_driver = {
333 .name = "Vitesse VSC8574",
336 .features = PHY_GBIT_FEATURES,
337 .config = &vsc8574_config,
338 .startup = &vitesse_startup,
339 .shutdown = &genphy_shutdown,
342 static struct phy_driver VSC8514_driver = {
343 .name = "Vitesse VSC8514",
346 .features = PHY_GBIT_FEATURES,
347 .config = &vsc8514_config,
348 .startup = &vitesse_startup,
349 .shutdown = &genphy_shutdown,
352 static struct phy_driver VSC8584_driver = {
353 .name = "Vitesse VSC8584",
356 .features = PHY_GBIT_FEATURES,
357 .config = &vsc8574_config,
358 .startup = &vitesse_startup,
359 .shutdown = &genphy_shutdown,
362 static struct phy_driver VSC8601_driver = {
363 .name = "Vitesse VSC8601",
366 .features = PHY_GBIT_FEATURES,
367 .config = &vsc8601_config,
368 .startup = &vitesse_startup,
369 .shutdown = &genphy_shutdown,
372 static struct phy_driver VSC8641_driver = {
373 .name = "Vitesse VSC8641",
376 .features = PHY_GBIT_FEATURES,
377 .config = &genphy_config_aneg,
378 .startup = &vitesse_startup,
379 .shutdown = &genphy_shutdown,
382 static struct phy_driver VSC8662_driver = {
383 .name = "Vitesse VSC8662",
386 .features = PHY_GBIT_FEATURES,
387 .config = &genphy_config_aneg,
388 .startup = &vitesse_startup,
389 .shutdown = &genphy_shutdown,
392 static struct phy_driver VSC8664_driver = {
393 .name = "Vitesse VSC8664",
396 .features = PHY_GBIT_FEATURES,
397 .config = &vsc8664_config,
398 .startup = &vitesse_startup,
399 .shutdown = &genphy_shutdown,
402 /* Vitesse bought Cicada, so we'll put these here */
403 static struct phy_driver cis8201_driver = {
407 .features = PHY_GBIT_FEATURES,
408 .config = &vitesse_config,
409 .startup = &vitesse_startup,
410 .shutdown = &genphy_shutdown,
413 static struct phy_driver cis8204_driver = {
414 .name = "Cicada Cis8204",
417 .features = PHY_GBIT_FEATURES,
418 .config = &cis8204_config,
419 .startup = &vitesse_startup,
420 .shutdown = &genphy_shutdown,
423 int phy_vitesse_init(void)
425 phy_register(&VSC8641_driver);
426 phy_register(&VSC8601_driver);
427 phy_register(&VSC8234_driver);
428 phy_register(&VSC8244_driver);
429 phy_register(&VSC8211_driver);
430 phy_register(&VSC8221_driver);
431 phy_register(&VSC8574_driver);
432 phy_register(&VSC8584_driver);
433 phy_register(&VSC8514_driver);
434 phy_register(&VSC8662_driver);
435 phy_register(&VSC8664_driver);
436 phy_register(&cis8201_driver);
437 phy_register(&cis8204_driver);