drivers/net/phy/ti.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <linux/compat.h>
   9 #include <malloc.h>
  10
  11 #include <dm.h>
  12 #include <dt-bindings/net/ti-dp83867.h>
  13
  14
  15 /* TI DP83867 */
  16 #define DP83867_DEVADDR         0x1f
  17
  18 #define MII_DP83867_PHYCTRL     0x10
  19 #define MII_DP83867_MICR        0x12
  20 #define MII_DP83867_CFG2        0x14
  21 #define MII_DP83867_BISCR       0x16
  22 #define DP83867_CTRL            0x1f
  23
  24 /* Extended Registers */
  25 #define DP83867_CFG4            0x0031
  26 #define DP83867_RGMIICTL        0x0032
  27 #define DP83867_STRAP_STS1      0x006E
  28 #define DP83867_RGMIIDCTL       0x0086
  29 #define DP83867_IO_MUX_CFG      0x0170
  30
  31 #define DP83867_SW_RESET        BIT(15)
  32 #define DP83867_SW_RESTART      BIT(14)
  33
  34 /* MICR Interrupt bits */
  35 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  36 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  37 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  38 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  39 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  40 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  41 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  42 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  43 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  44 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  45 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  46 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  47
  48 /* RGMIICTL bits */
  49 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  50 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  51
  52 /* STRAP_STS1 bits */
  53 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  54
  55 /* PHY CTRL bits */
  56 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  57 #define DP83867_PHYCR_RESERVED_MASK     BIT(11)
  58 #define DP83867_MDI_CROSSOVER           5
  59 #define DP83867_MDI_CROSSOVER_AUTO      2
  60 #define DP83867_MDI_CROSSOVER_MDIX      2
  61 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  62 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  63 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  64
  65 /* RGMIIDCTL bits */
  66 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  67
  68 /* CFG2 bits */
  69 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  70 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  71 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  72 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  73 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  74 #define MII_DP83867_CFG2_MASK                   0x003F
  75
  76 #define MII_MMD_CTRL    0x0d /* MMD Access Control Register */
  77 #define MII_MMD_DATA    0x0e /* MMD Access Data Register */
  78
  79 /* MMD Access Control register fields */
  80 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
  81 #define MII_MMD_CTRL_ADDR       0x0000 /* Address */
  82 #define MII_MMD_CTRL_NOINCR     0x4000 /* no post increment */
  83 #define MII_MMD_CTRL_INCR_RDWT  0x8000 /* post increment on reads & writes */
  84 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
  85
  86 /* User setting - can be taken from DTS */
  87 #define DEFAULT_RX_ID_DELAY     DP83867_RGMIIDCTL_2_25_NS
  88 #define DEFAULT_TX_ID_DELAY     DP83867_RGMIIDCTL_2_75_NS
  89 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  90
  91 /* IO_MUX_CFG bits */
  92 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  93
  94 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  95 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  96 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  97 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       \
  98                 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
  99
 100 /* CFG4 bits */
 101 #define DP83867_CFG4_PORT_MIRROR_EN             BIT(0)
 102
 103 enum {
 104         DP83867_PORT_MIRRORING_KEEP,
 105         DP83867_PORT_MIRRORING_EN,
 106         DP83867_PORT_MIRRORING_DIS,
 107 };
 108
 109 struct dp83867_private {
 110         int rx_id_delay;
 111         int tx_id_delay;
 112         int fifo_depth;
 113         int io_impedance;
 114         bool rxctrl_strap_quirk;
 115         int port_mirroring;
 116         int clk_output_sel;
 117 };
 118
 119 /**
 120  * phy_read_mmd_indirect - reads data from the MMD registers
 121  * @phydev: The PHY device bus
 122  * @prtad: MMD Address
 123  * @devad: MMD DEVAD
 124  * @addr: PHY address on the MII bus
 125  *
 126  * Description: it reads data from the MMD registers (clause 22 to access to
 127  * clause 45) of the specified phy address.
 128  * To read these registers we have:
 129  * 1) Write reg 13 // DEVAD
 130  * 2) Write reg 14 // MMD Address
 131  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
 132  * 3) Read  reg 14 // Read MMD data
 133  */
 134 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
 135                           int devad, int addr)
 136 {
 137         int value = -1;
 138
 139         /* Write the desired MMD Devad */
 140         phy_write(phydev, addr, MII_MMD_CTRL, devad);
 141
 142         /* Write the desired MMD register address */
 143         phy_write(phydev, addr, MII_MMD_DATA, prtad);
 144
 145         /* Select the Function : DATA with no post increment */
 146         phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 147
 148         /* Read the content of the MMD's selected register */
 149         value = phy_read(phydev, addr, MII_MMD_DATA);
 150         return value;
 151 }
 152
 153 /**
 154  * phy_write_mmd_indirect - writes data to the MMD registers
 155  * @phydev: The PHY device
 156  * @prtad: MMD Address
 157  * @devad: MMD DEVAD
 158  * @addr: PHY address on the MII bus
 159  * @data: data to write in the MMD register
 160  *
 161  * Description: Write data from the MMD registers of the specified
 162  * phy address.
 163  * To write these registers we have:
 164  * 1) Write reg 13 // DEVAD
 165  * 2) Write reg 14 // MMD Address
 166  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
 167  * 3) Write reg 14 // Write MMD data
 168  */
 169 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
 170                             int devad, int addr, u32 data)
 171 {
 172         /* Write the desired MMD Devad */
 173         phy_write(phydev, addr, MII_MMD_CTRL, devad);
 174
 175         /* Write the desired MMD register address */
 176         phy_write(phydev, addr, MII_MMD_DATA, prtad);
 177
 178         /* Select the Function : DATA with no post increment */
 179         phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 180
 181         /* Write the data into MMD's selected register */
 182         phy_write(phydev, addr, MII_MMD_DATA, data);
 183 }
 184
 185 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 186 {
 187         struct dp83867_private *dp83867 =
 188                 (struct dp83867_private *)phydev->priv;
 189         u16 val;
 190
 191         val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
 192                                     phydev->addr);
 193
 194         if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
 195                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 196         else
 197                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 198
 199         phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
 200                                phydev->addr, val);
 201
 202         return 0;
 203 }
 204
 205 #if defined(CONFIG_DM_ETH)
 206 /**
 207  * dp83867_data_init - Convenience function for setting PHY specific data
 208  *
 209  * @phydev: the phy_device struct
 210  */
 211 static int dp83867_of_init(struct phy_device *phydev)
 212 {
 213         struct dp83867_private *dp83867 = phydev->priv;
 214         ofnode node;
 215         u16 val;
 216
 217         /* Optional configuration */
 218
 219         /*
 220          * Keep the default value if ti,clk-output-sel is not set
 221          * or to high
 222          */
 223
 224         dp83867->clk_output_sel =
 225                 ofnode_read_u32_default(node, "ti,clk-output-sel",
 226                                         DP83867_CLK_O_SEL_REF_CLK);
 227
 228         node = phy_get_ofnode(phydev);
 229         if (!ofnode_valid(node))
 230                 return -EINVAL;
 231
 232         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 233                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 234         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 235                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 236         else
 237                 dp83867->io_impedance = -EINVAL;
 238
 239         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 240                 dp83867->rxctrl_strap_quirk = true;
 241         dp83867->rx_id_delay = ofnode_read_u32_default(node,
 242                                                        "ti,rx-internal-delay",
 243                                                        -1);
 244
 245         dp83867->tx_id_delay = ofnode_read_u32_default(node,
 246                                                        "ti,tx-internal-delay",
 247                                                        -1);
 248
 249         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 250                                                       -1);
 251         if (ofnode_read_bool(node, "enet-phy-lane-swap"))
 252                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
 253
 254         if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 255                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 256
 257
 258         /* Clock output selection if muxing property is set */
 259         if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
 260                 val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 261                                             DP83867_DEVADDR, phydev->addr);
 262                 val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 263                 val |= (dp83867->clk_output_sel <<
 264                         DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 265                 phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 266                                        DP83867_DEVADDR, phydev->addr, val);
 267         }
 268
 269         return 0;
 270 }
 271 #else
 272 static int dp83867_of_init(struct phy_device *phydev)
 273 {
 274         struct dp83867_private *dp83867 = phydev->priv;
 275
 276         dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
 277         dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
 278         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 279         dp83867->io_impedance = -EINVAL;
 280
 281         return 0;
 282 }
 283 #endif
 284
 285 static int dp83867_config(struct phy_device *phydev)
 286 {
 287         struct dp83867_private *dp83867;
 288         unsigned int val, delay, cfg2;
 289         int ret, bs;
 290
 291         if (!phydev->priv) {
 292                 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 293                 if (!dp83867)
 294                         return -ENOMEM;
 295
 296                 phydev->priv = dp83867;
 297                 ret = dp83867_of_init(phydev);
 298                 if (ret)
 299                         goto err_out;
 300         } else {
 301                 dp83867 = (struct dp83867_private *)phydev->priv;
 302         }
 303
 304         /* Restart the PHY.  */
 305         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 306         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 307                   val | DP83867_SW_RESTART);
 308
 309         /* Mode 1 or 2 workaround */
 310         if (dp83867->rxctrl_strap_quirk) {
 311                 val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
 312                                             DP83867_DEVADDR, phydev->addr);
 313                 val &= ~BIT(7);
 314                 phy_write_mmd_indirect(phydev, DP83867_CFG4,
 315                                        DP83867_DEVADDR, phydev->addr, val);
 316         }
 317
 318         if (phy_interface_is_rgmii(phydev)) {
 319                 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 320                         (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
 321                         (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 322                 if (ret)
 323                         goto err_out;
 324
 325                 /* The code below checks if "port mirroring" N/A MODE4 has been
 326                  * enabled during power on bootstrap.
 327                  *
 328                  * Such N/A mode enabled by mistake can put PHY IC in some
 329                  * internal testing mode and disable RGMII transmission.
 330                  *
 331                  * In this particular case one needs to check STRAP_STS1
 332                  * register's bit 11 (marked as RESERVED).
 333                  */
 334
 335                 bs = phy_read_mmd_indirect(phydev, DP83867_STRAP_STS1,
 336                                            DP83867_DEVADDR, phydev->addr);
 337                 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
 338                 if (bs & DP83867_STRAP_STS1_RESERVED) {
 339                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 340                         phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 341                                   val);
 342                 }
 343
 344         } else if (phy_interface_is_sgmii(phydev)) {
 345                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 346                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 347
 348                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 349                 cfg2 &= MII_DP83867_CFG2_MASK;
 350                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 351                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 352                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 353                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 354                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 355                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 356
 357                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 358                                        DP83867_DEVADDR, phydev->addr, 0x0);
 359
 360                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 361                           DP83867_PHYCTRL_SGMIIEN |
 362                           (DP83867_MDI_CROSSOVER_MDIX <<
 363                           DP83867_MDI_CROSSOVER) |
 364                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 365                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 366                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 367         }
 368
 369         if (phy_interface_is_rgmii(phydev)) {
 370                 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 371                                             DP83867_DEVADDR, phydev->addr);
 372
 373                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 374                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 375                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 376
 377                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 378                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 379
 380                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 381                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 382
 383                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 384                                        DP83867_DEVADDR, phydev->addr, val);
 385
 386                 delay = (dp83867->rx_id_delay |
 387                          (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 388
 389                 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 390                                        DP83867_DEVADDR, phydev->addr, delay);
 391
 392                 if (dp83867->io_impedance >= 0) {
 393                         val = phy_read_mmd_indirect(phydev,
 394                                                     DP83867_IO_MUX_CFG,
 395                                                     DP83867_DEVADDR,
 396                                                     phydev->addr);
 397                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 398                         val |= dp83867->io_impedance &
 399                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 400                         phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 401                                                DP83867_DEVADDR, phydev->addr,
 402                                                val);
 403                 }
 404         }
 405
 406         if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
 407                 dp83867_config_port_mirroring(phydev);
 408
 409         genphy_config_aneg(phydev);
 410         return 0;
 411
 412 err_out:
 413         kfree(dp83867);
 414         return ret;
 415 }
 416
 417 static struct phy_driver DP83867_driver = {
 418         .name = "TI DP83867",
 419         .uid = 0x2000a231,
 420         .mask = 0xfffffff0,
 421         .features = PHY_GBIT_FEATURES,
 422         .config = &dp83867_config,
 423         .startup = &genphy_startup,
 424         .shutdown = &genphy_shutdown,
 425 };
 426
 427 int phy_ti_init(void)
 428 {
 429         phy_register(&DP83867_driver);
 430         return 0;
 431 }