1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/compat.h>
12 #include <dt-bindings/net/ti-dp83867.h>
16 #define DP83867_DEVADDR 0x1f
18 #define MII_DP83867_PHYCTRL 0x10
19 #define MII_DP83867_MICR 0x12
20 #define MII_DP83867_CFG2 0x14
21 #define MII_DP83867_BISCR 0x16
22 #define DP83867_CTRL 0x1f
24 /* Extended Registers */
25 #define DP83867_CFG4 0x0031
26 #define DP83867_RGMIICTL 0x0032
27 #define DP83867_RGMIIDCTL 0x0086
28 #define DP83867_IO_MUX_CFG 0x0170
30 #define DP83867_SW_RESET BIT(15)
31 #define DP83867_SW_RESTART BIT(14)
33 /* MICR Interrupt bits */
34 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
35 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
36 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
37 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
38 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
39 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
40 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
41 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
42 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
43 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
44 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
45 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
48 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
49 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
52 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
53 #define DP83867_MDI_CROSSOVER 5
54 #define DP83867_MDI_CROSSOVER_AUTO 2
55 #define DP83867_MDI_CROSSOVER_MDIX 2
56 #define DP83867_PHYCTRL_SGMIIEN 0x0800
57 #define DP83867_PHYCTRL_RXFIFO_SHIFT 12
58 #define DP83867_PHYCTRL_TXFIFO_SHIFT 14
61 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
64 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
65 #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
66 #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
67 #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
68 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
69 #define MII_DP83867_CFG2_MASK 0x003F
71 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
72 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
74 /* MMD Access Control register fields */
75 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
76 #define MII_MMD_CTRL_ADDR 0x0000 /* Address */
77 #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */
78 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */
79 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
81 /* User setting - can be taken from DTS */
82 #define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS
83 #define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS
84 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
87 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
89 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
90 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
92 struct dp83867_private {
97 bool rxctrl_strap_quirk;
101 * phy_read_mmd_indirect - reads data from the MMD registers
102 * @phydev: The PHY device bus
103 * @prtad: MMD Address
105 * @addr: PHY address on the MII bus
107 * Description: it reads data from the MMD registers (clause 22 to access to
108 * clause 45) of the specified phy address.
109 * To read these registers we have:
110 * 1) Write reg 13 // DEVAD
111 * 2) Write reg 14 // MMD Address
112 * 3) Write reg 13 // MMD Data Command for MMD DEVAD
113 * 3) Read reg 14 // Read MMD data
115 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
120 /* Write the desired MMD Devad */
121 phy_write(phydev, addr, MII_MMD_CTRL, devad);
123 /* Write the desired MMD register address */
124 phy_write(phydev, addr, MII_MMD_DATA, prtad);
126 /* Select the Function : DATA with no post increment */
127 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
129 /* Read the content of the MMD's selected register */
130 value = phy_read(phydev, addr, MII_MMD_DATA);
135 * phy_write_mmd_indirect - writes data to the MMD registers
136 * @phydev: The PHY device
137 * @prtad: MMD Address
139 * @addr: PHY address on the MII bus
140 * @data: data to write in the MMD register
142 * Description: Write data from the MMD registers of the specified
144 * To write these registers we have:
145 * 1) Write reg 13 // DEVAD
146 * 2) Write reg 14 // MMD Address
147 * 3) Write reg 13 // MMD Data Command for MMD DEVAD
148 * 3) Write reg 14 // Write MMD data
150 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
151 int devad, int addr, u32 data)
153 /* Write the desired MMD Devad */
154 phy_write(phydev, addr, MII_MMD_CTRL, devad);
156 /* Write the desired MMD register address */
157 phy_write(phydev, addr, MII_MMD_DATA, prtad);
159 /* Select the Function : DATA with no post increment */
160 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
162 /* Write the data into MMD's selected register */
163 phy_write(phydev, addr, MII_MMD_DATA, data);
166 #if defined(CONFIG_DM_ETH)
168 * dp83867_data_init - Convenience function for setting PHY specific data
170 * @phydev: the phy_device struct
172 static int dp83867_of_init(struct phy_device *phydev)
174 struct dp83867_private *dp83867 = phydev->priv;
177 node = phy_get_ofnode(phydev);
178 if (!ofnode_valid(node))
181 if (ofnode_read_bool(node, "ti,max-output-impedance"))
182 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
183 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
184 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
186 dp83867->io_impedance = -EINVAL;
188 if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
189 dp83867->rxctrl_strap_quirk = true;
190 dp83867->rx_id_delay = ofnode_read_u32_default(node,
191 "ti,rx-internal-delay",
194 dp83867->tx_id_delay = ofnode_read_u32_default(node,
195 "ti,tx-internal-delay",
198 dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
204 static int dp83867_of_init(struct phy_device *phydev)
206 struct dp83867_private *dp83867 = phydev->priv;
208 dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
209 dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
210 dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
211 dp83867->io_impedance = -EINVAL;
217 static int dp83867_config(struct phy_device *phydev)
219 struct dp83867_private *dp83867;
220 unsigned int val, delay, cfg2;
224 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
228 phydev->priv = dp83867;
229 ret = dp83867_of_init(phydev);
233 dp83867 = (struct dp83867_private *)phydev->priv;
236 /* Restart the PHY. */
237 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
238 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
239 val | DP83867_SW_RESTART);
241 /* Mode 1 or 2 workaround */
242 if (dp83867->rxctrl_strap_quirk) {
243 val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
244 DP83867_DEVADDR, phydev->addr);
246 phy_write_mmd_indirect(phydev, DP83867_CFG4,
247 DP83867_DEVADDR, phydev->addr, val);
250 if (phy_interface_is_rgmii(phydev)) {
251 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
252 (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
253 (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
256 } else if (phy_interface_is_sgmii(phydev)) {
257 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
258 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
260 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
261 cfg2 &= MII_DP83867_CFG2_MASK;
262 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
263 MII_DP83867_CFG2_SGMII_AUTONEGEN |
264 MII_DP83867_CFG2_SPEEDOPT_ENH |
265 MII_DP83867_CFG2_SPEEDOPT_CNT |
266 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
267 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
269 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
270 DP83867_DEVADDR, phydev->addr, 0x0);
272 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
273 DP83867_PHYCTRL_SGMIIEN |
274 (DP83867_MDI_CROSSOVER_MDIX <<
275 DP83867_MDI_CROSSOVER) |
276 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
277 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
278 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
281 if (phy_interface_is_rgmii(phydev)) {
282 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
283 DP83867_DEVADDR, phydev->addr);
285 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
286 val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
287 DP83867_RGMII_RX_CLK_DELAY_EN);
289 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
290 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
292 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
293 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
295 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
296 DP83867_DEVADDR, phydev->addr, val);
298 delay = (dp83867->rx_id_delay |
299 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
301 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
302 DP83867_DEVADDR, phydev->addr, delay);
304 if (dp83867->io_impedance >= 0) {
305 val = phy_read_mmd_indirect(phydev,
309 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
310 val |= dp83867->io_impedance &
311 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
312 phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
313 DP83867_DEVADDR, phydev->addr,
318 genphy_config_aneg(phydev);
326 static struct phy_driver DP83867_driver = {
327 .name = "TI DP83867",
330 .features = PHY_GBIT_FEATURES,
331 .config = &dp83867_config,
332 .startup = &genphy_startup,
333 .shutdown = &genphy_shutdown,
336 int phy_ti_init(void)
338 phy_register(&DP83867_driver);