drivers/net/phy/ti.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <linux/compat.h>
   9 #include <malloc.h>
  10
  11 #include <dm.h>
  12 #include <dt-bindings/net/ti-dp83867.h>
  13
  14
  15 /* TI DP83867 */
  16 #define DP83867_DEVADDR         0x1f
  17
  18 #define MII_DP83867_PHYCTRL     0x10
  19 #define MII_DP83867_MICR        0x12
  20 #define MII_DP83867_CFG2        0x14
  21 #define MII_DP83867_BISCR       0x16
  22 #define DP83867_CTRL            0x1f
  23
  24 /* Extended Registers */
  25 #define DP83867_CFG4            0x0031
  26 #define DP83867_RGMIICTL        0x0032
  27 #define DP83867_RGMIIDCTL       0x0086
  28 #define DP83867_IO_MUX_CFG      0x0170
  29
  30 #define DP83867_SW_RESET        BIT(15)
  31 #define DP83867_SW_RESTART      BIT(14)
  32
  33 /* MICR Interrupt bits */
  34 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  35 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  36 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  37 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  38 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  39 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  40 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  41 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  42 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  43 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  44 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  45 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  46
  47 /* RGMIICTL bits */
  48 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  49 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  50
  51 /* PHY CTRL bits */
  52 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  53 #define DP83867_MDI_CROSSOVER           5
  54 #define DP83867_MDI_CROSSOVER_AUTO      2
  55 #define DP83867_MDI_CROSSOVER_MDIX      2
  56 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  57 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  58 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  59
  60 /* RGMIIDCTL bits */
  61 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  62
  63 /* CFG2 bits */
  64 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  65 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  66 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  67 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  68 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  69 #define MII_DP83867_CFG2_MASK                   0x003F
  70
  71 #define MII_MMD_CTRL    0x0d /* MMD Access Control Register */
  72 #define MII_MMD_DATA    0x0e /* MMD Access Data Register */
  73
  74 /* MMD Access Control register fields */
  75 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
  76 #define MII_MMD_CTRL_ADDR       0x0000 /* Address */
  77 #define MII_MMD_CTRL_NOINCR     0x4000 /* no post increment */
  78 #define MII_MMD_CTRL_INCR_RDWT  0x8000 /* post increment on reads & writes */
  79 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
  80
  81 /* User setting - can be taken from DTS */
  82 #define DEFAULT_RX_ID_DELAY     DP83867_RGMIIDCTL_2_25_NS
  83 #define DEFAULT_TX_ID_DELAY     DP83867_RGMIIDCTL_2_75_NS
  84 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  85
  86 /* IO_MUX_CFG bits */
  87 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  88
  89 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  90 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  91
  92 /* CFG4 bits */
  93 #define DP83867_CFG4_PORT_MIRROR_EN             BIT(0)
  94
  95 enum {
  96         DP83867_PORT_MIRRORING_KEEP,
  97         DP83867_PORT_MIRRORING_EN,
  98         DP83867_PORT_MIRRORING_DIS,
  99 };
 100
 101 struct dp83867_private {
 102         int rx_id_delay;
 103         int tx_id_delay;
 104         int fifo_depth;
 105         int io_impedance;
 106         bool rxctrl_strap_quirk;
 107         int port_mirroring;
 108 };
 109
 110 /**
 111  * phy_read_mmd_indirect - reads data from the MMD registers
 112  * @phydev: The PHY device bus
 113  * @prtad: MMD Address
 114  * @devad: MMD DEVAD
 115  * @addr: PHY address on the MII bus
 116  *
 117  * Description: it reads data from the MMD registers (clause 22 to access to
 118  * clause 45) of the specified phy address.
 119  * To read these registers we have:
 120  * 1) Write reg 13 // DEVAD
 121  * 2) Write reg 14 // MMD Address
 122  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
 123  * 3) Read  reg 14 // Read MMD data
 124  */
 125 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
 126                           int devad, int addr)
 127 {
 128         int value = -1;
 129
 130         /* Write the desired MMD Devad */
 131         phy_write(phydev, addr, MII_MMD_CTRL, devad);
 132
 133         /* Write the desired MMD register address */
 134         phy_write(phydev, addr, MII_MMD_DATA, prtad);
 135
 136         /* Select the Function : DATA with no post increment */
 137         phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 138
 139         /* Read the content of the MMD's selected register */
 140         value = phy_read(phydev, addr, MII_MMD_DATA);
 141         return value;
 142 }
 143
 144 /**
 145  * phy_write_mmd_indirect - writes data to the MMD registers
 146  * @phydev: The PHY device
 147  * @prtad: MMD Address
 148  * @devad: MMD DEVAD
 149  * @addr: PHY address on the MII bus
 150  * @data: data to write in the MMD register
 151  *
 152  * Description: Write data from the MMD registers of the specified
 153  * phy address.
 154  * To write these registers we have:
 155  * 1) Write reg 13 // DEVAD
 156  * 2) Write reg 14 // MMD Address
 157  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
 158  * 3) Write reg 14 // Write MMD data
 159  */
 160 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
 161                             int devad, int addr, u32 data)
 162 {
 163         /* Write the desired MMD Devad */
 164         phy_write(phydev, addr, MII_MMD_CTRL, devad);
 165
 166         /* Write the desired MMD register address */
 167         phy_write(phydev, addr, MII_MMD_DATA, prtad);
 168
 169         /* Select the Function : DATA with no post increment */
 170         phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 171
 172         /* Write the data into MMD's selected register */
 173         phy_write(phydev, addr, MII_MMD_DATA, data);
 174 }
 175
 176 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 177 {
 178         struct dp83867_private *dp83867 =
 179                 (struct dp83867_private *)phydev->priv;
 180         u16 val;
 181
 182         val = phy_read_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
 183                                     phydev->addr);
 184
 185         if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
 186                 val |= DP83867_CFG4_PORT_MIRROR_EN;
 187         else
 188                 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
 189
 190         phy_write_mmd_indirect(phydev, DP83867_CFG4, DP83867_DEVADDR,
 191                                phydev->addr, val);
 192
 193         return 0;
 194 }
 195
 196 #if defined(CONFIG_DM_ETH)
 197 /**
 198  * dp83867_data_init - Convenience function for setting PHY specific data
 199  *
 200  * @phydev: the phy_device struct
 201  */
 202 static int dp83867_of_init(struct phy_device *phydev)
 203 {
 204         struct dp83867_private *dp83867 = phydev->priv;
 205         ofnode node;
 206
 207         node = phy_get_ofnode(phydev);
 208         if (!ofnode_valid(node))
 209                 return -EINVAL;
 210
 211         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 212                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 213         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 214                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 215         else
 216                 dp83867->io_impedance = -EINVAL;
 217
 218         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 219                 dp83867->rxctrl_strap_quirk = true;
 220         dp83867->rx_id_delay = ofnode_read_u32_default(node,
 221                                                        "ti,rx-internal-delay",
 222                                                        -1);
 223
 224         dp83867->tx_id_delay = ofnode_read_u32_default(node,
 225                                                        "ti,tx-internal-delay",
 226                                                        -1);
 227
 228         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 229                                                       -1);
 230         if (ofnode_read_bool(node, "enet-phy-lane-swap"))
 231                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
 232
 233         if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
 234                 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
 235
 236
 237         return 0;
 238 }
 239 #else
 240 static int dp83867_of_init(struct phy_device *phydev)
 241 {
 242         struct dp83867_private *dp83867 = phydev->priv;
 243
 244         dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
 245         dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
 246         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 247         dp83867->io_impedance = -EINVAL;
 248
 249         return 0;
 250 }
 251 #endif
 252
 253 static int dp83867_config(struct phy_device *phydev)
 254 {
 255         struct dp83867_private *dp83867;
 256         unsigned int val, delay, cfg2;
 257         int ret;
 258
 259         if (!phydev->priv) {
 260                 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 261                 if (!dp83867)
 262                         return -ENOMEM;
 263
 264                 phydev->priv = dp83867;
 265                 ret = dp83867_of_init(phydev);
 266                 if (ret)
 267                         goto err_out;
 268         } else {
 269                 dp83867 = (struct dp83867_private *)phydev->priv;
 270         }
 271
 272         /* Restart the PHY.  */
 273         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 274         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 275                   val | DP83867_SW_RESTART);
 276
 277         /* Mode 1 or 2 workaround */
 278         if (dp83867->rxctrl_strap_quirk) {
 279                 val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
 280                                             DP83867_DEVADDR, phydev->addr);
 281                 val &= ~BIT(7);
 282                 phy_write_mmd_indirect(phydev, DP83867_CFG4,
 283                                        DP83867_DEVADDR, phydev->addr, val);
 284         }
 285
 286         if (phy_interface_is_rgmii(phydev)) {
 287                 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 288                         (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
 289                         (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 290                 if (ret)
 291                         goto err_out;
 292         } else if (phy_interface_is_sgmii(phydev)) {
 293                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 294                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 295
 296                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 297                 cfg2 &= MII_DP83867_CFG2_MASK;
 298                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 299                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 300                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 301                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 302                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 303                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 304
 305                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 306                                        DP83867_DEVADDR, phydev->addr, 0x0);
 307
 308                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 309                           DP83867_PHYCTRL_SGMIIEN |
 310                           (DP83867_MDI_CROSSOVER_MDIX <<
 311                           DP83867_MDI_CROSSOVER) |
 312                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 313                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 314                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 315         }
 316
 317         if (phy_interface_is_rgmii(phydev)) {
 318                 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 319                                             DP83867_DEVADDR, phydev->addr);
 320
 321                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 322                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 323                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 324
 325                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 326                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 327
 328                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 329                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 330
 331                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 332                                        DP83867_DEVADDR, phydev->addr, val);
 333
 334                 delay = (dp83867->rx_id_delay |
 335                          (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 336
 337                 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 338                                        DP83867_DEVADDR, phydev->addr, delay);
 339
 340                 if (dp83867->io_impedance >= 0) {
 341                         val = phy_read_mmd_indirect(phydev,
 342                                                     DP83867_IO_MUX_CFG,
 343                                                     DP83867_DEVADDR,
 344                                                     phydev->addr);
 345                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 346                         val |= dp83867->io_impedance &
 347                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 348                         phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 349                                                DP83867_DEVADDR, phydev->addr,
 350                                                val);
 351                 }
 352         }
 353
 354         if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
 355                 dp83867_config_port_mirroring(phydev);
 356
 357         genphy_config_aneg(phydev);
 358         return 0;
 359
 360 err_out:
 361         kfree(dp83867);
 362         return ret;
 363 }
 364
 365 static struct phy_driver DP83867_driver = {
 366         .name = "TI DP83867",
 367         .uid = 0x2000a231,
 368         .mask = 0xfffffff0,
 369         .features = PHY_GBIT_FEATURES,
 370         .config = &dp83867_config,
 371         .startup = &genphy_startup,
 372         .shutdown = &genphy_shutdown,
 373 };
 374
 375 int phy_ti_init(void)
 376 {
 377         phy_register(&DP83867_driver);
 378         return 0;
 379 }