1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/compat.h>
12 #include <dt-bindings/net/ti-dp83867.h>
16 #define DP83867_DEVADDR 0x1f
18 #define MII_DP83867_PHYCTRL 0x10
19 #define MII_DP83867_MICR 0x12
20 #define MII_DP83867_CFG2 0x14
21 #define MII_DP83867_BISCR 0x16
22 #define DP83867_CTRL 0x1f
24 /* Extended Registers */
25 #define DP83867_CFG4 0x0031
26 #define DP83867_RGMIICTL 0x0032
27 #define DP83867_STRAP_STS1 0x006E
28 #define DP83867_RGMIIDCTL 0x0086
29 #define DP83867_IO_MUX_CFG 0x0170
31 #define DP83867_SW_RESET BIT(15)
32 #define DP83867_SW_RESTART BIT(14)
34 /* MICR Interrupt bits */
35 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
36 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
37 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
38 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
39 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
40 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
41 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
42 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
43 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
44 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
45 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
46 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
49 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
50 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
53 #define DP83867_STRAP_STS1_RESERVED BIT(11)
56 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
57 #define DP83867_PHYCR_RESERVED_MASK BIT(11)
58 #define DP83867_MDI_CROSSOVER 5
59 #define DP83867_MDI_CROSSOVER_AUTO 2
60 #define DP83867_MDI_CROSSOVER_MDIX 2
61 #define DP83867_PHYCTRL_SGMIIEN 0x0800
62 #define DP83867_PHYCTRL_RXFIFO_SHIFT 12
63 #define DP83867_PHYCTRL_TXFIFO_SHIFT 14
66 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
69 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040
70 #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080
71 #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100
72 #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800
73 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000
74 #define MII_DP83867_CFG2_MASK 0x003F
76 /* User setting - can be taken from DTS */
77 #define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS
78 #define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS
79 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
82 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
84 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
85 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
86 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
87 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK \
88 GENMASK(0x1f, DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT)
91 #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
94 DP83867_PORT_MIRRORING_KEEP,
95 DP83867_PORT_MIRRORING_EN,
96 DP83867_PORT_MIRRORING_DIS,
99 struct dp83867_private {
104 bool rxctrl_strap_quirk;
109 static int dp83867_config_port_mirroring(struct phy_device *phydev)
111 struct dp83867_private *dp83867 =
112 (struct dp83867_private *)phydev->priv;
115 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
117 if (dp83867->port_mirroring == DP83867_PORT_MIRRORING_EN)
118 val |= DP83867_CFG4_PORT_MIRROR_EN;
120 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
122 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
127 #if defined(CONFIG_DM_ETH)
129 * dp83867_data_init - Convenience function for setting PHY specific data
131 * @phydev: the phy_device struct
133 static int dp83867_of_init(struct phy_device *phydev)
135 struct dp83867_private *dp83867 = phydev->priv;
139 /* Optional configuration */
142 * Keep the default value if ti,clk-output-sel is not set
146 dp83867->clk_output_sel =
147 ofnode_read_u32_default(node, "ti,clk-output-sel",
148 DP83867_CLK_O_SEL_REF_CLK);
150 node = phy_get_ofnode(phydev);
151 if (!ofnode_valid(node))
154 if (ofnode_read_bool(node, "ti,max-output-impedance"))
155 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
156 else if (ofnode_read_bool(node, "ti,min-output-impedance"))
157 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
159 dp83867->io_impedance = -EINVAL;
161 if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
162 dp83867->rxctrl_strap_quirk = true;
163 dp83867->rx_id_delay = ofnode_read_u32_default(node,
164 "ti,rx-internal-delay",
167 dp83867->tx_id_delay = ofnode_read_u32_default(node,
168 "ti,tx-internal-delay",
171 dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
173 if (ofnode_read_bool(node, "enet-phy-lane-swap"))
174 dp83867->port_mirroring = DP83867_PORT_MIRRORING_EN;
176 if (ofnode_read_bool(node, "enet-phy-lane-no-swap"))
177 dp83867->port_mirroring = DP83867_PORT_MIRRORING_DIS;
180 /* Clock output selection if muxing property is set */
181 if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
182 val = phy_read_mmd(phydev, DP83867_DEVADDR,
184 val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
185 val |= (dp83867->clk_output_sel <<
186 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
187 phy_write_mmd(phydev, DP83867_DEVADDR,
188 DP83867_IO_MUX_CFG, val);
194 static int dp83867_of_init(struct phy_device *phydev)
196 struct dp83867_private *dp83867 = phydev->priv;
198 dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
199 dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
200 dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
201 dp83867->io_impedance = -EINVAL;
207 static int dp83867_config(struct phy_device *phydev)
209 struct dp83867_private *dp83867;
210 unsigned int val, delay, cfg2;
214 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
218 phydev->priv = dp83867;
219 ret = dp83867_of_init(phydev);
223 dp83867 = (struct dp83867_private *)phydev->priv;
226 /* Restart the PHY. */
227 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
228 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
229 val | DP83867_SW_RESTART);
231 /* Mode 1 or 2 workaround */
232 if (dp83867->rxctrl_strap_quirk) {
233 val = phy_read_mmd(phydev, DP83867_DEVADDR,
236 phy_write_mmd(phydev, DP83867_DEVADDR,
240 if (phy_interface_is_rgmii(phydev)) {
241 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
242 (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
243 (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
247 /* The code below checks if "port mirroring" N/A MODE4 has been
248 * enabled during power on bootstrap.
250 * Such N/A mode enabled by mistake can put PHY IC in some
251 * internal testing mode and disable RGMII transmission.
253 * In this particular case one needs to check STRAP_STS1
254 * register's bit 11 (marked as RESERVED).
257 bs = phy_read_mmd(phydev, DP83867_DEVADDR,
259 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL);
260 if (bs & DP83867_STRAP_STS1_RESERVED) {
261 val &= ~DP83867_PHYCR_RESERVED_MASK;
262 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
266 } else if (phy_interface_is_sgmii(phydev)) {
267 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
268 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
270 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
271 cfg2 &= MII_DP83867_CFG2_MASK;
272 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
273 MII_DP83867_CFG2_SGMII_AUTONEGEN |
274 MII_DP83867_CFG2_SPEEDOPT_ENH |
275 MII_DP83867_CFG2_SPEEDOPT_CNT |
276 MII_DP83867_CFG2_SPEEDOPT_INTLOW);
277 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
279 phy_write_mmd(phydev, DP83867_DEVADDR,
280 DP83867_RGMIICTL, 0x0);
282 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
283 DP83867_PHYCTRL_SGMIIEN |
284 (DP83867_MDI_CROSSOVER_MDIX <<
285 DP83867_MDI_CROSSOVER) |
286 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
287 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
288 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
291 if (phy_interface_is_rgmii(phydev)) {
292 val = phy_read_mmd(phydev, DP83867_DEVADDR,
295 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
296 val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
297 DP83867_RGMII_RX_CLK_DELAY_EN);
299 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
300 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
302 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
303 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
305 phy_write_mmd(phydev, DP83867_DEVADDR,
306 DP83867_RGMIICTL, val);
308 delay = (dp83867->rx_id_delay |
309 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
311 phy_write_mmd(phydev, DP83867_DEVADDR,
312 DP83867_RGMIIDCTL, delay);
314 if (dp83867->io_impedance >= 0) {
315 val = phy_read_mmd(phydev,
318 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
319 val |= dp83867->io_impedance &
320 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
321 phy_write_mmd(phydev, DP83867_DEVADDR,
322 DP83867_IO_MUX_CFG, val);
326 if (dp83867->port_mirroring != DP83867_PORT_MIRRORING_KEEP)
327 dp83867_config_port_mirroring(phydev);
329 genphy_config_aneg(phydev);
337 static struct phy_driver DP83867_driver = {
338 .name = "TI DP83867",
341 .features = PHY_GBIT_FEATURES,
342 .config = &dp83867_config,
343 .startup = &genphy_startup,
344 .shutdown = &genphy_shutdown,
347 int phy_ti_init(void)
349 phy_register(&DP83867_driver);