drivers/net/phy/ti.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * TI PHY drivers
   4  *
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <linux/compat.h>
   9 #include <malloc.h>
  10
  11 #include <dm.h>
  12 #include <dt-bindings/net/ti-dp83867.h>
  13
  14
  15 /* TI DP83867 */
  16 #define DP83867_DEVADDR         0x1f
  17
  18 #define MII_DP83867_PHYCTRL     0x10
  19 #define MII_DP83867_MICR        0x12
  20 #define MII_DP83867_CFG2        0x14
  21 #define MII_DP83867_BISCR       0x16
  22 #define DP83867_CTRL            0x1f
  23
  24 /* Extended Registers */
  25 #define DP83867_CFG4            0x0031
  26 #define DP83867_RGMIICTL        0x0032
  27 #define DP83867_RGMIIDCTL       0x0086
  28 #define DP83867_IO_MUX_CFG      0x0170
  29
  30 #define DP83867_SW_RESET        BIT(15)
  31 #define DP83867_SW_RESTART      BIT(14)
  32
  33 /* MICR Interrupt bits */
  34 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  35 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  36 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  37 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  38 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  39 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  40 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  41 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  42 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  43 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  44 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  45 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  46
  47 /* RGMIICTL bits */
  48 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  49 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  50
  51 /* PHY CTRL bits */
  52 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  53 #define DP83867_MDI_CROSSOVER           5
  54 #define DP83867_MDI_CROSSOVER_AUTO      2
  55 #define DP83867_MDI_CROSSOVER_MDIX      2
  56 #define DP83867_PHYCTRL_SGMIIEN                 0x0800
  57 #define DP83867_PHYCTRL_RXFIFO_SHIFT    12
  58 #define DP83867_PHYCTRL_TXFIFO_SHIFT    14
  59
  60 /* RGMIIDCTL bits */
  61 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  62
  63 /* CFG2 bits */
  64 #define MII_DP83867_CFG2_SPEEDOPT_10EN          0x0040
  65 #define MII_DP83867_CFG2_SGMII_AUTONEGEN        0x0080
  66 #define MII_DP83867_CFG2_SPEEDOPT_ENH           0x0100
  67 #define MII_DP83867_CFG2_SPEEDOPT_CNT           0x0800
  68 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW        0x2000
  69 #define MII_DP83867_CFG2_MASK                   0x003F
  70
  71 #define MII_MMD_CTRL    0x0d /* MMD Access Control Register */
  72 #define MII_MMD_DATA    0x0e /* MMD Access Data Register */
  73
  74 /* MMD Access Control register fields */
  75 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/
  76 #define MII_MMD_CTRL_ADDR       0x0000 /* Address */
  77 #define MII_MMD_CTRL_NOINCR     0x4000 /* no post increment */
  78 #define MII_MMD_CTRL_INCR_RDWT  0x8000 /* post increment on reads & writes */
  79 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */
  80
  81 /* User setting - can be taken from DTS */
  82 #define DEFAULT_RX_ID_DELAY     DP83867_RGMIIDCTL_2_25_NS
  83 #define DEFAULT_TX_ID_DELAY     DP83867_RGMIIDCTL_2_75_NS
  84 #define DEFAULT_FIFO_DEPTH      DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
  85
  86 /* IO_MUX_CFG bits */
  87 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  88
  89 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  90 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  91
  92 struct dp83867_private {
  93         int rx_id_delay;
  94         int tx_id_delay;
  95         int fifo_depth;
  96         int io_impedance;
  97         bool rxctrl_strap_quirk;
  98 };
  99
 100 /**
 101  * phy_read_mmd_indirect - reads data from the MMD registers
 102  * @phydev: The PHY device bus
 103  * @prtad: MMD Address
 104  * @devad: MMD DEVAD
 105  * @addr: PHY address on the MII bus
 106  *
 107  * Description: it reads data from the MMD registers (clause 22 to access to
 108  * clause 45) of the specified phy address.
 109  * To read these registers we have:
 110  * 1) Write reg 13 // DEVAD
 111  * 2) Write reg 14 // MMD Address
 112  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
 113  * 3) Read  reg 14 // Read MMD data
 114  */
 115 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
 116                           int devad, int addr)
 117 {
 118         int value = -1;
 119
 120         /* Write the desired MMD Devad */
 121         phy_write(phydev, addr, MII_MMD_CTRL, devad);
 122
 123         /* Write the desired MMD register address */
 124         phy_write(phydev, addr, MII_MMD_DATA, prtad);
 125
 126         /* Select the Function : DATA with no post increment */
 127         phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 128
 129         /* Read the content of the MMD's selected register */
 130         value = phy_read(phydev, addr, MII_MMD_DATA);
 131         return value;
 132 }
 133
 134 /**
 135  * phy_write_mmd_indirect - writes data to the MMD registers
 136  * @phydev: The PHY device
 137  * @prtad: MMD Address
 138  * @devad: MMD DEVAD
 139  * @addr: PHY address on the MII bus
 140  * @data: data to write in the MMD register
 141  *
 142  * Description: Write data from the MMD registers of the specified
 143  * phy address.
 144  * To write these registers we have:
 145  * 1) Write reg 13 // DEVAD
 146  * 2) Write reg 14 // MMD Address
 147  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
 148  * 3) Write reg 14 // Write MMD data
 149  */
 150 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
 151                             int devad, int addr, u32 data)
 152 {
 153         /* Write the desired MMD Devad */
 154         phy_write(phydev, addr, MII_MMD_CTRL, devad);
 155
 156         /* Write the desired MMD register address */
 157         phy_write(phydev, addr, MII_MMD_DATA, prtad);
 158
 159         /* Select the Function : DATA with no post increment */
 160         phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
 161
 162         /* Write the data into MMD's selected register */
 163         phy_write(phydev, addr, MII_MMD_DATA, data);
 164 }
 165
 166 #if defined(CONFIG_DM_ETH)
 167 /**
 168  * dp83867_data_init - Convenience function for setting PHY specific data
 169  *
 170  * @phydev: the phy_device struct
 171  */
 172 static int dp83867_of_init(struct phy_device *phydev)
 173 {
 174         struct dp83867_private *dp83867 = phydev->priv;
 175         struct udevice *dev = phydev->dev;
 176         ofnode node = dev_ofnode(dev);
 177
 178         if (ofnode_read_bool(node, "ti,max-output-impedance"))
 179                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 180         else if (ofnode_read_bool(node, "ti,min-output-impedance"))
 181                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 182         else
 183                 dp83867->io_impedance = -EINVAL;
 184
 185         if (ofnode_read_bool(node, "ti,dp83867-rxctrl-strap-quirk"))
 186                 dp83867->rxctrl_strap_quirk = true;
 187         dp83867->rx_id_delay = ofnode_read_u32_default(node,
 188                                                        "ti,rx-internal-delay",
 189                                                        -1);
 190
 191         dp83867->tx_id_delay = ofnode_read_u32_default(node,
 192                                                        "ti,tx-internal-delay",
 193                                                        -1);
 194
 195         dp83867->fifo_depth = ofnode_read_u32_default(node, "ti,fifo-depth",
 196                                                       -1);
 197
 198         return 0;
 199 }
 200 #else
 201 static int dp83867_of_init(struct phy_device *phydev)
 202 {
 203         struct dp83867_private *dp83867 = phydev->priv;
 204
 205         dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
 206         dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
 207         dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
 208         dp83867->io_impedance = -EINVAL;
 209
 210         return 0;
 211 }
 212 #endif
 213
 214 static int dp83867_config(struct phy_device *phydev)
 215 {
 216         struct dp83867_private *dp83867;
 217         unsigned int val, delay, cfg2;
 218         int ret;
 219
 220         if (!phydev->priv) {
 221                 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
 222                 if (!dp83867)
 223                         return -ENOMEM;
 224
 225                 phydev->priv = dp83867;
 226                 ret = dp83867_of_init(phydev);
 227                 if (ret)
 228                         goto err_out;
 229         } else {
 230                 dp83867 = (struct dp83867_private *)phydev->priv;
 231         }
 232
 233         /* Restart the PHY.  */
 234         val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 235         phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
 236                   val | DP83867_SW_RESTART);
 237
 238         /* Mode 1 or 2 workaround */
 239         if (dp83867->rxctrl_strap_quirk) {
 240                 val = phy_read_mmd_indirect(phydev, DP83867_CFG4,
 241                                             DP83867_DEVADDR, phydev->addr);
 242                 val &= ~BIT(7);
 243                 phy_write_mmd_indirect(phydev, DP83867_CFG4,
 244                                        DP83867_DEVADDR, phydev->addr, val);
 245         }
 246
 247         if (phy_interface_is_rgmii(phydev)) {
 248                 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 249                         (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
 250                         (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 251                 if (ret)
 252                         goto err_out;
 253         } else if (phy_interface_is_sgmii(phydev)) {
 254                 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 255                           (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 256
 257                 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2);
 258                 cfg2 &= MII_DP83867_CFG2_MASK;
 259                 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN |
 260                          MII_DP83867_CFG2_SGMII_AUTONEGEN |
 261                          MII_DP83867_CFG2_SPEEDOPT_ENH |
 262                          MII_DP83867_CFG2_SPEEDOPT_CNT |
 263                          MII_DP83867_CFG2_SPEEDOPT_INTLOW);
 264                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2);
 265
 266                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 267                                        DP83867_DEVADDR, phydev->addr, 0x0);
 268
 269                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 270                           DP83867_PHYCTRL_SGMIIEN |
 271                           (DP83867_MDI_CROSSOVER_MDIX <<
 272                           DP83867_MDI_CROSSOVER) |
 273                           (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
 274                           (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 275                 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 276         }
 277
 278         if (phy_interface_is_rgmii(phydev)) {
 279                 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 280                                             DP83867_DEVADDR, phydev->addr);
 281
 282                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 283                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
 284                                 DP83867_RGMII_RX_CLK_DELAY_EN);
 285
 286                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 287                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 288
 289                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 290                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 291
 292                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 293                                        DP83867_DEVADDR, phydev->addr, val);
 294
 295                 delay = (dp83867->rx_id_delay |
 296                          (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 297
 298                 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 299                                        DP83867_DEVADDR, phydev->addr, delay);
 300
 301                 if (dp83867->io_impedance >= 0) {
 302                         val = phy_read_mmd_indirect(phydev,
 303                                                     DP83867_IO_MUX_CFG,
 304                                                     DP83867_DEVADDR,
 305                                                     phydev->addr);
 306                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 307                         val |= dp83867->io_impedance &
 308                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 309                         phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 310                                                DP83867_DEVADDR, phydev->addr,
 311                                                val);
 312                 }
 313         }
 314
 315         genphy_config_aneg(phydev);
 316         return 0;
 317
 318 err_out:
 319         kfree(dp83867);
 320         return ret;
 321 }
 322
 323 static struct phy_driver DP83867_driver = {
 324         .name = "TI DP83867",
 325         .uid = 0x2000a231,
 326         .mask = 0xfffffff0,
 327         .features = PHY_GBIT_FEATURES,
 328         .config = &dp83867_config,
 329         .startup = &genphy_startup,
 330         .shutdown = &genphy_shutdown,
 331 };
 332
 333 int phy_ti_init(void)
 334 {
 335         phy_register(&DP83867_driver);
 336         return 0;
 337 }