1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
7 * Copyright 2016 Karsten Merker <merker@debian.org>
10 #include <linux/bitops.h>
13 #define PHY_RTL8211x_FORCE_MASTER BIT(1)
14 #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
16 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
18 /* RTL8211x 1000BASE-T Control Register */
19 #define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
20 #define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
22 /* RTL8211x PHY Status Register */
23 #define MIIM_RTL8211x_PHY_STATUS 0x11
24 #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
25 #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
26 #define MIIM_RTL8211x_PHYSTAT_100 0x4000
27 #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
28 #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
29 #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
31 /* RTL8211x PHY Interrupt Enable Register */
32 #define MIIM_RTL8211x_PHY_INER 0x12
33 #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
34 #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
36 /* RTL8211x PHY Interrupt Status Register */
37 #define MIIM_RTL8211x_PHY_INSR 0x13
39 /* RTL8211F PHY Status Register */
40 #define MIIM_RTL8211F_PHY_STATUS 0x1a
41 #define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
42 #define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
43 #define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
44 #define MIIM_RTL8211F_PHYSTAT_100 0x0010
45 #define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
46 #define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
47 #define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
49 #define MIIM_RTL8211E_CONFREG 0x1c
50 #define MIIM_RTL8211E_CONFREG_TXD 0x0002
51 #define MIIM_RTL8211E_CONFREG_RXD 0x0004
52 #define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
54 #define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
56 #define MIIM_RTL8211F_PAGE_SELECT 0x1f
57 #define MIIM_RTL8211F_TX_DELAY 0x100
58 #define MIIM_RTL8211F_LCR 0x10
60 static int rtl8211f_phy_extread(struct phy_device *phydev, int addr,
61 int devaddr, int regnum)
63 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
64 MIIM_RTL8211F_PAGE_SELECT);
67 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
68 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum);
69 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
74 static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr,
75 int devaddr, int regnum, u16 val)
77 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE,
78 MIIM_RTL8211F_PAGE_SELECT);
80 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr);
81 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val);
82 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage);
87 static int rtl8211b_probe(struct phy_device *phydev)
89 #ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
90 phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
96 static int rtl8211e_probe(struct phy_device *phydev)
98 #ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
99 phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
105 /* RealTek RTL8211x */
106 static int rtl8211x_config(struct phy_device *phydev)
108 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
110 /* mask interrupt at init; if the interrupt is
111 * needed indeed, it should be explicitly enabled
113 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
114 MIIM_RTL8211x_PHY_INTR_DIS);
116 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
119 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
120 /* force manual master/slave configuration */
121 reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
122 /* force master mode */
123 reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
124 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
126 if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
129 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
131 phy_write(phydev, MDIO_DEVAD_NONE,
132 MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
133 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
134 /* Ensure both internal delays are turned off */
135 reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
136 /* Flip the magic undocumented bits */
137 reg |= MIIM_RTL8211E_CONFREG_MAGIC;
138 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
139 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
142 /* read interrupt status just to clear it */
143 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
145 genphy_config_aneg(phydev);
150 static int rtl8211f_config(struct phy_device *phydev)
154 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
156 phy_write(phydev, MDIO_DEVAD_NONE,
157 MIIM_RTL8211F_PAGE_SELECT, 0xd08);
158 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
160 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
161 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
162 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
163 reg |= MIIM_RTL8211F_TX_DELAY;
165 reg &= ~MIIM_RTL8211F_TX_DELAY;
167 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
168 /* restore to default page 0 */
169 phy_write(phydev, MDIO_DEVAD_NONE,
170 MIIM_RTL8211F_PAGE_SELECT, 0x0);
172 /* Set green LED for Link, yellow LED for Active */
173 phy_write(phydev, MDIO_DEVAD_NONE,
174 MIIM_RTL8211F_PAGE_SELECT, 0xd04);
175 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
176 phy_write(phydev, MDIO_DEVAD_NONE,
177 MIIM_RTL8211F_PAGE_SELECT, 0x0);
179 genphy_config_aneg(phydev);
184 static int rtl8211x_parse_status(struct phy_device *phydev)
187 unsigned int mii_reg;
189 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
191 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
194 /* in case of timeout ->link is cleared */
196 puts("Waiting for PHY realtime link");
197 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
198 /* Timeout reached ? */
199 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
200 puts(" TIMEOUT !\n");
205 if ((i++ % 1000) == 0)
207 udelay(1000); /* 1 ms */
208 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
209 MIIM_RTL8211x_PHY_STATUS);
212 udelay(500000); /* another 500 ms (results in faster booting) */
214 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
220 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
221 phydev->duplex = DUPLEX_FULL;
223 phydev->duplex = DUPLEX_HALF;
225 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
228 case MIIM_RTL8211x_PHYSTAT_GBIT:
229 phydev->speed = SPEED_1000;
231 case MIIM_RTL8211x_PHYSTAT_100:
232 phydev->speed = SPEED_100;
235 phydev->speed = SPEED_10;
241 static int rtl8211f_parse_status(struct phy_device *phydev)
244 unsigned int mii_reg;
247 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
248 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
251 while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
252 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
253 puts(" TIMEOUT !\n");
258 if ((i++ % 1000) == 0)
261 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
262 MIIM_RTL8211F_PHY_STATUS);
265 if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
266 phydev->duplex = DUPLEX_FULL;
268 phydev->duplex = DUPLEX_HALF;
270 speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
273 case MIIM_RTL8211F_PHYSTAT_GBIT:
274 phydev->speed = SPEED_1000;
276 case MIIM_RTL8211F_PHYSTAT_100:
277 phydev->speed = SPEED_100;
280 phydev->speed = SPEED_10;
286 static int rtl8211x_startup(struct phy_device *phydev)
290 /* Read the Status (2x to make sure link is right) */
291 ret = genphy_update_link(phydev);
295 return rtl8211x_parse_status(phydev);
298 static int rtl8211e_startup(struct phy_device *phydev)
302 ret = genphy_update_link(phydev);
306 return genphy_parse_link(phydev);
309 static int rtl8211f_startup(struct phy_device *phydev)
313 /* Read the Status (2x to make sure link is right) */
314 ret = genphy_update_link(phydev);
317 /* Read the Status (2x to make sure link is right) */
319 return rtl8211f_parse_status(phydev);
322 /* Support for RTL8211B PHY */
323 static struct phy_driver RTL8211B_driver = {
324 .name = "RealTek RTL8211B",
327 .features = PHY_GBIT_FEATURES,
328 .probe = &rtl8211b_probe,
329 .config = &rtl8211x_config,
330 .startup = &rtl8211x_startup,
331 .shutdown = &genphy_shutdown,
334 /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
335 static struct phy_driver RTL8211E_driver = {
336 .name = "RealTek RTL8211E",
339 .features = PHY_GBIT_FEATURES,
340 .probe = &rtl8211e_probe,
341 .config = &rtl8211x_config,
342 .startup = &rtl8211e_startup,
343 .shutdown = &genphy_shutdown,
346 /* Support for RTL8211DN PHY */
347 static struct phy_driver RTL8211DN_driver = {
348 .name = "RealTek RTL8211DN",
351 .features = PHY_GBIT_FEATURES,
352 .config = &rtl8211x_config,
353 .startup = &rtl8211x_startup,
354 .shutdown = &genphy_shutdown,
357 /* Support for RTL8211F PHY */
358 static struct phy_driver RTL8211F_driver = {
359 .name = "RealTek RTL8211F",
362 .features = PHY_GBIT_FEATURES,
363 .config = &rtl8211f_config,
364 .startup = &rtl8211f_startup,
365 .shutdown = &genphy_shutdown,
366 .readext = &rtl8211f_phy_extread,
367 .writeext = &rtl8211f_phy_extwrite,
370 int phy_realtek_init(void)
372 phy_register(&RTL8211B_driver);
373 phy_register(&RTL8211E_driver);
374 phy_register(&RTL8211F_driver);
375 phy_register(&RTL8211DN_driver);