1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc.
7 * Copyright 2016 Karsten Merker <merker@debian.org>
10 #include <linux/bitops.h>
13 #define PHY_RTL8211x_FORCE_MASTER BIT(1)
14 #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2)
16 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
18 /* RTL8211x 1000BASE-T Control Register */
19 #define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12);
20 #define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11);
22 /* RTL8211x PHY Status Register */
23 #define MIIM_RTL8211x_PHY_STATUS 0x11
24 #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000
25 #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000
26 #define MIIM_RTL8211x_PHYSTAT_100 0x4000
27 #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000
28 #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800
29 #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400
31 /* RTL8211x PHY Interrupt Enable Register */
32 #define MIIM_RTL8211x_PHY_INER 0x12
33 #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01
34 #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000
36 /* RTL8211x PHY Interrupt Status Register */
37 #define MIIM_RTL8211x_PHY_INSR 0x13
39 /* RTL8211F PHY Status Register */
40 #define MIIM_RTL8211F_PHY_STATUS 0x1a
41 #define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000
42 #define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030
43 #define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020
44 #define MIIM_RTL8211F_PHYSTAT_100 0x0010
45 #define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008
46 #define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800
47 #define MIIM_RTL8211F_PHYSTAT_LINK 0x0004
49 #define MIIM_RTL8211E_CONFREG 0x1c
50 #define MIIM_RTL8211E_CONFREG_TXD 0x0002
51 #define MIIM_RTL8211E_CONFREG_RXD 0x0004
52 #define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */
54 #define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e
56 #define MIIM_RTL8211F_PAGE_SELECT 0x1f
57 #define MIIM_RTL8211F_TX_DELAY 0x100
58 #define MIIM_RTL8211F_LCR 0x10
60 static int rtl8211b_probe(struct phy_device *phydev)
62 #ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER
63 phydev->flags |= PHY_RTL8211x_FORCE_MASTER;
69 static int rtl8211e_probe(struct phy_device *phydev)
71 #ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX
72 phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX;
78 /* RealTek RTL8211x */
79 static int rtl8211x_config(struct phy_device *phydev)
81 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
83 /* mask interrupt at init; if the interrupt is
84 * needed indeed, it should be explicitly enabled
86 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER,
87 MIIM_RTL8211x_PHY_INTR_DIS);
89 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) {
92 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
93 /* force manual master/slave configuration */
94 reg |= MIIM_RTL8211x_CTRL1000T_MSCE;
95 /* force master mode */
96 reg |= MIIM_RTL8211x_CTRL1000T_MASTER;
97 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
99 if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) {
102 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
104 phy_write(phydev, MDIO_DEVAD_NONE,
105 MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4);
106 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG);
107 /* Ensure both internal delays are turned off */
108 reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD);
109 /* Flip the magic undocumented bits */
110 reg |= MIIM_RTL8211E_CONFREG_MAGIC;
111 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg);
112 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT,
115 /* read interrupt status just to clear it */
116 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER);
118 genphy_config_aneg(phydev);
123 static int rtl8211f_config(struct phy_device *phydev)
127 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
129 phy_write(phydev, MDIO_DEVAD_NONE,
130 MIIM_RTL8211F_PAGE_SELECT, 0xd08);
131 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
133 /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */
134 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
135 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
136 reg |= MIIM_RTL8211F_TX_DELAY;
138 reg &= ~MIIM_RTL8211F_TX_DELAY;
140 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg);
141 /* restore to default page 0 */
142 phy_write(phydev, MDIO_DEVAD_NONE,
143 MIIM_RTL8211F_PAGE_SELECT, 0x0);
145 /* Set green LED for Link, yellow LED for Active */
146 phy_write(phydev, MDIO_DEVAD_NONE,
147 MIIM_RTL8211F_PAGE_SELECT, 0xd04);
148 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f);
149 phy_write(phydev, MDIO_DEVAD_NONE,
150 MIIM_RTL8211F_PAGE_SELECT, 0x0);
152 genphy_config_aneg(phydev);
157 static int rtl8211x_parse_status(struct phy_device *phydev)
160 unsigned int mii_reg;
162 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS);
164 if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
167 /* in case of timeout ->link is cleared */
169 puts("Waiting for PHY realtime link");
170 while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) {
171 /* Timeout reached ? */
172 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
173 puts(" TIMEOUT !\n");
178 if ((i++ % 1000) == 0)
180 udelay(1000); /* 1 ms */
181 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
182 MIIM_RTL8211x_PHY_STATUS);
185 udelay(500000); /* another 500 ms (results in faster booting) */
187 if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK)
193 if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX)
194 phydev->duplex = DUPLEX_FULL;
196 phydev->duplex = DUPLEX_HALF;
198 speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED);
201 case MIIM_RTL8211x_PHYSTAT_GBIT:
202 phydev->speed = SPEED_1000;
204 case MIIM_RTL8211x_PHYSTAT_100:
205 phydev->speed = SPEED_100;
208 phydev->speed = SPEED_10;
214 static int rtl8211f_parse_status(struct phy_device *phydev)
217 unsigned int mii_reg;
220 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43);
221 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS);
224 while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) {
225 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
226 puts(" TIMEOUT !\n");
231 if ((i++ % 1000) == 0)
234 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
235 MIIM_RTL8211F_PHY_STATUS);
238 if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX)
239 phydev->duplex = DUPLEX_FULL;
241 phydev->duplex = DUPLEX_HALF;
243 speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED);
246 case MIIM_RTL8211F_PHYSTAT_GBIT:
247 phydev->speed = SPEED_1000;
249 case MIIM_RTL8211F_PHYSTAT_100:
250 phydev->speed = SPEED_100;
253 phydev->speed = SPEED_10;
259 static int rtl8211x_startup(struct phy_device *phydev)
263 /* Read the Status (2x to make sure link is right) */
264 ret = genphy_update_link(phydev);
268 return rtl8211x_parse_status(phydev);
271 static int rtl8211e_startup(struct phy_device *phydev)
275 ret = genphy_update_link(phydev);
279 return genphy_parse_link(phydev);
282 static int rtl8211f_startup(struct phy_device *phydev)
286 /* Read the Status (2x to make sure link is right) */
287 ret = genphy_update_link(phydev);
290 /* Read the Status (2x to make sure link is right) */
292 return rtl8211f_parse_status(phydev);
295 /* Support for RTL8211B PHY */
296 static struct phy_driver RTL8211B_driver = {
297 .name = "RealTek RTL8211B",
300 .features = PHY_GBIT_FEATURES,
301 .probe = &rtl8211b_probe,
302 .config = &rtl8211x_config,
303 .startup = &rtl8211x_startup,
304 .shutdown = &genphy_shutdown,
307 /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */
308 static struct phy_driver RTL8211E_driver = {
309 .name = "RealTek RTL8211E",
312 .features = PHY_GBIT_FEATURES,
313 .probe = &rtl8211e_probe,
314 .config = &rtl8211x_config,
315 .startup = &rtl8211e_startup,
316 .shutdown = &genphy_shutdown,
319 /* Support for RTL8211DN PHY */
320 static struct phy_driver RTL8211DN_driver = {
321 .name = "RealTek RTL8211DN",
324 .features = PHY_GBIT_FEATURES,
325 .config = &rtl8211x_config,
326 .startup = &rtl8211x_startup,
327 .shutdown = &genphy_shutdown,
330 /* Support for RTL8211F PHY */
331 static struct phy_driver RTL8211F_driver = {
332 .name = "RealTek RTL8211F",
335 .features = PHY_GBIT_FEATURES,
336 .config = &rtl8211f_config,
337 .startup = &rtl8211f_startup,
338 .shutdown = &genphy_shutdown,
341 int phy_realtek_init(void)
343 phy_register(&RTL8211B_driver);
344 phy_register(&RTL8211E_driver);
345 phy_register(&RTL8211F_driver);
346 phy_register(&RTL8211DN_driver);