1 // SPDX-License-Identifier: GPL-2.0+
3 * National Semiconductor PHY drivers
5 * Copyright 2010-2011 Freescale Semiconductor, Inc.
12 #define DP83630_PHY_PAGESEL_REG 0x13
13 #define DP83630_PHY_PTP_COC_REG 0x14
14 #define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
15 #define DP83630_PHY_RBR_REG 0x17
17 static int dp83630_config(struct phy_device *phydev)
21 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
22 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
23 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
24 DP83630_PHY_PTP_COC_REG);
25 ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
26 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
28 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
30 genphy_config_aneg(phydev);
35 static struct phy_driver DP83630_driver = {
36 .name = "NatSemi DP83630",
39 .features = PHY_BASIC_FEATURES,
40 .config = &dp83630_config,
41 .startup = &genphy_startup,
42 .shutdown = &genphy_shutdown,
46 /* DP83865 Link and Auto-Neg Status Register */
47 #define MIIM_DP83865_LANR 0x11
48 #define MIIM_DP83865_SPD_MASK 0x0018
49 #define MIIM_DP83865_SPD_1000 0x0010
50 #define MIIM_DP83865_SPD_100 0x0008
51 #define MIIM_DP83865_DPX_FULL 0x0002
55 static int dp838xx_config(struct phy_device *phydev)
57 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
58 genphy_config_aneg(phydev);
63 static int dp83865_parse_status(struct phy_device *phydev)
67 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
69 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
71 case MIIM_DP83865_SPD_1000:
72 phydev->speed = SPEED_1000;
75 case MIIM_DP83865_SPD_100:
76 phydev->speed = SPEED_100;
80 phydev->speed = SPEED_10;
85 if (mii_reg & MIIM_DP83865_DPX_FULL)
86 phydev->duplex = DUPLEX_FULL;
88 phydev->duplex = DUPLEX_HALF;
93 static int dp83865_startup(struct phy_device *phydev)
97 ret = genphy_update_link(phydev);
101 return dp83865_parse_status(phydev);
105 static struct phy_driver DP83865_driver = {
106 .name = "NatSemi DP83865",
109 .features = PHY_GBIT_FEATURES,
110 .config = &dp838xx_config,
111 .startup = &dp83865_startup,
112 .shutdown = &genphy_shutdown,
115 /* NatSemi DP83848 */
116 static int dp83848_parse_status(struct phy_device *phydev)
120 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
122 if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) {
123 phydev->speed = SPEED_100;
125 phydev->speed = SPEED_10;
128 if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) {
129 phydev->duplex = DUPLEX_FULL;
131 phydev->duplex = DUPLEX_HALF;
137 static int dp83848_startup(struct phy_device *phydev)
141 ret = genphy_update_link(phydev);
145 return dp83848_parse_status(phydev);
148 static struct phy_driver DP83848_driver = {
149 .name = "NatSemi DP83848",
152 .features = PHY_BASIC_FEATURES,
153 .config = &dp838xx_config,
154 .startup = &dp83848_startup,
155 .shutdown = &genphy_shutdown,
158 int phy_natsemi_init(void)
160 phy_register(&DP83630_driver);
161 phy_register(&DP83865_driver);
162 phy_register(&DP83848_driver);